1254799 (1) 九、發明說明 【發明所屬之技術領域】 本發明係關於半導體裝置及其試驗方法，特別是關於 有效使用於具有驅動液晶面板的閘極線之功能的L c D (液 晶顯示器）驅動器等之半導體裝置及其試驗方法之技術。 【先前技術】 本發明人利用第1 6圖〜第1 9圖來說明作爲本發明之前 提而所檢討之技術。第1 6圖係顯示液晶面板與l C D驅動 器之連接關係，第1 7圖係顯示LCD驅動器與半導體試驗 裝置之連接關係，第18圖係第17圖之反相器電路3之構造 ，第1 9圖係顯示L C D驅動器之閘極輸出的動作圖。 如第1 6圖所示般，液晶面板5 0 0係與驅動此液晶所必 要之L C D驅動器連接。電晶體5 1 1與電容器5 1 2係以如圖 示之形式配置在液晶面板500之各畫素510，圖示之垂直方 向的各電晶體之源極端子係被共通化。同樣地，圖示之水 平方向的各電晶體之閘極端子也被共通化。 一般，在驅動液晶面板5 0 0上，需要有連接於源極共 通端子，具有施加於成爲顏色顯示資訊之灰階電壓的功能 之源極驅動器5 0 1，及連接於閘極共通端子，具有進行圖 示之水平方向的畫素之顯示控制之功能的閘極驅動器5 02 ，及具有產生使源極驅動器501與閘極驅動器5 02動作所必 要之電壓的功能之電源電路5 03。這些一般稱爲LCD驅動 器，源極驅動器5 0 1、閘極驅動器5 0 2、電源電路5 0 3有各 (2) (2)1254799 爲個別集成化之情形，及匯集幾個功能而集成化於1個晶 片上之情形。 如第1 7圖所示般，在實施電氣動作試驗時，具有驅動 液晶面板的閘極共通端子所必要之功能的LCD驅動器（ 電源電路內藏型閘極驅動器）1 f係連接於半導體試驗裝 置1 〇〇，在此連接狀態下實施電氣動作試驗。LCD驅動器 If之輸出段之反相器電路（輸出電路）30係如第18圖所 示般，以位準移位電路40，及p通道型電晶體50，及η通 道型電晶體51所構成，爲因應輸入位準H/L而由閘極輸出 端子Gx輸出正電壓VGH或負電壓VGL之構造。 第17圖中，LCD驅動器If之閘極輸出端子G1〜Gn係 進行液晶面板之各1線（第1 6圖所示之水平方向的1行之畫 素）之顯示/非顯示的控制。因此，如第1 9圖所示般，即 使LCD驅動器1 f之計數値（設定狀態）改變，複數的閘 極輸出端子G1〜Gn中，一定有1端子爲正電壓VGH (顯不 電壓）輸出，另外爲負電壓VGL (非顯示電壓）輸出’ 如此排它地輸出電壓而動作。 此種L C D驅動器1 f之試驗係如第1 7圖所示般，將各 閘極輸出端子G1〜Gn分別連接於半導體試驗裝置1〇〇的比 較器1 〇 3，各閘極輸出端子G 1〜Gn的電壓値係以半導體試 驗裝置100來判定爲正電壓VGH或負電壓VGL。而且， L C D驅動器1 f在第1 9圖所示之全部的計數値（設定狀態 )狀態中，圖示之電壓値如由各閘極輸出端子G1〜Gn所 輸出時，則判定關於此LCD驅動器1 f之閘極輸出的功能 -6 - (3) (3)1254799 並無不良，結束關於閘極輸出之試驗。 另一方面，液晶面板的高精細化往前邁進，LCD驅動 器的輸出接腳數有增加的傾向。習知的LCD驅動器之試 驗方法如前述般，係將各閘極輸出端子與半導體試驗裝置 的比較器連接以實施試驗。另外，使LCD驅動器動作用 之輸入接腳也同樣由半導體試驗裝置所施加故，輸入接腳 數也需要分配半導體試驗裝置的通道數。因此，具備LCD 驅動器之輸入輸出接腳數以上之通道之半導體試驗裝置成 爲必要，例如，在2 5 6通道搭載之半導體試驗裝置中，無 法試驗閘極輸出數3 5 0接腳之LCD驅動器，會有無法在該 半導體試驗裝置中進行試驗之問題。 進而，在驅動搭載於行動電話等之小型機器的液晶面 板之L C D驅動器中，以機器的小型化爲目的，有將驅動 液晶面板所必要之全部的功能（源極、閘極、電源電路等 )集積化在1個晶片上之傾向’ L C D驅動器之接腳數的總 和增加。因此，需要藉由搭載多數之通道數之高價的半導 體試驗裝置之新購入，或半導體試驗裝置製造商所販賣之 選購品等的購入，以增加半導體試驗裝置的通道數，會有 無法降低LCD驅動器的製造成本之問題。 作爲解決此問題之方法，例如在專利文獻1揭示有， 在被試驗元件與半導體試驗裝置之間設置切換開關之技術 。具體爲揭示：此切換開關依據來自半導體試驗裝置內的 C P U之切換訊號，一面依序切換半導體試驗裝置內的比較 器與半導體裝置的輸出接腳之各連接，一面進行試驗。因 1254799BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a test method thereof, and more particularly to an L c D (Liquid Crystal Display) which is effectively used for a function of a gate line for driving a liquid crystal panel. The technology of a semiconductor device such as a driver and a test method thereof. [Prior Art] The inventors of the present invention have explained the technique reviewed prior to the present invention by using Figs. 16 to 1.9. Figure 16 shows the connection between the LCD panel and the CD driver. Figure 17 shows the connection between the LCD driver and the semiconductor test device. Figure 18 shows the structure of the inverter circuit 3 in Figure 17. Figure 9 shows the action diagram of the gate output of the LCD driver. As shown in Fig. 16, the liquid crystal panel 500 is connected to the L C D driver necessary to drive the liquid crystal. The transistor 51 1 and the capacitor 5 1 2 are arranged in the form of the respective pixels 510 of the liquid crystal panel 500, and the source terminals of the respective transistors in the vertical direction are shown to be common. Similarly, the gate terminals of the respective transistors in the horizontal direction shown in the figure are also common. Generally, in driving the liquid crystal panel 500, it is necessary to have a source driver 510 connected to the source common terminal, having a function of applying a gray scale voltage as color display information, and a common terminal connected to the gate. A gate driver 502 for performing a display control function of a pixel in the horizontal direction and a power supply circuit 503 having a function of generating a voltage necessary for operating the source driver 501 and the gate driver 502. These are generally referred to as LCD drivers, source driver 5 0 1 , gate driver 5 0 2, power supply circuit 5 0 3 have (2) (2) 1254799 for individual integration, and integrate several functions to integrate On the case of one wafer. As shown in FIG. 7 , an LCD driver (power supply circuit built-in gate driver) 1 f having a function necessary for driving the gate common terminal of the liquid crystal panel is connected to the semiconductor test device during the electrical operation test. 1 〇〇, perform an electrical action test in this connected state. The inverter circuit (output circuit) 30 of the output section of the LCD driver If is formed by the level shift circuit 40, the p-channel type transistor 50, and the n-channel type transistor 51 as shown in FIG. A configuration in which a positive voltage VGH or a negative voltage VGL is output from the gate output terminal Gx in response to the input level H/L. In Fig. 17, the gate output terminals G1 to Gn of the LCD driver If perform display/non-display control of one line of each of the liquid crystal panels (pixels in the horizontal direction shown in Fig. 6). Therefore, as shown in Fig. 19, even if the count 値 (set state) of the LCD driver 1 f is changed, one of the plurality of gate output terminals G1 to Gn must have a positive voltage VGH (display voltage) output. In addition, the negative voltage VGL (non-display voltage) output 'acts so exclusively for outputting voltage. In the test of the LCD driver 1f, as shown in FIG. 7, each of the gate output terminals G1 to Gn is connected to the comparator 1 〇3 of the semiconductor test apparatus 1A, and each gate output terminal G1. The voltage 〜 of Gn is determined by the semiconductor test apparatus 100 as a positive voltage VGH or a negative voltage VGL. Further, in the state of all the counts (set state) of the LCD driver 1 f shown in FIG. 9, when the voltages shown are output from the gate output terminals G1 to Gn, it is determined about the LCD driver. 1 f gate output function -6 - (3) (3) 1254799 There is no defect, and the test on the gate output is ended. On the other hand, the high definition of the liquid crystal panel is moving forward, and the number of output pins of the LCD driver tends to increase. The conventional LCD driver test method is as described above, in which each gate output terminal is connected to a comparator of a semiconductor test apparatus to carry out a test. Further, the input pin for operating the LCD driver is similarly applied by the semiconductor test apparatus, and the number of input pins also needs to be allocated to the number of channels of the semiconductor test apparatus. Therefore, it is necessary to have a semiconductor test device having a channel with more than one input/output pin of the LCD driver. For example, in a semiconductor test device equipped with 256 channels, it is not possible to test an LCD driver with a gate output of 305 pins. There is a problem that it is impossible to test in the semiconductor test apparatus. Furthermore, in the LCD driver for driving a liquid crystal panel mounted on a small device such as a mobile phone, for the purpose of miniaturization of the device, there are all functions (source, gate, power supply circuit, etc.) necessary for driving the liquid crystal panel. The tendency to accumulate on one wafer increases the sum of the number of pins of the LCD driver. Therefore, it is necessary to increase the number of channels of the semiconductor test device by purchasing a new semiconductor test device with a large number of channels, or purchasing a product purchased by a semiconductor test device manufacturer, and the LCD cannot be lowered. The problem of manufacturing cost of the drive. As a method for solving this problem, for example, Patent Document 1 discloses a technique of providing a changeover switch between a device under test and a semiconductor test device. Specifically, it is revealed that the switch performs a test while sequentially switching the connection between the comparator in the semiconductor test device and the output pin of the semiconductor device in accordance with the switching signal from the C P U in the semiconductor test device. Because 1254799
此，半導體裝置的輸出接腳數即使超過半導體試驗裝置的 通道數，也可以進行試驗。 [專利文獻1]日本專利特開平1 0-2665 5號公報 【發明內容】 但是’使用前述專利文獻1所記載之技術，試驗超過 半導體試驗裝置之通道的輸出接腳數之半導體裝置時，由 於係一面以開關依序進行切換，一面實施試驗故，比起習 知者，會導致試驗時間的增加，變成提高測試成本之原因 。例如，在具有3 5 0接腳之閘極輸出的LCD驅動器之閘極 輸出試驗，利用專利文獻1之技術，使用半導體裝置的1 0 通道而試驗之情形，需要習知之3 5倍的試驗時間。因此， 產生無法降低半導體裝置之製造成本的問題。 因此，本發明係有鑑於前述問題，目的在於提供：彙 集複數的輸出接腳，以比半導體裝置的輸出接腳數少之半 導體試驗裝置之通道數，可以實施複數的輸出接腳之同時 試驗之半導體裝置，及其之試驗方法。特別是目的在於提 供：適合於具有驅動液晶面板的閘極線之功能的L C D驅 動器之半導體裝置，及其之試驗方法。 如簡單說明在本申請案所揭示發明中之代表性者的槪 要，則如下述： 即本發明係具備：適用於具有驅動液晶面板的閘極線 之功能的半導體裝置，使驅動閘極線之正電壓及負電壓之 極性反轉之極性反轉電路，及可將驅動閘極線用之輸出電 (5) (5)1254799 路控制爲高阻抗狀態之狀態設定電路，及控制極性反轉電 路與狀態設定電路的狀態用之至少1個之控制端子。 另外’本發明係適用於具有驅動液晶面板的閘極線之 功能的半導體裝置，具備：使驅動閘極線之正電壓及負電 壓之極性反轉之極性反轉電路，及可將驅動閘極線用之輸 出電路控制在高阻抗狀態之電晶體，及爲了控制極性反轉 電路與電晶體之狀態，至少1個之控制端子。 進而，本發明係適用於具有驅動液晶面板之閘極線的 功能之半導體裝置之試驗方法，將驅動閘極線之複數的輸 出端子之輸出控制爲正電壓輸出及高阻抗狀態，或者負電 壓輸出及高阻抗狀態，通過設置在半導體裝置的內部或外 部之電阻電路網，以比半導體裝置的輸出端子數少之半導 體試驗裝置的通道數’實施半導體裝置的複數之輸出端子 的試驗。 如簡單說明由本申請案所揭示發明中的代表性者所獲 得之效果，則如下述： (1 )以比半導體裝置的複數之輸出接腳數少之半導 體試驗裝置之通道數’可以實施複數的輸出接腳之同時試 GE入 驗c (2 )可以有效活用比半導體裝置的接腳數之總和少 的通道數之半導體試驗裝置。 【實施方式】 以下，依據圖面詳細說明本發明之實施形態。另外， -9- (6) (6)1254799 在說明實施形態用之全圖中，對於具有相同功能之構件， 原則上賦予相同符號，省略其之重複說明。 (實施形態1 ) 利用第1圖〜第8圖來說明依據本發明之半導體裝置的 實施形態1之LCD驅動器。第1圖係LCD驅動器的構造圖 ，第2圖係試驗時之等效電路，第3圖係假定故障時之等效 電路，第4圖係控制訊號的設定狀態，第5圖係測試控制電 路的真値表之一例，第6圖係試驗時之動作，第7圖係使電 路規模變小之例子的LCD驅動器之構造，第8圖係第7圖 之反相器電路的電路構造。 本實施形態1之L C D驅動器係如前述第1 6圖所示，爲 適用在驅動液晶面板所必要之源極驅動器、閘極驅動器、 電源電路中，連接於閘極共通端子’具有進行水平方向之 畫素的顯示控制之功能之閘極驅動器’與前述第1 7圖所示 之LCD驅動器不同處爲，如第1圖所示般，變更爲可將輸 出段之反相器電路的輸出切換爲高阻抗狀態之試驗狀態型 反相器電路（狀態設定電路）9，在解碼電路5與閂鎖電路 7之間設置Ex-OR電路（極性反轉電路）6，設置控制這 些用之測試控制電路（控制電路）2與測試控制端子（控 制端子）TEST。 因此，在本實施形態之L C D驅動器中，詳細雖在之 後加以敘述，但是，藉由半導體試驗裝置之試驗時’藉由 只有閘極輸出中之1端子爲正電壓VGH或者負電壓VGL ’ -10- (7) 1254799 其他爲高阻抗狀態，通過電阻電路網而彙集複數的閘 出，以比閘極輸出數少之半導體試驗裝置的通道數， 同時實施複數之閘極輸出的同時試驗。 即本實施形態1之LCD驅動器1係由：連接於測 制端子TEST之測試控制電路2，及連接於此測試控 路2，輸入有輸入訊號之介面電路/暫存器3，及連接 介面電路/暫存器3之計數器4，並聯連接於此計數§ 複數的解碼器電路（DEC ) 5，及連接於各解碼器電g 輸入有來自測試控制電路2之訊號Μ之複數的Ex· OR 6，及連接於各Ex-OR電路6，與時鐘脈衝CLK同步 數的閂鎖電路7，及連接於各閂鎖電路7，藉由來自測 制電路2之設定訊號ΕπΗ/EnL所控制之複數的試驗狀 反相器電路9，及連接於電源端子Vcc，產生正電壓 及負電壓VGL之電源電路1 1等所構成。 在此LCD驅動器1中，輸入訊號係包含有移往液 板之下一線的畫素顯示用之資訊的訊號，依據驅動液 板之各功能是否集成化在同一晶片上，或集成在個別 ，會有由內部電路輸入之情形以及由外部輸入之情形 輸入訊號係藉由介面電路/暫存器3而輸入計數器4， 輸入訊號之變化，計數器4之値被增量而輸入於解碼 路5。而且，在解碼器電路5中，因應計數器4之値， Ex-OR電路6、閂鎖電路7、試驗狀態型反相器電路9 通常動作（第4圖）中，各閘極輸出端子 G1〜Gn VGH/VGL(輸入位準L/H)的輸出電壓般輸出。此通常 極輸 可以 試控 制電 於此 I 4之 $ 5， 電路 之複 試控 態型 VGH 晶面 晶面 晶片 。此 因應 器電 藉由 ，在 成爲 動作 -11 - (8) 1254799 時係來自測試控制電路2之訊號Μ爲“ H”（High位準） EnH爲“ L”（ Low位準）、EnL爲“ H”。關於測試模式 動作，於之後敘述。Therefore, the number of output pins of the semiconductor device can be tested even if it exceeds the number of channels of the semiconductor test device. [Patent Document 1] Japanese Patent Laid-Open Publication No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. When the test is performed by switching the switches one by one, the test is performed, which leads to an increase in the test time and becomes a cause of an increase in the test cost. For example, in the gate output test of an LCD driver having a gate output of a 350 pin, using the technique of Patent Document 1, the test using the 10 channel of the semiconductor device requires a conventional test time of 35 times. . Therefore, there arises a problem that the manufacturing cost of the semiconductor device cannot be reduced. Accordingly, the present invention has been made in view of the above problems, and an object of the invention is to provide a plurality of output pins that can be tested at the same time as a plurality of output pins of a semiconductor test device having a smaller number of output pins than a semiconductor device. Semiconductor device, and test method thereof. In particular, it is an object of the invention to provide a semiconductor device suitable for an L C D driver having a function of driving a gate line of a liquid crystal panel, and a test method therefor. A brief description of a representative of the invention disclosed in the present application is as follows: that is, the present invention is provided with a semiconductor device having a function of driving a gate line of a liquid crystal panel to drive a gate line A polarity inversion circuit in which the polarity of the positive voltage and the negative voltage is reversed, and a state setting circuit capable of controlling the output power (5) (5) 1254799 for driving the gate line to a high impedance state, and controlling the polarity inversion At least one control terminal is used for the state of the circuit and the state setting circuit. Further, the present invention is applied to a semiconductor device having a function of driving a gate line of a liquid crystal panel, and includes a polarity inversion circuit for inverting a polarity of a positive voltage and a negative voltage of a driving gate line, and a driving gate The output circuit for the line controls the transistor in the high impedance state, and at least one control terminal for controlling the state of the polarity inversion circuit and the transistor. Furthermore, the present invention is applicable to a test method for a semiconductor device having a function of driving a gate line of a liquid crystal panel, and controls an output of a plurality of output terminals for driving a gate line to a positive voltage output and a high impedance state, or a negative voltage output. In the high-impedance state, a plurality of output terminals of the semiconductor device are tested by a number of channels of the semiconductor test device having a smaller number of output terminals than the number of output terminals of the semiconductor device through a resistor circuit network provided inside or outside the semiconductor device. The effects obtained by the representative of the invention disclosed in the present application will be briefly described as follows: (1) The number of channels of the semiconductor test device having a smaller number of output pins than the plurality of semiconductor devices can be implemented. At the same time as the output pin, the GE test c (2) can effectively utilize a semiconductor test device having a smaller number of channels than the sum of the number of pins of the semiconductor device. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In the entire description of the embodiments, the same reference numerals will be given to the components having the same functions, and the repeated description thereof will be omitted. (Embodiment 1) An LCD driver according to Embodiment 1 of a semiconductor device according to the present invention will be described with reference to Figs. 1 to 8 . Figure 1 is the structure diagram of the LCD driver, Figure 2 is the equivalent circuit during the test, Figure 3 is the equivalent circuit when the fault is assumed, Figure 4 is the setting state of the control signal, and Figure 5 is the test control circuit. An example of the true table, the sixth figure is the operation at the time of the test, the seventh figure is the structure of the LCD driver which makes the circuit scale smaller, and the figure 8 is the circuit structure of the inverter circuit of the seventh figure. The LCD driver of the first embodiment is applied to the source driver, the gate driver, and the power supply circuit necessary for driving the liquid crystal panel, and is connected to the gate common terminal 'in the horizontal direction as shown in the above-mentioned FIG. The gate driver of the display control function of the pixel is different from the LCD driver shown in the above-mentioned FIG. 7 , and as shown in FIG. 1 , the output of the inverter circuit of the output section can be switched to A test state type inverter circuit (state setting circuit) 9 of a high impedance state, an Ex-OR circuit (polarity inversion circuit) 6 is provided between the decoding circuit 5 and the latch circuit 7, and a test control circuit for controlling these is provided. (Control circuit) 2 and test control terminal (control terminal) TEST. Therefore, in the LCD driver of the present embodiment, although it will be described later in detail, in the test by the semiconductor test apparatus, 'only one of the gate outputs is a positive voltage VGH or a negative voltage VGL ' -10 - (7) 1254799 Others are in a high-impedance state, and a plurality of gates are collected through a resistor network, and the number of channels of the semiconductor test device having a smaller number of gate outputs is simultaneously tested at the same time as the gate output of the plurality of gates. That is, the LCD driver 1 of the first embodiment is composed of a test control circuit 2 connected to the measurement terminal TEST, and a interface circuit/storage device 3 connected to the test control circuit 2, inputting an input signal, and a connection interface circuit. The counter 4 of the register/storage unit 3 is connected in parallel to the decoder circuit (DEC) 5 of the count § complex, and the Ex·OR 6 connected to the complex signal g of each of the decoders and the signal 来自 from the test control circuit 2 And a latch circuit 7 connected to each Ex-OR circuit 6 in synchronization with the clock pulse CLK, and a plurality of latch circuits 7 connected to each latch circuit 7 controlled by the set signal ΕπΗ/EnL from the measurement circuit 2. The test inverter circuit 9 and the power supply circuit 1 1 connected to the power supply terminal Vcc and generating a positive voltage and a negative voltage VGL are formed. In the LCD driver 1, the input signal includes a signal for moving the information for displaying the pixel under the liquid plate, and whether the functions of the driving liquid plate are integrated on the same wafer, or integrated in the individual, The input signal is input from the internal circuit and the input signal is input to the counter 4 through the interface circuit/register 3, and the input signal is changed. The counter 4 is incremented and input to the decoding path 5. Further, in the decoder circuit 5, in response to the counter 4, the Ex-OR circuit 6, the latch circuit 7, and the test state inverter circuit 9 are normally operated (Fig. 4), and the gate output terminals G1 to Gn VGH/VGL (input level L/H) output voltage output. This usually pole-transfer can be used to test and control the V5 crystal face wafer of the circuit. The cause of the response is that the signal from the test control circuit 2 is "H" (High level) when the action is -11 - (8) 1254799. EnH is "L" (low level), and EnL is " H". The test mode action will be described later.
Ex-OR電路6係使驅動液晶面板之閘極線的正電壓 負電壓的極性反轉之極性反轉電路，試驗狀態型反相器 路9係可將驅動閘極線用之輸出電路控制爲高阻抗狀態 狀態設定電路。另外，閂鎖電路（D-正反器電路）7係 在液晶面板的各線之畫素的顯示期間中，保持解碼器電 5之輸出値的目的而所設置。 試驗狀態型反相器電路9係所謂之定時反相器電路 構造，如第2圖所示般，是以：位準移位電路4 0，及構 通常之反相器電路之高耐壓的p通道型電晶體50及60， 高耐壓的η通道型電晶體5 1及6 1所構成。在此試驗狀態 反相器電路9中，藉由在電晶體60及6 1的閘極端子 EnH/EnL)輸入H/L之訊號，如第4圖所示般，因應輸 位準H/L，可以控制爲高阻抗狀態。 另外，使用位準移位電路40及高耐壓的電晶體之目 係如下述：即閘極輸出電壓 VGH/VGL例如比+16.. 16.5V之使LCD驅動器1動作用的電源電壓Vcc高好幾 之電壓故，P通道型電晶體50、60與η通道型電晶體51 61係使用即使在由VGH施加以VGL之電壓，即33V之 壓（通常在此以上之電壓）的情形，也可以保證動作之 耐壓的電晶體。 以第2圖所示之圓形標記所包圍之ρ通道型電晶體 之 及 電 之 以 路 之 成 及 型 ( 入 的 5/- 倍 、 電 高 50 -12- (9) (9)1254799 、6 0及5 1、6 1係顯示使用高耐壓的電晶體。高耐壓的電晶 體係比以施加通常之電源電壓而保證動作之通常的電晶體 尺寸大。因此，如第2圖所示般，設置位準移位電路4 0， 藉由在比位準移位電路40前段之電路使用通常之電晶體， 在比位準移位電路40後段之電路使用高耐壓電晶體，以使 LCD驅動器1的晶片面積變小。 在實施試驗之情形，如第4圖所示之測試模式（1 )般 ，設對於試驗狀態型反相器電路9之設定訊號EnH = EriL = L 。此時，如設E X - Ο R電路6之輸入訊號M = L時，則解碼器 電路5之輸入位準沒有改變，藉由問鎖電路7而輸入於試驗 狀態型反相器電路9。因此，在本設定狀態中，如第6 ( a )圖所示般，可將在通常動作中成爲負電壓輸出VGL之 部份變更爲高阻抗狀態。另外，關於對於試驗狀態型反相 器電路9之設定訊號EnH/EnL以及Ex-OR電路6之訊號Μ 的設定方法之詳細，於之後敘述。 在此種測試模式之狀態設定LCD驅動器，如第1圖所 示般，在各閘極輸出端子G1〜Gn分別連接第1電阻（R1) 1 2，共通連接第1電阻1 2之另一單側，在該共通連接點A 設置以第2電阻（R2 ) 1 3爲終接之電阻電路網。而且’將 連接點 A連接於半導體試驗裝置1 〇 〇之比較器1 〇 3 ’實施 試驗。在L C D驅動器1沒有不良之情形，如第6 ( a )圖所 示般，與計數器4之値無關，只有閘極輸出的1端子爲 V G Η輸出，其他成爲高阻抗狀態故，等效上成爲第2圖所 示電路。即比較器1 0 3的輸入電壓變成電阻1 2的電阻値R 1 -13- (10) 1254799 與電阻1 3的電阻値R2之比，即： VA={R2/(Rl+R2)}xVGH [V] (式 1) ，在第1電阻1 2與第2電阻1 3之電阻値變成相 R1=R2 = R)之情形，VA = (1/2)VGH [V]。 基於解碼器電路5等之故障，與第6(a)圖所元 出電壓狀態不同，在正電壓VGH被輸入於2個以上；^ 輸出的情形，或者電壓未被輸出於全部的閘極輸出二 ，藉由第1圖所示之電阻電路網，與前述電壓不同座 値被輸入於比較器1 〇 3。例如，由於故障，在正電壓 被輸出於閘極輸出中的2端子之情形，等效上成爲第 示電路。此時，如使用米耳曼（Millman )原理時.， 入於比較器1 〇3之連接點A的電壓變成： V A = (2VGH/R1 )/ {(1/R1) + (1/R1)+1/R1}} [V] (式 2) 。在第1電阻1 2與第2電阻1 3的電阻値設爲相同 R1 =R2 = R )之情形，VA = (2/3)VGH [V]，基於在連接 之電壓値，可以判定故障之有無。 在上述說明之試驗中，本來於輸出負電壓VGL 形，藉由將對於試驗狀態型反相器電路9之設定訊费 爲EnH = EnL = L而變更爲高阻抗。在實施此種試驗二 1値（ ；:之輸 L閘極 L情形 J電壓 VGH 3圖所 則輸 値（ 點 A 之情 設定 情形 -14- (11) (11)1254799 ，第2圖所示之η通道型電晶體50經常不動作。因此，爲 了實施η通道型電晶體50之動作試驗，將輸入Ex-OR電 路6之Μ訊號設定爲Η位準，使輸入於試驗狀態型反相器 電路9之H/L的位準反轉。而且，如第4圖之測試模式（2 )所示般，如設對於試驗狀態型反相器電路9之設定訊號 EnH = EnL = H時，則如第6(b)圖所示般，只有閘極輸出 的1端子成爲V GL輸出。輸入於比較器1 〇 3之連接點A的 電壓變成將在前述說明之（式1)及（式2)之VGH變更 爲VGL之値故，同樣地，可以判定故障之有無。 如此，藉由將對於Ex-OR電路6之極性反轉訊號Μ ’ 及試驗狀態型反相器電路9的設定訊號EnH及EnL設定爲 第4圖所示之測試模式（1 )及測試模式（2 ) ’以半導體 試驗裝置之1通道可以同時進行複數的閘極輸出之試驗。 接著，說明對於Ex-OR電路6之Μ訊號’及對於試驗 狀態型反相器電路9之EnH以及EnL訊號之設定。第1圖 係顯示以測試控制電路2產生Μ、EnH以及EnL之訊號的 電路構造。具體爲，於介面電路/暫存器3內準備測試用 暫存器（未圖示出），及測試控制端子TE S T。對於測試 用暫存器之寫入係利用輸入訊號線進行。測試控制端子 T E S T係當成選擇通常動作/測試模式用之控制端子使用 。測試控制電路2例如如第5圖所示般’可因應測試控制端 子與測試用暫存器之設定値，輸出Μ、EnH以及EnL訊 號之電路而構成。 另外，第5圖之測試控制端子TEST以及測試用暫存 -15- (12) (12)1254799 器之設定値與Μ、EnH以及EnL訊號的對應係顯示其之 一例而已，並不限定於此。另外，測試控制電路2雖獨立 而圖示，但是，也可以是例如包含在介面電路/暫存器3 之構造。第2電阻1 3雖係終接在G N D (接地），但是也可以 終接在某任意之電壓。 在本實施形態中，雖圖示因應測試控制端子TE S T及 測試用暫存器之設定値，以測試控制電路2產生測試模式 之切換用的訊號（Μ、EnH、EnL )之例子而做說明，但 是，本發明之目的係在試驗實施時，設定爲第6圖之輸出 狀態（測試模式（1 ) 、（2))而實施試驗，並不限定這些 測試模式之切換用訊號的產生電路構造，可以做各種變更 。例如，也可以設置 Μ、EnH以及 EnL之控制端子，由 外部切換控制H/L之位準。The Ex-OR circuit 6 is a polarity inverting circuit that inverts the polarity of the positive voltage negative voltage of the gate line of the liquid crystal panel, and the test state type inverter circuit 9 controls the output circuit for driving the gate line to High impedance state state setting circuit. Further, a latch circuit (D-reactor circuit) 7 is provided for the purpose of maintaining the output of the decoder 5 during the display period of the pixels of each line of the liquid crystal panel. The test state inverter circuit 9 is a so-called timing inverter circuit structure, as shown in Fig. 2, is a level shift circuit 40, and a high withstand voltage of a conventional inverter circuit. The p-channel type transistors 50 and 60 are composed of high-voltage n-channel type transistors 5 1 and 61. In the test state inverter circuit 9, by inputting the H/L signal at the gate terminals EnH/EnL of the transistors 60 and 61, as shown in Fig. 4, the input level H/L is applied. Can be controlled to a high impedance state. In addition, the purpose of using the level shifting circuit 40 and the high withstand voltage transistor is as follows: that is, the gate output voltage VGH/VGL is higher than the power supply voltage Vcc for operating the LCD driver 1 by, for example, +16.. 16.5V. Therefore, the P-channel type transistor 50, 60 and the n-channel type transistor 51 61 are used even when a voltage of VGL applied by VGH, that is, a voltage of 33 V (usually a voltage higher than this) is used. A transistor that guarantees the withstand voltage of the action. The shape and type of the ρ channel type transistor surrounded by the circular mark shown in Fig. 2 (input 5/- times, electric height 50 -12- (9) (9) 1254799, 60 0 and 5 1 and 6 1 show the use of a high withstand voltage transistor. The high withstand voltage crystal system is larger than the normal transistor size that is guaranteed to operate by applying a normal power supply voltage. Therefore, as shown in Fig. 2 As shown, the level shifting circuit 40 is set, by using a normal transistor in the circuit of the front stage of the level shifting circuit 40, and using a high voltage resistant crystal in the circuit of the latter stage of the level shifting circuit 40, The area of the wafer of the LCD driver 1 is made small. In the case of performing the test, as in the test mode (1) shown in Fig. 4, the setting signal EnH = EriL = L for the test state type inverter circuit 9 is set. When the input signal M = L of the EX - Ο R circuit 6 is set, the input level of the decoder circuit 5 is not changed, and is input to the test state type inverter circuit 9 by the inquiry lock circuit 7. Therefore, In this setting state, as shown in Fig. 6(a), the negative voltage output VGL can be made in the normal operation. The details are changed to the high-impedance state. The details of the setting method of the signal EnH/EnL of the test state inverter circuit 9 and the signal Μ of the Ex-OR circuit 6 will be described later. In the state setting LCD driver, as shown in Fig. 1, the first resistor (R1) 1 2 is connected to each of the gate output terminals G1 to Gn, and the other side of the first resistor 1 2 is connected in common. Connection point A is set to the second resistor (R2) 1 3 as the termination of the resistor circuit net. And 'Connect the connection point A to the semiconductor test device 1 比较 comparator 1 〇 3 ' to carry out the test. There is no LCD driver 1 In the case of the defect, as shown in Fig. 6(a), regardless of the state of the counter 4, only the 1 terminal of the gate output is the VG Η output, and the other is in the high impedance state, which is equivalent to the second figure. The circuit, that is, the input voltage of the comparator 1 0 3 becomes the ratio of the resistance 値R 1 -13- of the resistor 1 2 (10) 1254799 to the resistance 値R2 of the resistor 13 , namely: VA={R2/(Rl+R2) }xVGH [V] (Formula 1), the resistance of the first resistor 1 2 and the second resistor 13 becomes phase R1 = R2 = R) , VA = (1/2) VGH [V]. Based on the failure of the decoder circuit 5 or the like, unlike the voltage state of the sixth (a) diagram, the positive voltage VGH is input to two or more; in the case of output, or the voltage is not output to all of the gate outputs. Second, the resistor circuit shown in FIG. 1 is input to the comparator 1 〇3 different from the aforementioned voltage. For example, in the case of a fault, in the case where the positive voltage is output to the two terminals in the gate output, it becomes equivalent to the first circuit. At this time, if the principle of Millman is used, the voltage at the connection point A of the comparator 1 〇3 becomes: VA = (2VGH/R1) / {(1/R1) + (1/R1) +1/R1}} [V] (Equation 2). In the case where the resistance 値 of the first resistor 1 2 and the second resistor 13 is the same as R1 = R2 = R ), VA = (2/3) VGH [V], based on the voltage 连接 at the connection, the fault can be determined. There is no. In the above-described test, the output negative voltage VGL was originally changed to a high impedance by setting the signal for the test state inverter circuit 9 to EnH = EnL = L. In the implementation of this test 2 1 値 (;: the L gate L case J voltage VGH 3 map is the input 点 (point A situation set situation -14 - (11) (11) 1254799, shown in Figure 2 The n-channel type transistor 50 often does not operate. Therefore, in order to carry out the operation test of the n-channel type transistor 50, the input signal of the input Ex-OR circuit 6 is set to the Η level so that the input is in the test state type inverter. The level of the H/L of the circuit 9 is reversed. Moreover, as shown in the test mode (2) of Fig. 4, if the setting signal EnH = EnL = H for the test state type inverter circuit 9 is set, As shown in Fig. 6(b), only the one terminal of the gate output becomes the V GL output. The voltage input to the connection point A of the comparator 1 〇3 becomes (Formula 1) and (Formula 2) as described above. The VGH is changed to VGL, and similarly, the presence or absence of the fault can be determined. Thus, by setting the polarity inversion signal Μ ' for the Ex-OR circuit 6 and the setting signal EnH of the test state type inverter circuit 9 And EnL is set to the test mode (1) and test mode (2) shown in Fig. 4 'One channel of the semiconductor test device can be simultaneously entered The test of the gate output of the complex number is performed. Next, the setting of the Μ signal ' of the Ex-OR circuit 6 and the EnH and EnL signals for the test state type inverter circuit 9 is explained. Fig. 1 shows the test control circuit 2 A circuit configuration for generating signals of Μ, EnH, and EnL. Specifically, a test register (not shown) and a test control terminal TE ST are prepared in the interface circuit/storage unit 3. For the test register The writing is performed by using the input signal line. The test control terminal TEST is used as a control terminal for selecting the normal operation/test mode. For example, as shown in Fig. 5, the test control circuit 2 can respond to the test control terminal and the test. The setting of the memory is composed of circuits for outputting Μ, EnH and EnL signals. In addition, the test control terminal TEST of Figure 5 and the test temporary storage -15-(12) (12) 1254799 are set and Μ, The correspondence between the EnH and the EnL signal is not limited to this. The test control circuit 2 is illustrated separately, but may be included in the interface circuit/storage unit 3, for example. 2 Although the resistor 1 3 is terminated at GND (ground), it may be terminated at any arbitrary voltage. In the present embodiment, the setting of the test control terminal TE ST and the test register is shown in the figure. The test control circuit 2 generates an example of the signal (Μ, EnH, EnL) for switching the test mode. However, the object of the present invention is to set the output state of the sixth figure (test mode) during the test implementation ( 1) and (2)) are tested, and the circuit configuration for switching signals of these test modes is not limited, and various modifications can be made. For example, you can also set the control terminals of Μ, EnH, and EnL to switch the H/L level by external switching.
Ex-OR電路6由目前爲止之說明可以明白，係使對於 試驗狀態型反相器電路9之輸入位準反轉用之目的，只要 是藉由Μ訊號可使輸入輸出位準反轉之電路構造，即使 不是Ex-OR電路6亦可。雖圖示含有由電源電壓Vcc產生 閘極輸出電壓VGH/VGL之電源電路1 1，但是，依據LCD 驅動器之種類，可以是包含有電源電路之構造，也可以是 由外部輸入閘極輸出電壓VGH/VGL之構造。 另外，第1圖係舉關於閘極輸出之LCD驅動器的構造 之一例，並不限定輿圖示之構造。另外，具有未圖示出之 功能的電路集成化於同一晶片上亦可。另外，第2圖中， 雖圖示位準移位電路組裝在試驗狀態型反相器電路9內， -16- (13) (13)1254799 但是並不一定要設置在同一電路內。 在本實施形態中，雖以半導體試驗裝置之1通道來同 時試驗LCD驅動器之全部閘極輸出而做圖示及說明，但 是，本發明並不限定於此，也可以將複數的閘極輸出藉由 電阻電路網彙集爲1個，使用比閘極輸出數少之半導體試 驗裝置的通道數以實施試驗。可以考慮LCD驅動器的輸 入輸出接腳數與使用的半導體試驗裝置的全部通道數之關 係或閘極輸出接腳的晶片上之配置等，決定閘極輸出之彙 集數與半導體試驗裝置之使用通道數。 在以後說明之其他的實施形態中，雖不特別記載此點 ，但是，在基於本發明之實施形態中，很淸楚全部是相同 的。 最後，在本實施形態中，說明使追加電路的晶片佔有 面積減少之方法。第1圖所示之試驗狀態型反相器電路9的 構造雖可以第2圖所示之電晶體之組合來實現，但是，如 已經說明過的，此電路所使用之電晶體也需要使用高耐壓 者。因此，與本發明之前提的LCD驅動器相比，p通道型 、η通道型之高耐壓電晶體分別需要追加閘極輸出端子數 份，晶片面積增加，LCD驅動器的價格降低變得困難。 因此，如第7圖及第8圖所示般，令電路規模變小之例 子的LCD驅動器la係將控制爲高阻抗用之電晶體65及66 與試驗狀態型反相器電路10另外設置，藉由將電晶體65及 όό的 及 VGL2分配給各試驗狀態型反相器電路10， 可以使進行與第1圖及第2圖所示之電路相同的動作。藉由 -17- (14) (14)1254799 變更爲第7圖及第8圖所示之構造，追加之高耐壓的電晶體 數變得比第1圖及第2圖所示之情形少，可使基於本發明之 使用所致之LCD驅動器的晶片面積之增加的影響變少。 第7圖中，高阻抗控制用之電晶體65及66雖圖示爲與 其他的電路獨立而配置，但是，也可以是包含在測試控制 電路2或電源電路1 1內之構造。另外，電晶體6 5及6 6雖分 別圖示爲1個之電晶體，但是，考慮電晶體的電流限制或 電阻値等，可以複數個並聯設置電晶體等而構成最佳之設 定系統，也可做各種之變更。 在以後說明之實施形態中，雖以第1圖及第2圖所示之 試驗狀態型反相器電路做圖示及說明，但是，變更爲如第 7圖及第8圖之電路構造，不用說也可以。 (實施形態2 ) 利用第9圖〜第12圖來說明依據本發明之半導體裝置 的實施形態2之LCD驅動器。第9圖係LCD驅動器之構造 ，第1 〇圖係試驗時之等效電路，第1 1圖係不需要再設定比 較電壓之例子的LCD驅動器之構造，第1 2圖係測試形式 圖。 本實施形態2之LCD驅動器lb係如第9圖所示般，爲 將在則述貫施形悲1中設置於L C D驅動益與丰導體§式驗裝 置之間的電阻電路網集成化在LCD驅動器內之一例，在 不實施試驗時，可以切離電阻電路網而設置與第1電阻1 2 串聯連接之開關（開關手段）1 7。關於試驗實施（測試模 -18- (15) (15)1254799 式）時之各閘極輸出電壓，及 Μ、EnH、EnL之各訊號的 設定，係與前述實施形態1中所說明者相同故，省略說明 。與前述實施形態1不同處係藉由將電阻電路網集成化於 LCD驅動器1 b內，試驗時之輸出電壓全部經由閘極輸出 端子G 1，輸入半導體試驗裝置1 0 0之比較器而進行判定及 其之輸出電壓値。 如具體說明時，在LCD驅動器1 b無故障時，前述第6 圖所示之計數値爲1時之等效電路係變成如第10 (a)圖， 計數値爲1以外之情形’變成第1 〇 ( b )圖之等效電路。在 前述實施形態1中，於正常動作時’係與計數値無關，經 常以第1電阻1 2及第2電阻1 3之電阻比所決定之電壓，爲一 定之値，但是，在本實施形態中’由第1 0圖之等效電路可 以明白，只在計數値爲1之情形’輸出電壓成爲 V GH或 VGL。電壓値之良否判定雖以半導體試驗裝置1〇〇來進行 ，但是，藉由以LCD驅動器1 b的計數値爲1之狀態以及其 他狀態而變更半導體試驗裝置1 0 0的比較器1 0 3之比較電壓 値，可以正確地實施試驗。另外’比較器1 0 3的比較電壓 設定可藉由稱爲測試程式之控制半導體試驗裝置1 0 0用之 程式而任意進行。 另外，在本實施形態中所圖示之開關1 7 ’ 一般係以1 個或者複數個電晶體構成。另外’雖圖示將第1電阻1 2以 及第2電阻13—同集成化在LCD驅動器1內’但是’也可 以變更爲第2電阻1 3不予以集成化’於試驗時’以外部連 接方式爲之。 -19- (16) (16)1254799 如以上所說明般，在本實施形態中’於計數値爲1時 以及其以外時，輸入於半導體試驗裝置1〇〇的比較器10 3的 電壓不同。如前述實施形態1般，不管L C D驅動器1之設 定狀態，比較器1 〇 3的輸入電壓爲一定之情形’於試驗時 ，雖無必要令比較器的比較電壓改變，但是，在本實施形 態之情形，於試驗時，需要1次變更比較器的比較電壓。 因此，與前述實施形態1相比，比較器的比較電壓設定部 份會增加試驗時間。因此，於第1 1圖顯示在本實施形態所 示之LCD驅動器lb中，不須再設定比較器103的比較電壓 而進行試驗之例子。 在第11圖之LCD驅動器lc中，使用2個之半導體試 驗裝置100的比較器（Cpl、CP2 ) 103，分別連接於閘極 輸出端子G1與G2而實施試驗。LCD驅動器lc在測試模式 (1 )之設定時，計數値爲1時，於連接於 G 1之比較器 Cpl輸入 VGH，於連接於G2之比較器Cp2輸入 VGH/2之 電壓。另外，計數値爲2時，於連接於G1之比較器Cpl輸 入VGH/2，於連接於G2之比較器Cp2輸入VGH之電壓。 至前述爲止，雖說明基於半導體試驗裝置1 00之比較 益1 0 j的良否判定之詳細，但是，實際上，係以與記載如 第1 2圖所示之稱爲測試形式之比較器輸出的期待値η/L之 形式是否一致來進行LCD驅動器之良否判定。此處，記 載於測試形式之X係表示與比較器之輸出値Η/L無關， 不做期待値判定。即在第1 1圖所示之實施形態中，連接於 閘極輸出之2個比較器c p 1、C p 2的比較電壓係期待V G Η / 2 -20- (17) 1254799 故，當成一定値，依據測試形式，只在計數値1時， 接於G2之比較器做判定，在其他的計數値時，以連 G 1之比較器做判定。因此，不需要再設定比較器的 電壓故，比起第7圖所示之情形，試驗時間變短。 另外，在第1 1圖中，雖將比較器103連接於Gl|5 ，但是，並不限定連接端子，只是使用2個比較器實 驗即可。另外，第1 2圖之測試形式係說明其之一例而 並不限定於此。 在以上說明之實施形態1及實施形態2中，雖可確 複數的閘極輸出中，只有1接腳輸出電壓之排它性動 但是，要界定是哪個閘極輸出接腳輸出電壓有其困難 此，進而在以試驗之高可靠性爲目標之情形，可以使 下說明之實施形態3或實施形態4。 (實施形態3 ) 利用第13圖、第14圖說明依據本發明之半導體裝 實施形態3之LCD驅動器。第13圖係顯示LCD驅動 構造，第1 4圖係顯示試驗時之等效電路。 在本實施形態3之LCD驅動器Id中，與前述實施 1不同的部份係如第1 3圖所示般，設置在閘極輸出 G1〜Gn與半導體試驗裝置1〇〇之間的電阻電路網。具 ，將第1電阻1 2連接於各閘極輸出端間，將只連接於 輸出端子之第1電阻12的一方（連接點A)以第2電阻 以終接。連接此種與前述實施形態1不同之電阻電路 以連 接於 比較 t G2 施試 已， 認於 作， 。因 用以 置的 器之 形態 端子 體爲 閘極 13予 網， -21 - (18) (18)1254799 設定於在前述實施形態1說明之測試模式（1 )而實施試驗 〇 在本實施形態中，連接點A之電壓例如在設定爲第6 (a )圖之計數値1時，爲V G Η，在設定爲計數値2時’爲 以第1電阻及第2電阻R2所分壓之電壓，在設定爲計數 値3時，爲以第1電阻之2倍的2 R1與第3電阻R2所分壓之電 壓，如此第1電阻R 1被賦予權重。如表示在此種情形之等 效電路，則成爲如第1 4圖，在連接點Α之電壓變成： VA={R2/(xRl+R2)} VGH [V] (式 3) (但是，X :計數値· 1 ) ，藉由在連接點A之電壓値，也可以同時進行閘極 輸出電壓的接腳之特定的判定。 另外，在本實施形態中，與前述實施形態1相同，係 設定爲第4圖所示之測試模式（2 )而同樣地實施試驗。另 外，基於故障，在試驗時不成爲第6圖所示之電壓輸出狀 態時，如在前述實施形態1說明般而考慮等效電路時，在 連接點 A之電壓値與期待之値不同，很淸楚可以判定故 障之有無。 在連接點A之電壓測量係如第i 3圖所示般，以半導 體試驗裝置1 0 0之電壓測量單元1 5 0來進行測量。如前述實 施形態1般，雖也可以半導體試驗裝置100之比較器來進行 判定’但是，一般半導體試驗裝置1 〇〇在進行比較器的比 «22^ (19) (19)1254799 較電壓設定上，需要數値A s程度之時間。半導體試驗裝 置1 0 0之電壓測量單元1 5 0係測量電壓，以預先記載在測試 程式之判定値來判定故，速度與半導體試驗裝置1 〇 〇之 c P u等有關故，可以高速進行判定。如本實施形態般，在 測量時，電壓改變之情形，如第1 3圖所示般，以電壓測量 單元1 5 0進行判定’則試驗時間可以縮短，能夠降低L C D 驅動器1 d之製造成本。 但是，本實施形態並不限定於半導體試驗裝置1 0 0之 電壓測量單元1 5 〇，也可以最適合於試驗實施之方法來實 施試驗。 (實施形態4 ) 使用第1 5圖說明依據本發明之半導體裝置之實施形態 4的L C D驅動器。第1 5圖係顯示L C D驅動器之構造圖。 本實施形態4之L C D驅動器1 e係如第1 5圖所示般，爲 將前述實施形態3之電阻電路網集成化在L C D驅動器1內 之一例子，設置與第1電阻1 2串聯連接之開關〗7，使得在 試驗實施時之測試模式設定以外時，可以切離電阻電路網 °具體之動作及試驗方法等係與前述實施形態3相同故， 省略說明。另外，在本實施形態中，也可以獲得同樣的效 果。 另外，本實施形態中所圖示之開關1 7係與前述實施形 態2相同，以1個或複數個電晶體構成。另外，雖圖示將第 1電阻12及第2電阻13都集成化在LCD驅動器丨內，但是， -23- (20) (20)1254799 也可以變更爲第2電阻1 3不予以集成化’而在試驗時做外 部連接。 (實施形態5 ) 利用第1圖、第2 0圖說明依據本發明之實施形態、5之· LCD驅動器。第1圖係LCD驅動器之構造’第20圖係第1 圖之反相器電路9之電路構造圖。 本實施形態5之L C D驅動器1係將實施形態1所不之反 相器電路9的構造（第2圖）變更爲第20圖所示之電路構造 10者。 具體爲，與實施形態1相同’如第4圖所示般’ 一設定 爲測試模式時，因應輸入於反相器電路9之位準’以〇R 電路90及AND電路91來控制輸入p通道型電晶體50及η 通道型電晶體5 1之閘極的位準（H/L )，與實施形態1相同 ，因應輸入位準，可以控制爲高阻抗。以下，關於具體之 試驗方法，由於與實施形態1相同故，省略說明。 如依據本實施形態，控制爲高阻抗用之〇 R電路9 0與 A N D電路9 1係配置在位準移位電路4 0之輸入端子全段故 ，如實施形態1之高阻抗控制用電晶體般，不需要高耐壓 電晶體。另外，在實施形態1之第2圖所示的電路構造中， 由閘極端子所見到之導通時的電阻（輸出阻抗）雖成爲p 通道型電晶體50與60之和或者η通道型電晶體51與61之和 ，但是，在本實施形態中，與習知的L C D驅動器相同， 成爲Ρ通道型電晶體50或者η通道型電晶體51故，在使用 Ρ通道型電晶體5 0、η通道型電晶體5 i爲與實施形態1同樣 -24- (21) (21)1254799 特性者之情形，可使閘極端子之導通電阻變得更小。 以上，雖以將本實施形態5之反相器電路使用於實施 形態1 (第1圖）爲前提而做說明，但是，同樣地，能使用 於實施形態2至4 (第9圖、第1 1圖、第1 3圖、第1 5圖）一 事，由前述實施形態2至4之說明也可以淸楚。 在本實施形態中，作爲控制輸入於p通道型電晶體5 0 、η通道型電晶體5 1之閘極之位準而設爲高阻抗之手段， 雖係使用〇R電路90與AND電路91而做說明，但是，本 發明並不限定於此電路構造，只要是可以同樣地控制p通 道型電晶體5 0、η通道型電晶體5 1之閘極位準的構造即可 〇 以上，雖依據實施形態而具體說明由本發明人所完成 之發明，但是，本發明並不限定於前述實施形態，在不脫 離其要旨之範圍內，不用說可有種種變更之可能性。 【圖式簡單說明】 第1圖係顯示實施形態1之LCD驅動器的構造圖。 第2圖係顯示實施形態1之試驗時的等效電路圖。 第3圖係顯示在實施形態1中，假定故障時之等效電路 圖。 第4圖係顯示實施形態1之控制訊號的設定狀態圖。 第5圖係顯示實施形態1之測試控制電路的真値表圖。 第6A圖及第6B圖係顯示在實施形態1中，試驗時之 動作圖，第6A圖係對應測試模式（1 )，第6B圖係對應 -25- (22) (22)1254799 測試模式（2 )。 第7圖係顯示在實施形態1中’使電路規模變小之例子 的LCD驅動器之構造圖。 第8圖係顯示在實施形態1中，第7圖的反相器電路之 電路構造圖。 第9圖係顯示實施形態2之LCD驅動器的構造圖。 第1 Ο A圖及第1 Ο B圖係顯示在實施形態2中，試驗時 之等效電路圖，第10A圖係顯不計數値爲1時之等效電路 ，第1 0B圖係計數値在1以外時之等效電路圖。 第1 1圖係顯示在實施形態2中，不需要再設定比較電 壓之例子的LCD驅動器之構造圖。 第1 2圖係顯示實施形態2之測試形式圖。 第1 3圖係顯示實施形態3之L C D驅動器的構造圖。 第1 4圖係顯示在實施形態3中，試驗時之等效電路圖 〇 第15圖係顯示實施形態4之LCD驅動器的構造圖。 第1 6圖係顯示在當成本發明之前提所檢討之技術中， 液晶面板與LCD驅動器之連接關係圖。 第1 7圖係顯示在當成本發明之前提所檢討之技術中， LCD驅動器與半導體試驗裝置之連接關係圖。 第1 8圖係顯示在當成本發明之前提所檢討之技術中， 第1 7圖之反相器電路的構造圖。 第1 9圖係顯示在當成本發明之前提所檢討的技術中， LCD驅動器之閘極輸出的動作圖。 -26” (23) 1254799 第2 0圖係實施形態5之反相器電路的構造圖。 【主要元件符號說明】 1 液晶驅動器 2 測試控制電路 3 介面電路/暫存器 4 計數器 5 解碼器電路 6 Ε X -〇R電路 7 閂鎖電路 9 試驗狀態型反相器電路 10 試驗狀態型反相器電路 11 電源電路 12 第1電阻 13 第2電阻 17 開關 30 反相器電路 40 位準移位電路 50 Ρ通道型電晶體 5 1 η通道型電晶體 60 Ρ通道型電晶體 61 η通道型電晶體 65 電晶體 66 電晶體The Ex-OR circuit 6 can be understood from the description so far, and the purpose of inverting the input level of the test state type inverter circuit 9 is as long as the circuit can invert the input and output levels by the sigma signal. The configuration is not even the Ex-OR circuit 6. Although the power supply circuit 1 1 including the gate output voltage VGH/VGL generated by the power supply voltage Vcc is shown, it may be a configuration including a power supply circuit depending on the type of the LCD driver, or may be an external input gate output voltage VGH. /VGL construction. Further, Fig. 1 is an example of a structure of an LCD driver for gate output, and is not limited to the structure shown in the figure. Further, a circuit having a function not shown may be integrated on the same wafer. Further, in Fig. 2, although the level shifting circuit is shown assembled in the test state inverter circuit 9, -16-(13)(13) 1254799 is not necessarily provided in the same circuit. In the present embodiment, although all the gate outputs of the LCD driver are simultaneously tested by one channel of the semiconductor test apparatus, the illustration and description are made. However, the present invention is not limited thereto, and a plurality of gate outputs may be borrowed. One of the resistor circuit nets was collected, and the number of channels of the semiconductor test apparatus having a smaller number of gate outputs was used to carry out the test. The number of input and output pins of the LCD driver and the number of channels of the semiconductor test device used or the arrangement of the gate of the gate output pin can be considered to determine the number of gate outputs and the number of channels used by the semiconductor test device. . In the other embodiments described later, these points are not particularly described, but in the embodiments according to the present invention, they are all quite the same. Finally, in the present embodiment, a method of reducing the area occupied by the wafer of the additional circuit will be described. The structure of the test state inverter circuit 9 shown in Fig. 1 can be realized by a combination of transistors shown in Fig. 2, but as already explained, the transistor used in the circuit also needs to be used high. Pressure-resistant. Therefore, compared with the LCD driver previously proposed in the present invention, the p-channel type and n-channel type high resistance piezoelectric crystals require additional gate output terminal numbers, and the wafer area is increased, and the price of the LCD driver is lowered. Therefore, as shown in FIGS. 7 and 8, the LCD driver la which is an example in which the circuit scale is reduced is additionally provided with the transistors 65 and 66 controlled to be high impedance and the test state inverter circuit 10, By assigning the transistors 65 and όό and VGL2 to the respective test state inverter circuits 10, the same operations as those of the circuits shown in Figs. 1 and 2 can be performed. By changing the structure shown in Fig. 7 and Fig. 8 by -17-(14) (14) 1254799, the number of additional high-withstand voltage transistors is less than that shown in Figs. 1 and 2 The influence of the increase in the wafer area of the LCD driver due to the use of the present invention can be reduced. In Fig. 7, the transistors 65 and 66 for high-impedance control are shown as being independent of other circuits, but may be included in the test control circuit 2 or the power supply circuit 11. In addition, although the transistors 65 and 6 are each shown as one transistor, considering the current limit of the transistor, the resistance 値, etc., it is possible to form a plurality of transistors in parallel to form an optimum setting system. Various changes can be made. In the embodiment to be described later, the test state inverter circuit shown in FIGS. 1 and 2 is illustrated and described. However, the circuit configuration shown in FIGS. 7 and 8 is not used. Say it can. (Embodiment 2) An LCD driver according to a second embodiment of a semiconductor device according to the present invention will be described with reference to Figs. 9 to 12 . Figure 9 is the structure of the LCD driver. The first circuit is the equivalent circuit of the test. The first picture is the structure of the LCD driver that does not need to set the comparison voltage. The first picture is the test form. In the LCD driver 1b of the second embodiment, as shown in FIG. 9, the resistor circuit network provided between the LCD driving benefit and the conductor § test device is integrated in the LCD. In an example of the driver, when the test is not performed, the switch (switch means) 17 connected in series with the first resistor 1 2 can be provided by cutting off the resistor network. Regarding the test implementation (test -18-(15) (15) 1254799 type), the gate output voltages, and the settings of the signals of Μ, EnH, and EnL are the same as those described in the first embodiment. , the description is omitted. The difference from the first embodiment is that the resistor circuit network is integrated into the LCD driver 1b, and all of the output voltages during the test are input to the comparator of the semiconductor test device 100 via the gate output terminal G1. And its output voltage 値. As described in detail, when the LCD driver 1 b is not faulty, the equivalent circuit when the count 値 shown in Fig. 6 is 1 becomes the 10th (a) figure, and the case where the count 値 is 1 becomes the first 1 〇( b ) The equivalent circuit of the figure. In the first embodiment, the voltage is determined by the resistance ratio of the first resistor 1 2 and the second resistor 13 in the normal operation, regardless of the count 値. However, in the present embodiment, It can be understood from the equivalent circuit of Fig. 10 that the output voltage becomes V GH or VGL only when the count 値 is 1. The determination of the quality of the voltage 値 is performed by the semiconductor test apparatus 1B, but the comparator 1 0 3 of the semiconductor test apparatus 100 is changed by the state in which the count 値 of the LCD driver 1 b is 1 and other states. When the voltage is compared, the test can be performed correctly. Further, the comparison voltage setting of the comparator 1300 can be arbitrarily performed by a program for controlling the semiconductor test device 100 called a test program. Further, the switch 1 7 ' illustrated in the present embodiment is generally constituted by one or a plurality of transistors. In addition, although the first resistor 1 2 and the second resistor 13 are integrated in the LCD driver 1 'but the same can be changed to the second resistor 1 3 and not integrated into the test. For it. -19- (16) (16) 1254799 As described above, in the present embodiment, when the count 値 is 1 or other, the voltage of the comparator 10 3 input to the semiconductor test apparatus 1 is different. As in the first embodiment, the input voltage of the comparator 1 〇3 is constant regardless of the setting state of the LCD driver 1. In the test, it is not necessary to change the comparison voltage of the comparator. However, in the present embodiment, In the case of the test, it is necessary to change the comparison voltage of the comparator once. Therefore, compared with the first embodiment, the comparison voltage setting portion of the comparator increases the test time. Therefore, in the LCD driver 1b shown in the present embodiment, an example in which the comparison voltage of the comparator 103 is not required to be set is tested in Fig. 1 . In the LCD driver 1c of Fig. 11, two comparators (Cpl, CP2) 103 of the semiconductor test apparatus 100 are connected to the gate output terminals G1 and G2, respectively, and the test is performed. When the LCD driver lc is set in the test mode (1), when the count 値 is 1, the VGH is input to the comparator Cpl connected to G1, and the voltage of VGH/2 is input to the comparator Cp2 connected to G2. Further, when the count 値 is 2, VGH/2 is input to the comparator Cpl connected to G1, and the voltage of VGH is input to the comparator Cp2 connected to G2. As described above, the details of the comparison of the benefits of the comparison test of the semiconductor test apparatus 100 are described. However, in actuality, the output is compared with the comparator described as the test form shown in FIG. It is expected that the form of 値η/L is consistent to determine the quality of the LCD driver. Here, the X system recorded in the test form is not related to the output 値Η/L of the comparator, and is not expected to be determined. That is, in the embodiment shown in Fig. 1, the comparison voltages of the two comparators cp 1 and C p 2 connected to the gate output are expected to be VG Η / 2 -20 - (17) 1254799. According to the test form, only when the count 値1, the comparator connected to G2 makes a judgment, and when other counts 値, the judgment is made by the comparator of G1. Therefore, it is not necessary to set the voltage of the comparator, and the test time becomes shorter than in the case shown in Fig. 7. Further, in Fig. 1, the comparator 103 is connected to Gl|5, but the connection terminal is not limited, and only two comparator experiments may be used. Further, the test form of Fig. 2 is an example of the test, and is not limited thereto. In the first embodiment and the second embodiment described above, although it is possible to determine the gate output voltage of the plurality of gate outputs, only one pin output voltage is excitable. However, it is difficult to define which gate output pin output voltage is difficult. Further, in the case of the high reliability of the test, the third embodiment or the fourth embodiment will be described below. (Embodiment 3) An LCD driver according to Embodiment 3 of the semiconductor package according to the present invention will be described with reference to Figs. 13 and 14. Fig. 13 shows the LCD driving structure, and Fig. 14 shows the equivalent circuit during the test. In the LCD driver Id of the third embodiment, a portion different from the above-described first embodiment is a resistor circuit network provided between the gate outputs G1 to Gn and the semiconductor test device 1 as shown in FIG. . The first resistor 1 2 is connected between the gate output terminals, and one of the first resistors 12 (connection point A) connected only to the output terminal is terminated by a second resistor. A resistor circuit different from the above-described first embodiment is connected to the comparison t G2 and has been tested. In the embodiment, the terminal body of the device is a gate 13 and the -21 - (18) (18) 1254799 is set in the test mode (1) described in the first embodiment, and the test is carried out. The voltage at the connection point A is, for example, VG Η when the count 値1 of the sixth (a) diagram is set, and 'the voltage divided by the first resistor and the second resistor R2 when set to the count 値2. When the count 値3 is set, the voltage is divided by 2 R1 and the third resistor R2 which are twice the first resistance, and thus the first resistor R 1 is given a weight. As shown in the equivalent circuit in this case, the voltage at the connection point becomes: VA={R2/(xRl+R2)} VGH [V] (Expression 3) (However, X : Count 値· 1 ), by the voltage 连接 at the connection point A, the specific determination of the pin of the gate output voltage can be simultaneously performed. Further, in the present embodiment, as in the first embodiment, the test mode (2) shown in Fig. 4 is set and the test is carried out in the same manner. Further, when the voltage is not in the voltage output state shown in Fig. 6 at the time of the test, when the equivalent circuit is considered as described in the first embodiment, the voltage 连接 at the connection point A is different from the expected value. You can determine the presence or absence of a fault. The voltage measurement at the connection point A is measured by the voltage measuring unit 150 of the semiconductor test device 100 as shown in Fig. 3 . As in the first embodiment, the comparator of the semiconductor test apparatus 100 can be used for the determination. However, in general, the semiconductor test apparatus 1 is configured to compare the voltage of the comparator with the ratio of «22^ (19) (19) 1254799. It takes a few 値A s degrees. The voltage measuring unit of the semiconductor test device 100 detects the voltage, which is determined in advance in the determination of the test program. Therefore, the speed is related to the c P u of the semiconductor test device 1 and can be determined at high speed. . As in the case of the present embodiment, when the voltage is changed during the measurement, as determined by the voltage measuring unit 150, as shown in Fig. 3, the test time can be shortened, and the manufacturing cost of the L C D driver 1 d can be reduced. However, the present embodiment is not limited to the voltage measuring unit 15 5 of the semiconductor test apparatus 100, and the test may be carried out in a manner most suitable for the test. (Embodiment 4) An L C D driver according to Embodiment 4 of the semiconductor device according to the present invention will be described with reference to Fig. 15. Figure 15 shows the construction of the L C D driver. As shown in FIG. 5, the LCD driver 1e of the fourth embodiment is an example in which the resistor circuit network of the third embodiment is integrated in the LCD driver 1, and is connected in series with the first resistor 1 2 . When the test mode is set other than the test mode setting, the switch circuit can be cut off from the resistor circuit. The specific operation and test method are the same as those in the third embodiment, and the description thereof is omitted. Further, in the present embodiment, the same effect can be obtained. Further, the switch 17 shown in the present embodiment is the same as the above-described embodiment 2, and is constituted by one or a plurality of transistors. In addition, although the first resistor 12 and the second resistor 13 are integrated in the LCD driver, the -23-(20) (20) 1254799 may be changed to the second resistor 1 3 and not integrated. And do external connections during the test. (Fifth Embodiment) An LCD driver according to an embodiment of the present invention and a fifth embodiment will be described with reference to Figs. 1 and 2O. Fig. 1 is a configuration of an LCD driver. Fig. 20 is a circuit configuration diagram of an inverter circuit 9 of Fig. 1. In the L C D driver 1 of the fifth embodiment, the structure (second diagram) of the inverter circuit 9 of the first embodiment is changed to the circuit structure 10 shown in Fig. 20. Specifically, in the same manner as in the first embodiment, when the test mode is set as shown in FIG. 4, the input p channel is controlled by the R circuit 90 and the AND circuit 91 in response to the level input to the inverter circuit 9. The level (H/L) of the gate of the type transistor 50 and the ? channel type transistor 51 is the same as that of the first embodiment, and can be controlled to a high impedance in accordance with the input level. Hereinafter, the specific test method is the same as that of the first embodiment, and the description thereof will be omitted. According to the present embodiment, the 〇R circuit 90 and the AND circuit 9 1 for controlling the high impedance are disposed in the entire input terminal of the level shift circuit 40, and the high impedance control transistor of the first embodiment is used. Generally, high resistance to piezoelectric crystals is not required. Further, in the circuit configuration shown in Fig. 2 of the first embodiment, the resistance (output impedance) when the gate terminal is turned on is the sum of the p-channel type transistors 50 and 60 or the n-channel type transistor. The sum of 51 and 61, however, in the present embodiment, like the conventional LCD driver, the Ρ channel type transistor 50 or the n channel type transistor 51 is used, and the Ρ channel type transistor 50, η channel is used. The transistor 5i is the same as the -24(21)(21)1254799 characteristic of the first embodiment, and the on-resistance of the gate terminal can be made smaller. The above description is based on the premise that the inverter circuit of the fifth embodiment is used in the first embodiment (first drawing), but similarly, it can be used in the second to fourth embodiments (the ninth diagram and the first The descriptions of the first embodiment, the first embodiment, the first embodiment, the second embodiment, the first embodiment, the first embodiment, the first embodiment, the second embodiment, the second embodiment, the second embodiment, the second embodiment. In the present embodiment, the 〇R circuit 90 and the AND circuit 91 are used as means for controlling the level of the gates input to the p-channel transistor 50 and the n-channel transistor 5 1 to be high impedance. In addition, the present invention is not limited to this circuit configuration, and any structure that can control the gate levels of the p-channel transistor 50 and the n-channel transistor 5 1 in the same manner can be used. The invention made by the inventors of the present invention is specifically described with reference to the embodiments. However, the present invention is not limited to the embodiments described above, and various modifications may be made without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a structural view showing an LCD driver of the first embodiment. Fig. 2 is an equivalent circuit diagram showing the test in the first embodiment. Fig. 3 is a view showing an equivalent circuit diagram at the time of failure in the first embodiment. Fig. 4 is a view showing a setting state of the control signal of the first embodiment. Fig. 5 is a true diagram showing the test control circuit of the first embodiment. Fig. 6A and Fig. 6B are diagrams showing the operation diagram during the test in the first embodiment, Fig. 6A corresponds to the test mode (1), and Fig. 6B corresponds to the -25-(22) (22) 1254799 test mode ( 2 ). Fig. 7 is a view showing the construction of an LCD driver in which the circuit scale is reduced in the first embodiment. Fig. 8 is a circuit diagram showing the inverter circuit of Fig. 7 in the first embodiment. Fig. 9 is a view showing the configuration of an LCD driver of the second embodiment. The first ΟA diagram and the first ΟB diagram show the equivalent circuit diagram at the time of the test in the second embodiment, and the 10A diagram shows the equivalent circuit when the 値 is 1 and the 1st 0B diagram is counted. Equivalent circuit diagram when 1 is outside. Fig. 1 is a structural view showing an LCD driver in which the comparison voltage is not required to be set in the second embodiment. Fig. 12 is a view showing a test form of the second embodiment. Fig. 13 is a structural view showing the L C D driver of the third embodiment. Fig. 14 is a view showing an equivalent circuit diagram at the time of the test in the third embodiment. Fig. 15 is a view showing the configuration of the LCD driver of the fourth embodiment. Fig. 16 is a diagram showing the connection relationship between the liquid crystal panel and the LCD driver in the technique reviewed before the invention of the invention. Fig. 17 is a diagram showing the connection relationship between the LCD driver and the semiconductor test apparatus in the technique reviewed before the invention of the invention. Fig. 18 is a view showing the construction of the inverter circuit of Fig. 17 in the technique reviewed before the invention of the invention. Figure 19 shows an action diagram of the gate output of the LCD driver in the technique reviewed prior to the cost invention. -26" (23) 1254799 Figure 20 is a structural diagram of the inverter circuit of Embodiment 5. [Main component symbol description] 1 LCD driver 2 Test control circuit 3 Interface circuit/register 4 Counter 5 Decoder circuit 6 Ε X -〇R circuit 7 Latch circuit 9 Test state type inverter circuit 10 Test state type inverter circuit 11 Power supply circuit 12 1st resistor 13 2nd resistor 17 Switch 30 Inverter circuit 40 Level shift Circuit 50 Ρ channel type transistor 5 1 η channel type transistor 60 Ρ channel type transistor 61 η channel type transistor 65 transistor 66 transistor
-27- (24)1254799 1 00 半 導 體 試 驗裝置 1 03 比 較 器 500 液 晶 面 板 50 1 源 極 驅 動 器 502 閘 極 驅 動 器 503 電 源 電 路 5 10 畫 素-27- (24)1254799 1 00 Semi-conductor test device 1 03 Comparator 500 liquid crystal panel 50 1 source driver 502 gate driver 503 power circuit 5 10 pixels
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