KR20050040002A - Manufacturing method for semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device, wherein in the process of forming the bit line contact plug into the barrier metal layer and the W layer, the etching process proceeds to the CMP process, and the amount of seam of the W layer or the barrier metal layer is limited by limiting the excess amount. Since damage is prevented, it is possible to prevent a pattern defect or an increase in capacitance of a bit line.

Description

Manufacturing method for semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to prevent loss of a bit line contact plug, to prevent a defect of the device, and to increase process resistance and reliability of a device by preventing an increase in contact resistance or an increase in bit line capacitance. It relates to a method for manufacturing a semiconductor device that can be.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.

In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A contrast enhancement layer (CEL) method or a tri layer resister (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. In addition, a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wirings are reduced, and the contact hole diameter and The aspect ratio, which is the ratio of depths, increases. Therefore, in the highly integrated semiconductor device having the multilayer conductive wiring, accurate and strict alignment between the masks in the contact forming process is required, so that the process margin is reduced or the process must be performed without any margin.

These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, The mask is formed by considering factors such as registration between the masks.

As a method of forming the contact hole as described above, there are a direct etching method, a method using a sidewall spacer, a SAC method, and the like.

In the above method, the direct etching method and the sidewall spacer forming method cannot be used for manufacturing a device having a design rule of 0.3 μm or less in the current technology level, and thus there is a limitation in high integration of the device.

In addition, the SAC method, which is designed to overcome the limitations of the lithography process in forming contact holes, can be divided into polysilicon layer, nitride film, or oxynitride film, depending on the material used as the etch barrier layer. Can be used as an etch shield.

Although not shown, a method of manufacturing a semiconductor device according to the related art is as follows.

First, a gate oxide layer constituting a metal oxide semi conductor field effect transistor (hereinafter referred to as a MOS FET) and a gate electrode overlapping the hard mask layer pattern are formed on a semiconductor substrate, and then the hard mask layer is formed. An insulating spacer made of a nitride film is formed on the sidewalls of the pattern and the gate electrode, and the lower interlayer insulating film is coated on the entire surface of the structure, and then planarized.

Next, the lower interlayer insulating layer is patterned to form a landing plug contact hole by a photolithography process using an etching mask for landing plugs, and a landing plug conductive layer is applied to the entire surface of the structure to fill the contact hole. The conductive layer is etched to form a landing plug separated by each contact hole.

Thereafter, the upper interlayer insulating film is applied to the entire surface of the structure, and then the upper interlayer insulating film on the portion of the landing plug, which is supposed to be a bitline contact, is removed to form a bitline contact hole.

Then, the Ti / TiN layer, which is a barrier metal layer, and the W layer, which is a plug material, are sequentially applied to the entire surface of the structure to fill the contact hole, and then the back layer and the barrier metal layer are sequentially etched back to form a bit line contact plug. do.

In the method of manufacturing a semiconductor device according to the related art as described above, the barrier metal layer inside the contact hole is severely damaged during the etch back process of the barrier metal layer after W etching to form the bit line contact plug, as shown in FIGS. 1A to 1C. There is a problem that the barrier metal layer is lost, and a core is generated at the center of W to cause electrical disconnection, or the capacitance of a subsequent bit line is increased, thereby decreasing process yield and device reliability.

Furthermore, in devices having a design rule of 0.1 μm or less, the barrier metal layer occupies a thickness of 30% or more of the contact plug material, thereby increasing the occurrence of defects.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to prevent damage of the barrier metal layer and the contact plug material when the bit line contact plug is formed, thereby deteriorating the characteristics of the device due to electrical disconnection or increasing the capacitance of the bit line. It is to provide a method of manufacturing a semiconductor device that can prevent the.

Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,

Forming an interlayer insulating film having a bit line large hole on a semiconductor substrate having a predetermined lower structure formed thereon;

Sequentially forming a barrier metal layer and a contact plug conductive layer on the entire surface of the structure;

And forming a contact plug having a first barrier metal layer and a conductive layer pattern filling the bit line contact hole by sequentially CMP etching the contact plug conductive layer and the first barrier metal layer on the interlayer insulating layer.

In addition, another feature of the present invention is that the barrier metal layer is a Ti, TiN or Ti / TiN laminated structure, the interlayer insulating film is BPSG, PSG or SOD, the interlayer insulating film is 1000-10000Å thickness, the slurry of the slurry in the CMP process H2O2 is 0.1 to 5 w%, the slurry is an acid slurry of pH 1-9, the slurry in the CMP process using a colloidal silica-based abrasive, the slurry in the CMP process contains 0.01 to 10 w% citric acid, After the CMP process is carried out a cleaning process for removing the residue, it is carried out for 1-60 seconds using NH4OH or HF.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are manufacturing process diagrams of a semiconductor device according to the present invention.

First, as described above in the related art, a gate oxide film 12 of the MOS FET is formed on the semiconductor substrate 10, and the gate electrode overlapping the hard mask layer 16 pattern on the gate oxide film 12. After forming (14), an insulating spacer 18 of a nitride film material is formed on the sidewalls of the hard mask layer 16 pattern and the gate electrode 14. The etching barrier layer may be formed before the lower interlayer insulating layer 20 is applied.

Thereafter, the lower interlayer insulating film 20 is applied to the entire surface of the structure, and then planarized. (See FIG. 2A).

Next, the lower interlayer insulating layer 20 is patterned to form a landing plug contact hole by a photolithography process using an etching mask for landing plugs, and a landing plug conductive layer 22 is coated on the entire surface of the structure to form the landing plug contact hole. Fill the hall (See FIG. 2B).

Thereafter, the conductive layer 22 is etched by etching, CMP, or the like to form a landing plug having a conductive layer 22 pattern separated into respective contact holes. (See FIG. 2C).

Then, after applying the upper interlayer insulating film 24 to the entire surface of the structure, the upper interlayer insulating film 24 on the portion of the landing plug, which is supposed to be a bit line contact, is removed to form a bit line contact hole, and the structure The bit line contact hole is filled by sequentially applying a barrier metal layer 26 having a Ti, TiN or Ti / TiN stacked structure and a W layer 28 which is a plug material on the entire surface of the substrate. In this case, the upper interlayer insulating film 24 uses BPSG, PSG, or SOD to mitigate the topology in the etching process for forming the landing plug to minimize the influence of subsequent processes by the topology, and the thickness thereof is 1000-10000 1000. It is enough. (See FIG. 2D).

Thereafter, the W layer 28 and the barrier metal layer 26 on the upper interlayer insulating film 24 are removed by a CMP process to form a bit line contact plug having a pattern of the W layer 28 and the barrier metal layer 26. At this time, the CMP process reduces the H 2 O 2 of the slurry to 0.1 to 5 wt% to prevent the seam of the W layer 28, and does not use a slurry for metal, using a slurry of about pH 1-9, acidic slurry A colloidal silica-based abrasive is used, and 0.01 to 10 wt% of citric acid is contained in the acidic slurry. Here, limiting the fruit tree to 5 wt% or less can be seen that the seam of the W layer increases as the amount of fruit in the slurry increases, as shown in FIGS. 3A to 3E.

A cleaning process is then performed to remove residues formed during the CMP process. Here, the cleaning process uses NH 4 OH or HF, and the cleaning time is limited to about 1 to 60 seconds to prevent the core of W from growing when using HF. (See FIG. 2E).

As described above, the contact plug formed according to the present invention can be seen that the damage of the barrier metal layer and the generation of the seam of the W layer are prevented as shown in FIGS. 4A to 4C.

As described above, in the method of manufacturing a semiconductor device according to the present invention, in the process of forming the bit line contact plug into the barrier metal layer and the W layer, the etching process proceeds to the CMP process to prevent seam generation of the W layer or damage of the barrier metal layer. As a result, there is an advantage of preventing a pattern defect or an increase in capacitance of a bit line.

Figure 1a is a cross-sectional SEM photograph of a semiconductor device according to the prior art.

Figure 1b is a CD-SEM photograph of a semiconductor device according to the prior art.

Figure 1c is a TEM photograph of a semiconductor device according to the prior art.

2a to 2e is a manufacturing process diagram of a semiconductor device according to the present invention.

3A to 3E are TEM photographs of the semiconductor device according to the excess amount during the CMP process according to the present invention.

Figure 4a is a cross-sectional SEM photograph of a semiconductor device according to the present invention.

Figure 4b is a CD-SEM picture of the semiconductor device according to the present invention.

4c is a TEM photograph of a semiconductor device according to the present invention;

<Description of Symbols for Main Parts of Drawings>

10 semiconductor substrate 12 gate oxide film

14 gate electrode 16 hard mask layer

18: insulating spacer 20: lower interlayer insulating film

22: conductive layer for landing plug 24: upper interlayer insulating film

26: barrier metal layer 28: W layer

Claims (9)

Forming an interlayer insulating film having a bit line large hole on a semiconductor substrate having a predetermined lower structure formed thereon; Sequentially forming a barrier metal layer and a contact plug conductive layer on the entire surface of the structure; And CMP etching the contact plug conductive layer and the barrier metal layer on the interlayer insulating film sequentially to form a contact plug having a barrier metal layer and a conductive layer pattern filling the bit line contact hole. The method of claim 1, The barrier metal layer is a manufacturing method of a semiconductor device, characterized in that the Ti, TiN or Ti / TiN laminated structure. The method of claim 1, The interlayer insulating film is a method of manufacturing a semiconductor device, characterized in that formed of one material arbitrarily selected from the group consisting of BPSG, PSG and SOD. The method of claim 1, The interlayer insulating film is a manufacturing method of a semiconductor device, characterized in that the thickness of 1000-10000Å. The method of claim 1, The H2O2 of the slurry in the CMP process is a method for manufacturing a semiconductor device, characterized in that 0.1 to 5 wt%. The method of claim 1, The slurry in the CMP process is a method for manufacturing a semiconductor device, characterized in that the slurry of pH 1-9. The method of claim 1, In the CMP process, the slurry is a manufacturing method of a semiconductor device, characterized in that to use a colloidal silica-based abrasive. The method of claim 1, In the CMP process, the slurry includes 0.01 to 10% by weight of citric acid. The method of claim 1, After the CMP process to perform a cleaning process for removing the residue, a method of manufacturing a semiconductor device, characterized in that for 1 to 60 seconds using NH4OH or HF.