KR20050006852A - Method for forming metal line of semiconductor device - Google Patents

Method for forming metal line of semiconductor device Download PDF

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Publication number
KR20050006852A
KR20050006852A KR1020030046824A KR20030046824A KR20050006852A KR 20050006852 A KR20050006852 A KR 20050006852A KR 1020030046824 A KR1020030046824 A KR 1020030046824A KR 20030046824 A KR20030046824 A KR 20030046824A KR 20050006852 A KR20050006852 A KR 20050006852A
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South Korea
Prior art keywords
landing plug
forming
layer
contact hole
buffer oxide
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KR1020030046824A
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Korean (ko)
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강경두
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주식회사 하이닉스반도체
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Priority to KR1020030046824A priority Critical patent/KR20050006852A/en
Publication of KR20050006852A publication Critical patent/KR20050006852A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Abstract

PURPOSE: A method for forming a metal interconnection of a semiconductor device is provided to prevent a bridge between a gate and a bitline caused by over-etch in etching a landing plug contact and a bitline contact by forming a buffer oxide layer under a nitride layer for a hard mask. CONSTITUTION: A conductive material layer pattern is formed on an active region of a semiconductor substrate(31) divided into the active region(31a) and a filed region(31b). A buffer oxide layer(37) is formed on the semiconductor substrate including the conductive material layer pattern. A hard mask nitride layer is formed on the buffer oxide layer to perform a gap-fill process. The hard mask nitride layer between the conductive material layer patterns is selectively removed. A spacer nitride layer is formed on the resultant structure. The spacer nitride layer and the buffer oxide layer are selectively removed to form a landing plug contact hole exposing a part of the semiconductor substrate. A landing plug is formed in the landing plug contact hole. After an interlayer dielectric(47) is formed on the resultant structure, a bitline contact hole(49) for exposing the landing plug is formed in the interlayer dielectric. A bitline(51) electrically connected to the landing plug is formed on the interlayer dielectric including the bitline contact hole.

Description

반도체소자의 금속배선 형성방법{Method for forming metal line of semiconductor device}Method for forming metal line of semiconductor device

본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로서, 보다 상세하게는 하드마스크용 질화막하단부에서 버퍼산화막을 형성하므로써 랜딩플러그 콘택 식각 및 비트라인 콘택식각시에 과도식각으로 인해 유발될 수 있는 게이트와 비트라인간 브릿지를 방지할 수 있는 반도체소자의 금속배선 형성방법에 관한 것이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and more particularly, by forming a buffer oxide film at a lower portion of a nitride film for a hard mask, and a gate which may be caused due to excessive etching during landing plug contact etching and bit line contact etching. The present invention relates to a metal wiring forming method of a semiconductor device capable of preventing the bridge between the bit lines.

현재 적용되는 게이트 제조공정에 대해 설명하면, 도면에는 도시하지 않았지만, 액티브영역과 필드영역으로 구분된 반도체기판상에 도프트 폴리실리콘층, 텅스텐실리사이드층 및 하드마스크층을 순차적으로 증착한후 하드마스크용 질화막을 선택적으로 식각하여 게이트를 정의하는 질화막패턴을 형성한다.Referring to the current manufacturing process of the gate, although not shown in the figure, the hard mask after depositing a doped polysilicon layer, a tungsten silicide layer and a hard mask layer sequentially on a semiconductor substrate divided into an active region and a field region The nitride film is selectively etched to form a nitride film pattern defining a gate.

그다음, 질화막 스페이서를 형성하기 전에 질화막과 실리콘사이의 스트레스를 완화시키는 차원에서 버퍼산화막을 형성하게 된다.Next, before forming the nitride spacer, a buffer oxide layer is formed in order to alleviate the stress between the nitride layer and the silicon.

그러나, 이때 형성된 버퍼산화막은 비트라인을 형성하기 위한 랜딩플러그 콘택식각 및 비트라인 콘택식각 그리고 세정공정이 반복적으로 진행되는 동안, 게이트 상부쪽에서부터 텅스텐실리사이드층측면까지 이어지는 버퍼산화막이 식각되면서 비트라인 배리어금속인 Ti/TiN 증착시에 게이트와 비트라인사이의 브릿지를 유발시킬 가능성이 매우 높으며, 포토공정 진행시에 얼라인 마진이 매우 작은 문제점이 존재한다.However, the buffer oxide film formed at this time is a bit line barrier as the buffer oxide film is etched from the top of the gate to the tungsten silicide layer side during the landing plug contact etching, the bit line contact etching, and the cleaning process to form the bit line repeatedly. There is a high possibility of causing a bridge between the gate and the bit line during the deposition of Ti / TiN, which is a metal, and there is a problem that the alignment margin is very small during the photo process.

이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 하드마스크용 질화막하단부에서 버퍼산화막을 형성하므로써 랜딩플러그 콘택 식각 및 비트라인 콘택식각시에 과도식각으로 인해 유발될 수 있는 게이트와 비트라인간 브릿지를 방지할 수 있는 반도체소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Therefore, the present invention has been made to solve the above-mentioned problems of the prior art, and by forming a buffer oxide film at the lower end of the nitride film for the hard mask, the gate and the gate which may be caused by the transient etching during the etching of the landing plug contact and bit line contact; It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device capable of preventing a bridge between bit lines.

도 1a 내지 도 1e는 본 발명에 따른 반도체소자의 금속배선 형성방법을 설명하기 위한 공정단면도,1A through 1E are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to the present invention;

[도면부호의설명][Description of Drawing Reference]

31 : 반도체기판 31a : 액티브지역31: semiconductor substrate 31a: active area

31b : 필드지역 33 : 폴리실리콘층31b: field area 33: polysilicon layer

35 : 텅스텐실리사이드층 37 : 버퍼산화막35: tungsten silicide layer 37: buffer oxide film

39 : 하드마스크 질화막 41 : 제2희생레지스트막패턴39 hard mask nitride film 41 second sacrificial resist film pattern

43 : 스페이서 질화막 43a : 스페이서43 spacer nitride film 43a spacer

45 : 랜딩플러그 47 : 층간절연막45: landing plug 47: interlayer insulating film

49 : 비트라인 콘택홀 51 : 비트라인49: bit line contact hole 51: bit line

상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 금속배선 형성방법 은, 액티브지역과 필드지역으로 구분된 반도체기판의 액티브지역상에 도전물질층패턴을 형성하는 단계;According to an aspect of the present invention, there is provided a metal wiring forming method of a semiconductor device, the method comprising: forming a conductive material layer pattern on an active region of a semiconductor substrate divided into an active region and a field region;

상기 도전물질층패턴을 포함한 반도체기판상면에 버퍼산화막을 형성하는 단계;Forming a buffer oxide film on an upper surface of the semiconductor substrate including the conductive material layer pattern;

상기 버퍼산화막상에 하드마스크 질화막을 형성하여 갭매립시키는 단계;Forming a hard mask nitride layer on the buffer oxide layer to fill a gap;

상기 도전물질층패턴사이의 하드마스크 질화막을 선택적으로 제거하는 단계;Selectively removing the hard mask nitride layer between the conductive material layer patterns;

상기 선택적으로 제거된 하드마스크 질화막을 포함한 전체 구조의 상면에 스페이서 질화막을 형성하는 단계;Forming a spacer nitride film on an upper surface of the entire structure including the selectively removed hard mask nitride film;

상기 스페이서 질화막 및 버퍼산화막을 선택적으로 제거하여 상기 반도체기판의 일부분을 드러나게 하는 랜딩플러그 콘택홀을 형성하는 단계;Selectively removing the spacer nitride layer and the buffer oxide layer to form a landing plug contact hole exposing a portion of the semiconductor substrate;

상기 랜딩플러그 콘택홀내에 랜딩플러그를 형성하는 단계;Forming a landing plug in the landing plug contact hole;

상기 랜딩플러그를 포함한 전체 구조의 상면에 층간절연막을 형성한후 상기 층간절연막내에 상기 랜딩플러그부분을 노출시키는 비트라인콘택홀을 형성하는 단계; 및Forming an interlayer insulating film on an upper surface of the entire structure including the landing plug, and then forming a bit line contact hole in the interlayer insulating film to expose the landing plug portion; And

상기 비트라인콘택홀을 포함한 층간절연막상에 상기 랜딩플러그와 전기적으로 연결되는 비트라인을 형성하는 단계를 포함하여 구성되는 것을 특징으로한다.And forming a bit line electrically connected to the landing plug on the interlayer insulating layer including the bit line contact hole.

(실시예)(Example)

이하, 본 발명에 따른 반도체소자의 금속배선 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming metal wirings of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1e는 본 발명에 따른 반도체소자의 금속배선 형성방법을 설명하기 위한 공정단면도이다.1A to 1E are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to the present invention.

본 발명에 따른 반도체소자의 금속배선 형성방법은, 도 1a에 도시된 바와같이, 먼저 액티브영역(31a)과 필드영역(31b)으로 구분된 반도체기판(31)상에 폴리실리콘층(33)과 텅스텐실리사이드층(35)을 순차적으로 증착한후 그 위에 레지스트막(미도시)을 도포한다.As shown in FIG. 1A, a method of forming a metal wiring of a semiconductor device according to the present invention includes a polysilicon layer 33 and a polysilicon layer 33 formed on a semiconductor substrate 31 divided into an active region 31a and a field region 31b. The tungsten silicide layer 35 is sequentially deposited and a resist film (not shown) is applied thereon.

그다음, 포토리소그라피 공정기술에 의해 상기 레지스트막을 노광 및 현상공정을 거쳐 선택적으로 패터닝하여 게이트지역을 정의하는 제1희생레지스트막패턴(미도시)을 형성한다.Then, the resist film is selectively patterned by photolithography process technology through an exposure and development process to form a first sacrificial resist film pattern (not shown) defining a gate area.

이어서, 상기 제1희생레지스트막패턴을 마스크로 상기 텅스텐실리사이드층(35)과 폴리실리콘층(33)을 순차적으로 식각한후 상기 제1희생레지스트막패턴을 제거한다.Subsequently, the tungsten silicide layer 35 and the polysilicon layer 33 are sequentially etched using the first sacrificial resist film pattern as a mask, and then the first sacrificial resist film pattern is removed.

그다음, 순차적으로 식각된 청스텐실리사이드층(35)과 폴리실리콘층(33)을 포함한 반도체기판(31)상에 버퍼산화막(37)을 증착한다.Next, a buffer oxide film 37 is deposited on the semiconductor substrate 31 including the etched blue stencil silicide layer 35 and the polysilicon layer 33.

이어서, 도 1b에 도시된 바와같이, 버퍼산화막(37)상에 하드마스크용 질화막(39)을 증착하여 상기 텅스텐실리사이드층(35)과 폴리실리콘층(33)을 매립한다.Subsequently, as illustrated in FIG. 1B, a hard mask nitride layer 39 is deposited on the buffer oxide layer 37 to fill the tungsten silicide layer 35 and the polysilicon layer 33.

그다음, 도 1c에 도시된 바와같이, 상기 하드마스크용 질화막(39)상에 레지스트막(미도시)을 도포한후 포토리소그라피 공정기술에 의해 상기 레지스트막을 노광 및 현상공정을 거쳐 선택적으로 패터닝하여 게이트지역을 정의하는 제2희생레지스트막패턴(41)을 형성한다.Next, as shown in FIG. 1C, a resist film (not shown) is coated on the hard mask nitride film 39, and then the resist film is selectively patterned through an exposure and development process by a photolithography process technique to form a gate. A second sacrificial resist film pattern 41 defining a region is formed.

이어서, 상기 제2희생레지스트막패턴(41)을 마스크로 상기 질화막(39)을 선택적으로 제거한후 상기 제2희생레지스트막패턴(41)을 제거한다.Subsequently, the nitride film 39 is selectively removed using the second sacrificial resist film pattern 41 as a mask, and then the second sacrificial resist film pattern 41 is removed.

그다음, 도 1d에 도시된 바와같이, 선택적으로 제거되고 잔류하는 질화막(39a)을 포함한 버퍼산화막(37)상에 스페이서용 질화막(43)을 증착한다.Then, as shown in FIG. 1D, a nitride nitride film 43 for spacers is deposited on the buffer oxide film 37 including the nitride film 39a that is selectively removed and remains.

이어서, 도 1e에 도시된 바와같이, 상기 스페이서용 질화막(43)을 에치백하여 상기 하드마스크용 질화막(39a)의 상면에 있는 질화막과 버퍼산화막(37)의 바닥면에 있는 질화막(43) 및 그 아래의 버퍼산화막(37)부분을 제거하여 랜딩플러그 콘택홀(미도시)을 형성한다. 이때, 상기 랜딩플러그 콘택홀(미도시)아래에 위치하는 상기 반도체기판(31)의 액티브영역(31a)이 드러나게 된다.Subsequently, as shown in FIG. 1E, the nitride nitride film 43 on the top surface of the hard mask nitride film 39a and the nitride film 43 on the bottom surface of the buffer oxide film 37 are etched back. A portion of the buffer oxide film 37 below is removed to form a landing plug contact hole (not shown). In this case, the active region 31a of the semiconductor substrate 31 positioned under the landing plug contact hole (not shown) is exposed.

그다음, 상기 랜딩플러그콘택홀(미도시)을 포함한 전체 구조의 상면에 랜딩플러그용 폴리실리콘층(미도시)을 증착한후 상기 랜딩플러그 콘택홀(미도시)에만 남도록 이를 전면식각하여 랜딩플러그(45)를 형성한다.Thereafter, a polysilicon layer (not shown) for the landing plug is deposited on the top surface of the entire structure including the landing plug contact hole (not shown), and then the front surface is etched so as to remain only in the landing plug contact hole (not shown). 45).

이어서, 상기 랜딩플러그(45)를 포함한 전체 구조의 상면에 층간절연막(47)을 증착한후 그 위에 레지스트막(미도시)을 도포한한다.Subsequently, an interlayer insulating film 47 is deposited on the upper surface of the entire structure including the landing plug 45, and then a resist film (not shown) is applied thereon.

그다음, 포토리소그라피 공정기술에 의해 상기 레지스트막(미도시)을 노광 및 현상공정을 거친후 패터닝하여 비트라인콘택홀(49)을 형성한다.Thereafter, the resist film (not shown) is subjected to an exposure and development process by a photolithography process technology and then patterned to form a bit line contact hole 49.

이어서, 상기 레지스트막(미도시)을 제거한후 상기 비트라인콘택홀(49)을 포함한 층간절연막(47)상에 비트라인(51)을 형성한다.Subsequently, after removing the resist film (not shown), a bit line 51 is formed on the interlayer insulating layer 47 including the bit line contact hole 49.

상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 금속배선 형성방법에 의하면, 랜딩플러그 콘택 식각 및 비트라인 콘택식각과 같은 비트라인 형성을 위한 공정진행중 발생할 수 있는 게이트와 비트라인간 브릿지를 방지할 수 있다.As described above, according to the method of forming the metal wiring of the semiconductor device according to the present invention, it is possible to prevent the bridge between the gate and the bit line that may occur during the process for forming the bit line such as the landing plug contact etching and the bit line contact etching. Can be.

또한, 공정중 얼라인 마진을 크게 가져갈 수 있어 포토공정이 용이해지는 장점이 있으며, 게이트와 비트라인간 브릿지로 인해 발생되는 로우(row) 및 컬럼(column)의 불량을 줄일 수 있기 때문에 수율 개선효과도 기대할 수 있다.In addition, there is a merit that the alignment margin can be greatly increased during the process, and thus the photo process becomes easy, and the defects in the rows and columns caused by the bridge between the gate and the bitline can be reduced, thereby improving the yield. You can also expect.

한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (4)

액티브지역과 필드지역으로 구분된 반도체기판의 액티브지역상에 도전물질층패턴을 형성하는 단계;Forming a conductive material layer pattern on an active region of the semiconductor substrate divided into an active region and a field region; 상기 도전물질층패턴을 포함한 반도체기판상면에 버퍼산화막을 형성하는 단계;Forming a buffer oxide film on an upper surface of the semiconductor substrate including the conductive material layer pattern; 상기 버퍼산화막상에 하드마스크 질화막을 형성하여 갭매립시키는 단계;Forming a hard mask nitride layer on the buffer oxide layer to fill a gap; 상기 도전물질층패턴사이의 하드마스크 질화막을 선택적으로 제거하는 단계;Selectively removing the hard mask nitride layer between the conductive material layer patterns; 상기 선택적으로 제거된 하드마스크 질화막을 포함한 전체 구조의 상면에 스페이서 질화막을 형성하는 단계;Forming a spacer nitride film on an upper surface of the entire structure including the selectively removed hard mask nitride film; 상기 스페이서 질화막 및 버퍼산화막을 선택적으로 제거하여 상기 반도체기판의 일부분을 드러나게 하는 랜딩플러그 콘택홀을 형성하는 단계;Selectively removing the spacer nitride layer and the buffer oxide layer to form a landing plug contact hole exposing a portion of the semiconductor substrate; 상기 랜딩플러그 콘택홀내에 랜딩플러그를 형성하는 단계;Forming a landing plug in the landing plug contact hole; 상기 랜딩플러그를 포함한 전체 구조의 상면에 층간절연막을 형성한후 상기 층간절연막내에 상기 랜딩플러그부분을 노출시키는 비트라인콘택홀을 형성하는 단계; 및Forming an interlayer insulating film on an upper surface of the entire structure including the landing plug, and then forming a bit line contact hole in the interlayer insulating film to expose the landing plug portion; And 상기 비트라인콘택홀을 포함한 층간절연막상에 상기 랜딩플러그와 전기적으로 연결되는 비트라인을 형성하는 단계를 포함하여 구성되는 것을 특징으로하는 반도체소자의 금속배선 형성방법.Forming a bit line electrically connected to the landing plug on the interlayer insulating layer including the bit line contact hole. 제1항에 있어서, 상기 도전물질층패턴은 폴리실리콘층과 텅스텐실리사이드층의 적층구조로 형성하는 것을 특징으로하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the conductive material layer pattern is formed by stacking a polysilicon layer and a tungsten silicide layer. 제1항에 있어서, 상기 랜딩플러그 콘택홀은 상기 스페이스 질화막과 버퍼 산화막을 에치백하여 형성하는 것을 특징으로하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the landing plug contact hole is formed by etching back the space nitride layer and the buffer oxide layer. 제1항에 있어서, 상기 랜딩플러그는 랜딩플러그콘택홀을 포함한 전체 구조의 상면에 폴리실리콘층을 증착한후 이를 전면식각하여 형성하는 것을 특징으로하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the landing plug is formed by depositing a polysilicon layer on an upper surface of the entire structure including a landing plug contact hole and etching the entire surface thereof.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140061072A (en) * 2012-11-13 2014-05-21 삼성전자주식회사 Semiconductor device and method for fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140061072A (en) * 2012-11-13 2014-05-21 삼성전자주식회사 Semiconductor device and method for fabricating the same

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