KR20040087458A - Method for forming element isolating film of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming an isolation layer of a semiconductor device is provided to prevent hump and INWE(Inverse Narrow Width Effect) by rounding a top corner of STI(Shallow Trench Isolation). CONSTITUTION: A pad oxide pattern(33) and a pad nitride pattern(35) are formed on a substrate(31). A polysilicon spacer and a nitride spacer are formed at both sidewalls of the pad patterns. A trench is formed by selectively etching the substrate using the spacers as a mask. The spacers are removed. An oxide layer(43) is grown on the resultant structure by oxidizing. A planarized oxide layer is filled in the trench. The planarized oxide layer and the oxide layer are polished to expose the nitride pattern. By removing the exposed nitride pattern, an isolation layer is then formed.

Description

Method for forming element isolating film of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to suppress the occurrence of edge moat in an STI process to improve the characteristics of the hump and the inverse narrow width effect (INWE). The present invention relates to a device isolation film forming method of a semiconductor device.

A method of performing an STI process, which is a device isolation process, in a semiconductor device manufacturing process is described below with reference to FIGS. 1A to 1E.

1A through 1E are cross-sectional views illustrating a method of forming a device isolation layer of a semiconductor device according to the related art.

In the method of forming a device isolation film of a semiconductor device according to the related art, as illustrated in FIG. 1A, a pad oxide film 13 and a pad nitride film 15 are sequentially stacked on a semiconductor substrate 11, and then trench formation regions are formed thereon. To form a photoresist pattern (not shown) defining a.

Then, the pad nitride film 15 is selectively removed using the photoresist pattern as a mask. In this case, the plasma activated by the combination of CHF ₃ / CF ₄ / O ₂ / Ar gas is used during the etching process of the nitride film 15. In addition, the combination gas may include CxFx (for example, C ₄ F ₈ , C ₂ F ₆ , C ₅ F _8, etc.).

Subsequently, as shown in FIG. 1B, the pad oxide layer 13 and the semiconductor substrate 11 are formed by using a plasma activated by a combination of Cl ₂ / O ₂ / Ar gas using the photoresist pattern (not shown) as a mask. The trench 17 is excessively etched to form the trench 17 in the semiconductor substrate 11. In this case, the etching gas may also include a gas such as Hx.

Then, a sacification (SAC) oxidation process is performed. At this time, silicon (Si) at the interface between the semiconductor substrate 11 and the pad oxide film 13 is oxidized to form some rounding, such as "A".

Subsequently, as shown in FIG. 1C, after removing the photoresist pattern (not shown), a planarization oxide film 19 filling the trench 17 is deposited on the upper surface of the entire structure including the trench 17. At this time, the planarization oxide film 19 is deposited to be high enough to fill the STI region.

Then, as shown in FIG. 1D, a chemical mechanical polishing process is performed to planarize leaving a portion of the nitride film 15.

Subsequently, as shown in FIG. 1E, the remaining nitride film 15 is removed by H ₃ PO ₄ or the like to form the device isolation film 19a. At this time, since the nitride film 15 exhibits an excellent selectivity with respect to the oxide film, only the planarized oxide film and the pad oxide film are slightly removed.

However, according to the prior art as described above, since the gate oxide film deposition is a very important process for the characteristics of the semiconductor device, in order to remove the foreign matter remaining before the gate oxide film deposition, it is removed with HF or mixed hydrofluoric acid (HF) and then the gate oxide film. Will be deposited.

However, as shown in FIG. 2, the edge moat is generated as the cleaning is performed with HF or HF / H ₂ O, BOE, and the like before the deposition of the gate oxide film. When such edge moves occur, a hump and an inverse narrow width effect (INWE) occur due to device characteristics, which may cause abnormal operation of the device.

Accordingly, the present invention has been made to solve the above problems of the prior art, and by suppressing the edge moat generated in the STI process to improve the characteristics of the hump, the inverse narrow width effect (INWE) by the normal operation of the device It is an object of the present invention to provide a method for forming a device isolation film of a semiconductor device that enables it.

1A through 1E are cross-sectional views illustrating a process of forming a device isolation film of a semiconductor device according to the prior art;

Figure 2 is a photograph showing that the moat phenomenon occurs in the device manufactured through the device isolation film forming process of the semiconductor device according to the prior art,

3A to 3I are cross-sectional views illustrating a process of forming an isolation layer in a semiconductor device according to the present invention.

[Description of Drawing Reference]

31 semiconductor substrate 33 pad oxide film

35 pad nitride film 37 photosensitive film pattern

39: polysilicon layer 39a: polysilicon layer pattern

41, 41a: nitride film 43: oxide film

45 planarization oxide film 45b device isolation film

B: corner

A device isolation film forming method of a semiconductor device according to the present invention for achieving the above object comprises the steps of: laminating a pad oxide film and a pad nitride film on a semiconductor substrate;

Forming a photoresist pattern defining a device isolation region on the pad nitride film;

Selectively removing the pad nitride layer and the pad oxide layer using the photoresist pattern as a mask to expose a portion of the semiconductor substrate;

Stacking the polysilicon layer and the nitride film on the upper surface of the entire structure including the pad nitride film pattern and the pad oxide film pattern, the portions of which are selectively removed after removing the photoresist pattern;

Selectively removing the nitride film to form a nitride film spacer, and then selectively removing the polysilicon layer pattern with a barrier;

Selectively removing the exposed semiconductor substrate portion using the spacer as a mask to form a trench in the semiconductor substrate, and then removing the nitride film spacer;

Performing an oxidation process to form an oxide film on the surface of the entire structure, and then forming a planarized oxide film thereon to fill gaps;

Selectively removing the planarization oxide layer and the oxide layer to stop etching in the pad nitride layer pattern region through a planarization process; And

And removing the remaining pad nitride layer pattern to form an isolation layer.

(Example)

Hereinafter, a method of forming a device isolation film of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

3A to 3I are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to the present invention.

In the method of forming a device isolation film of a semiconductor device according to the present invention, as illustrated in FIG. 3A, a pad oxide film 33 and a pad nitride film 35 are sequentially stacked on a semiconductor substrate 31, and then trench formation regions are formed thereon. A photosensitive film pattern 37 is formed to define the shape.

3B, the pad nitride film 35 and the pad oxide film 33 are selectively removed using the photosensitive film pattern 37 as a mask. At this time, during the etching process of the pad nitride layer 35, plasma activated by a combination of CHF ₃ / CF ₄ / O ₂ / Ar gas is used. In addition, the combination gas may include CxFx (for example, C ₄ F ₈ , C ₂ F ₆ , C ₅ F _8, etc.).

3C, the polysilicon layer 39 and the nitride film 41 are laminated on the entire structure after the photoresist pattern 37 is removed. At this time, the polysilicon layer 39 is deposited to a thickness of about 10 to 500 kPa, and the nitride film 41 is deposited to about 100 to 500 kPa.

Next, as shown in FIG. 3D, the nitride film 41 is subjected to dry etching with a blanket to form a nitride film spacer 41a, and then the polysilicon layer 39 is dry-etched with a barrier to the semiconductor substrate 31. To expose a portion of the. In this case, it is confirmed that a part of the semiconductor substrate 31 is exposed by removing the portions of the polysilicon layer 39 and the nitride layer 41 on the pad nitride layer 35 so that the pad nitride layer pattern 35 is exposed. In addition, the thickness of the pad nitride film pattern 35 is measured to determine the thickness of the nitride film, and thus, the polysilicon layer in the semiconductor substrate 31 in the trench formation region, which is exposed, is completely removed. Here, the dry etching of the nitride film spacer may be performed by dry etching using a plasma activated with CH ₃ / CF ₄ / Ar, and O ₂ / N ₂ may be added thereto, instead of CHF ₃ / CF ₄ , which is the main gas. CxFy gas may be used.

In addition, the dry etching of the polysilicon layer 39 as a barrier of the nitride film spacer is performed by dry etching using a plasma activated with Cl ₂ / HBr / He / O ₂ / Ar, and the like, and HBr / He / O You don't have to use ₂ , but instead use O ₂ .

As shown in Fig. 3D, it can be seen that the polysilicon layer pattern 39a has an " L " shape, in order to sufficiently secure the substrate region later.

Subsequently, as shown in FIG. 3E, the semiconductor substrate 31 is excessively dry-etched using the nitride film spacer 41a as a mask to form the trench 43. In this case, the trench 43 performs dry etching using a plasma activated by a combination of Cl ₂ / HBr / H ₂ / O _2, and the like. In this case, when the subsequent oxidation process is performed, the “L” shaped polysilicon layer 39a and the region B where the silicon (Si) of the trench region are exposed are oxidized in the shape of a buzz beak because of the oxidation. The "L" shape also serves as an important factor for preventing edge moats later.

Subsequently, as shown in FIG. 3F, the nitride film spacer 41a is removed to expose the " L " -shaped polysilicon layer pattern 39a, and then an oxidation process is performed to oxidize the portion. In this way, the “L” shaped polysilicon layer pattern 39a reacts with oxygen to change into an oxide film 45. In addition, since the oxidation progresses in the “B” region of FIG. 3E, the rounding is formed as in “C”.

In this way, the oxide film 45 is formed in the trench region and the sidewall portion of the nitride film pattern, and since the silicon substrate is exposed to a large extent as in " D " Can be prevented. In this case, the nitride film is removed in a downflow manner. In addition, the nitride film has an excellent selectivity and no loss of the polysilicon layer.

Next, as shown in FIG. 3G, the planarization oxide film 47 is deposited on the upper surface of the entire structure to fill the trench 43.

Subsequently, as shown in FIG. 3H, a chemical mechanical smoke screening process is performed to be stopped and planarized on the upper surface of the nitride film pattern 35.

3I, the nitride film remaining is removed using a phosphoric acid solution or the like to form the device isolation film 49a. In this case, the device isolation layer 49a is described as including both the planarization oxide layer 49 and the oxide layer 45.

When the process is completed in this way, the edge film can be prevented from forming because the oxide film is formed on the substrate.

As described above, according to the method of forming a device isolation film of a semiconductor device according to the present invention, the corner rounding of the STI is possible, and thus, the edge-movement phenomenon does not occur. This gets better.

On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (8)

Stacking a pad oxide film and a pad nitride film on a semiconductor substrate; Forming a photoresist pattern defining a device isolation region on the pad nitride film; Selectively removing the pad nitride layer and the pad oxide layer using the photoresist pattern as a mask to expose a portion of the semiconductor substrate; Stacking the polysilicon layer and the nitride film on the upper surface of the entire structure including the pad nitride film pattern and the pad oxide film pattern, the portions of which are selectively removed after removing the photoresist pattern; Selectively removing the nitride film to form a nitride film spacer, and then selectively removing the polysilicon layer pattern with a barrier; Selectively removing the exposed semiconductor substrate portion using the spacer as a mask to form a trench in the semiconductor substrate, and then removing the nitride film spacer; Performing an oxidation process to form an oxide film on the surface of the entire structure, and then forming a planarized oxide film thereon to fill gaps; Selectively removing the planarization oxide layer and the oxide layer to stop etching in the pad nitride layer pattern region through a planarization process; And Forming an isolation layer by removing the remaining pad nitride layer pattern. The method of claim 1, wherein the device is formed by dry etching using plasma activated with Cl ₂ / HBr / He-O ₂ / Ar during etching of the pad nitride layer. The method of claim 1, wherein the polysilicon layer has a thickness of 100 to 500 GPa and a nitride film of 100 to 500 GPa. The method of claim 1, wherein the nitride film spacer is formed by blanket dry etching, and an activated plasma using CHF ₃ / CF ₄ / Ar is used during dry etching. The method of claim 4, wherein a CxFy-based gas or an O ₂ / N ₂ gas is further added during the dry etching. The method of claim 1, wherein a dry etching process using an activated plasma comprising a combination of Cl ₂ / HBr / O ₂ / H ₂ gas is performed during the trench formation. The method of claim 1, wherein a nitric acid dip process is used to remove the remaining pad nitride film pattern. The method of claim 1, wherein the remaining polysilicon layer pattern is oxidized and the trench edges are rounded.