KR100923760B1 - Method for forming device isolation layer in semiconductor device - Google Patents

Method for forming device isolation layer in semiconductor device Download PDF

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KR100923760B1
KR100923760B1 KR1020020082775A KR20020082775A KR100923760B1 KR 100923760 B1 KR100923760 B1 KR 100923760B1 KR 1020020082775 A KR1020020082775 A KR 1020020082775A KR 20020082775 A KR20020082775 A KR 20020082775A KR 100923760 B1 KR100923760 B1 KR 100923760B1
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film
oxide film
silicon nitride
etching
polysilicon
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KR1020020082775A
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KR20040056204A (en
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조성필
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Abstract

본 발명은 STI 형성공정 이후에 화학 공정에 의하여 활성영역의 에지 부분이 침식되는 에지모트를 방지하기 위해, 패드산화막을 증착한 후, 실리콘 질화막을 증착하기 전에 박막 실리콘 질화막, 버퍼산화막, 폴리실리콘막을 증착하고, 포토레지스트를 이용하여 상기 폴리실리콘막까지 식각을 행하고 나서, 산화를 시킬 때 버퍼 산화막의 계면에서 산화되는 양의 차이를 이용하여 상기 식각에 의해 노출된 폴리 실리콘 측면을 산화시켜 능동 에지 부분의 산화막의 두께를 두껍게 함으로써 후속 화학공정에서 능동 에지 부분이 침식되는 것을 방지할 수 있는 반도체 소자의 소자분리막 형성방법을 제시한다.According to the present invention, after the STI forming process, the thin film silicon nitride film, the buffer oxide film, and the polysilicon film are deposited after the pad oxide film is deposited and the silicon oxide film is deposited before the deposition of the pad oxide film to prevent the edge mot from eroding the edge portion of the active region by a chemical process. Depositing, etching to the polysilicon film using a photoresist, and then oxidizing the polysilicon side exposed by the etching using the difference in amount oxidized at the interface of the buffer oxide film when oxidizing the active edge portion. By increasing the thickness of the oxide film of the present invention, a method of forming a device isolation film of a semiconductor device which can prevent the active edge portion from being eroded in a subsequent chemical process.

에지모트, STI, 필드산화막, 패드산화막, 박막 실리콘질화막 Edge Mot, STI, Field Oxide, Pad Oxide, Thin Film Silicon Nitride

Description

반도체 소자의 소자분리막 형성방법{METHOD FOR FORMING DEVICE ISOLATION LAYER IN SEMICONDUCTOR DEVICE}METHODS FOR FORMING DEVICE ISOLATION LAYER IN SEMICONDUCTOR DEVICE}

도 1a 내지 1e는 종래 기술에 의한 에지모트가 형성되는 반도체 제조 공정을 도시한 단면도들이다. 1A to 1E are cross-sectional views illustrating a semiconductor manufacturing process in which an edge mot according to the prior art is formed.

도 2a 및 2b는 종래 기술에 의해 에지모트가 형성된 것을 자세히 도시한 단면도들이다. 2A and 2B are cross-sectional views illustrating in detail an edge mott formed by the prior art.

도3a 내지 도3h는 본 발명의 바람직한 실시예에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위하여 도시한 단면도들이다.3A to 3H are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to a preferred embodiment of the present invention.

- 도면의 주요부분에 대한 부호의 설명 -   -Explanation of symbols for the main parts of the drawings-

100 : 실리콘 기판 102 : 패드 산화막100 silicon substrate 102 pad oxide film

103 : 박막 실리콘 질화막 104 : 버퍼 산화막103 thin film silicon nitride film 104 buffer oxide film

105 : 폴리 실리콘층 106 : 실리콘 질화막105: polysilicon layer 106: silicon nitride film

107 : 포토레지스트 108 : 산화된 폴리 실리콘층107 photoresist 108 oxidized polysilicon layer

109 : 필드 산화막
109: field oxide film

본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 보다 상세하게는, STI(shallow trench isolation) 공정을 이용한 반도체 소자의 소자분리막 형성방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device using a shallow trench isolation (STI) process.

현재의 반도체 소자 제조 공정 중에서 아이솔레이션 공정인 얕은 트렌치 아이솔레이션(shallow trench isolation; STI) 공정을 진행하는 전형적인 방법을 도 1a 내지 1e에 도시하였다. Exemplary methods of performing a shallow trench isolation (STI) process, which is an isolation process among current semiconductor device manufacturing processes, are illustrated in FIGS. 1A to 1E.

먼저, 도 1a에 도시한 바와 같이, 실리콘 기판(1) 상에 패드 산화막(2), 실리콘 질화막(3)을 연속하여 증착한다. First, as shown in FIG. 1A, the pad oxide film 2 and the silicon nitride film 3 are successively deposited on the silicon substrate 1.

이어서, 도 1b에 도시한 바와 같이, 실리콘 질화막(3) 상에 포토레지스트(4)를 도포한 후, 패터닝 공정을 수행한다. 그리고 나서, 실리콘 질화막(3)을 건식 식각한다. 그리고 나서, 실리콘 기판(1)을 STI 식각을 진행하여, 실리콘 기판(1) 내의 소정 영역에 트렌치(6)를 형성한다.Subsequently, as shown in FIG. 1B, after the photoresist 4 is applied onto the silicon nitride film 3, a patterning process is performed. Then, the silicon nitride film 3 is dry etched. Then, the silicon substrate 1 is subjected to STI etching to form the trench 6 in a predetermined region in the silicon substrate 1.

이어서, 도 1c에 도시한 바와 같이, 포토레지스트(4)를 제거한 후, 평탄화를 수행하기 위한 필드산화막(5)을 트렌치(6)가 형성된 실리콘 기판(1) 상에 트렌치(6)를 채울 수 있도록 충분하게 증착한다. 고밀도 플라즈마 화학 기상 증착법(high density plasma chemical vapoer deposition; HDP CVD)으로 필드산화막(5)을 증착할 수 있다.Subsequently, as shown in FIG. 1C, after removing the photoresist 4, the field oxide film 5 for planarization may be filled with the trench 6 on the silicon substrate 1 on which the trench 6 is formed. Enough to be deposited. The field oxide film 5 can be deposited by high density plasma chemical vapor deposition (HDP CVD).

다음 단계로, 도 1d에 도시한 바와 같이, 실리콘 기판(1) 상에 형성된 필드산화막(5)을 화학적 기계적 연마(chemical mechanical polishing; CMP)를 통하여 트렌치(6)를 충진한 필드산화막(5)만을 남기고 평탄화시킨다. 따라서, 트렌치 내에 필드산화막(5)이 채워진 실리콘 기판(1)을 얻게 된다. Next, as shown in FIG. 1D, the field oxide film 5 having the trench 6 filled with the trench 6 is formed by chemical mechanical polishing (CMP) of the field oxide film 5 formed on the silicon substrate 1. Flattening leaving only bay. Thus, the silicon substrate 1 filled with the field oxide film 5 in the trench is obtained.

도 1e에 도시한 바와 같이, H3PO4와 같은 식각액을 사용하여 남겨진 실리콘 질화막을 제거한다. 이 경우 H3PO4는 산화막과의 선택비가 우수한 특성을 보이기 때문에 평탄화를 위한 필드산화막(5)과 패드 산화막(2)은 약간만이 제거되게 된다.As shown in FIG. 1E, the remaining silicon nitride film is removed using an etchant such as H 3 PO 4 . In this case, since H 3 PO 4 has excellent selectivity with respect to the oxide film, only a small amount of the field oxide film 5 and the pad oxide film 2 for planarization are removed.

전술한 바와 같이 STI를 형성하기 위한 공정을 수행하고 나면, 실리콘 질화막을 제거한 후 폴리실리콘을 증착하기 전에 여러 가지 화학약품(chemical)을 사용하는 공정, 특히 산화막의 증착 이전에 불산(HF) 또는 희석된 불산용액, BOE(buffered oxide etchant) 등의 화학약품으로 세정 공정을 진행하는 과정에서, 도 2a에 도시한 바와 같이, 활성영역의 에지 부분이 침식되어 에지모트(edge moat)가 발생하게 된다. 도 2a 및 도 2b에서 (7)로 표시한 영역에서 에지모트가 발생하게 된다. 도 2b는 활성영역 에지 부분에 에지모트(7)가 발생한 상태에서 게이트용 폴리실리콘막(8)을 증착한 상태를 나타낸 단면도이다.After performing the process to form the STI as described above, a process using various chemicals before removing the silicon nitride film and depositing polysilicon, in particular hydrofluoric acid (HF) or dilution prior to deposition of the oxide film In the course of the cleaning process with a chemical such as hydrofluoric acid solution, buffered oxide etchant (BOE), as shown in Figure 2a, the edge portion of the active area is eroded to generate an edge moat. In the areas indicated by (7) in Figs. 2A and 2B, edgemots occur. FIG. 2B is a cross-sectional view illustrating a state in which the gate polysilicon film 8 is deposited in the state where the edge mot 7 is generated at the edge of the active region.

이러한 에지모트가 발생하게 되면, 소자 특성상 험프(hump) 및 INWE(inverse narrow width effect)가 발생하여 소자의 비정상적인 동작을 유발시키는 소자의 트랜지스터의 전기적 특성을 열화시키는 문제점이 존재하게 된다.
When such edge mot occurs, there is a problem in that a hump and an inverse narrow width effect (INWE) occur due to device characteristics, thereby deteriorating electrical characteristics of a transistor of the device causing abnormal operation of the device.

본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 STI 형성공정 이후에 화학 공정에 의하여 활성영역의 에지 부분이 침식되는 에지모트를 방지할 수 있는 반도체 소자의 소자분리막 형성방법을 제공하는 데 있다.The present invention was created to solve the above problems, and an object of the present invention is to form an isolation layer of a semiconductor device capable of preventing edge mottling of an edge portion of an active region by a chemical process after an STI forming process. To provide a way.

상기와 같은 목적을 실현하기 위한 본 발명은 실리콘기판 상에 패드산화막, 박막 실리콘질화막, 버퍼산화막, 폴리실리콘막 및 실리콘질화막을 순차적으로 형성하는 단계와, 소자분리영역의 실리콘질화막 및 폴리실리콘막을 식각하는 단계와, 식각에 의해 노출된 폴리실리콘막의 측면을 산화시키는 단계와, 실리콘질화막을 마스크로 이용하여 버퍼산화막, 박막 실리콘질화막 및 패드산화막을 식각하여 실리콘기판을 노출시키는 단계와, 노출된 영역의 실리콘기판을 식각하여 트렌치를 형성하는 단계와, 트렌치가 매립되도록 필드산화막을 형성하는 단계와, 실리콘질화막의 상부면이 노출될 때까지 필드산화막을 평탄화하는 단계와, 실리콘질화막과 폴리실리콘막을 제거하는 단계, 및 버퍼산화막, 박막 실리콘질화막 및 패드산화막을 제거함으로써 필드산화막의 에지에 박막 실리콘질화막의 일부가 남도록 하는 단계를 포함하는 것을 특징으로 한다.According to the present invention, a pad oxide film, a thin film silicon nitride film, a buffer oxide film, a polysilicon film, and a silicon nitride film are sequentially formed on a silicon substrate, and the silicon nitride film and the polysilicon film of the device isolation region are etched. Oxidizing the side surfaces of the polysilicon film exposed by etching, etching the buffer oxide film, the thin film silicon nitride film and the pad oxide film using a silicon nitride film as a mask to expose the silicon substrate, and Forming a trench by etching the silicon substrate; forming a field oxide film to fill the trench; planarizing the field oxide film until the upper surface of the silicon nitride film is exposed; and removing the silicon nitride film and the polysilicon film. And removing the buffer oxide film, the thin film silicon nitride film, and the pad oxide film. Characterized in that it comprises a portion of the thin silicon nitride film to leave the edges of the oxide film.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, this embodiment is not intended to limit the scope of the present invention, but is presented by way of example only.

도3a 내지 도3h는 본 발명의 바람직한 실시예에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위하여 나타낸 단면도들이다.3A to 3H are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to a preferred embodiment of the present invention.

먼저, 도3a에 도시된 바와 같이, 실리콘기판(100) 상에 패드산화막(102), 박막 실리콘질화막(103), 버퍼산화막(104), 폴리실리콘막(105) 및 실리콘질화막(106)을 순차적으로 형성한다.First, as shown in FIG. 3A, the pad oxide film 102, the thin film silicon nitride film 103, the buffer oxide film 104, the polysilicon film 105, and the silicon nitride film 106 are sequentially formed on the silicon substrate 100. To form.

그리고 나서, 도 3b에 도시된 바와 같이, 실리콘질화막(106) 상에 포토레지스트를 도포하고 패터닝을 하여 소정 형상으로 패터닝된 포토레지스트 패턴(107)을 형성한다. 포토레지스트 패턴(107)을 마스크로 이용하여 실리콘질화막(106) 및 폴리실리콘막(105)을 식각하여 버퍼산화막(104)의 소정 영역을 개방시킴으로써, 실리콘질화막(106)과 폴리실리콘(105)의 측면도 노출된다.Then, as shown in FIG. 3B, a photoresist is applied and patterned on the silicon nitride film 106 to form a patterned photoresist pattern 107 in a predetermined shape. The silicon nitride film 106 and the polysilicon film 105 are etched by using the photoresist pattern 107 as a mask to open a predetermined region of the buffer oxide film 104, thereby forming the silicon nitride film 106 and the polysilicon 105. The sides are also exposed.

이어서, 도 3c에 도시된 바와 같이, 실리콘 기판(100)에 대해 산화를 실시하면 노출된 폴리실리콘막(105)의 측면에서는 산화가 빠르게 진행되고 실리콘 기판(100)의 표면은 박막 실리콘질화막(103)이 산화가 진행되는 것을 차단하기 때문에 실리콘 기판(100)은 산화가 진행되지 않는다. 따라서, 노출된 폴리실리콘막(105)의 측면에서만 산화막(108)이 형성되게 된다. 또한, 본 발명의 바람직한 실시예에 따르면, 폴리실리콘막(105)을 산화시키는 단계에서 산화물의 계면에서의 산화 속도의 차이를 이용하여 아래쪽에서 산화가 많이 일어나게 된다.Subsequently, as shown in FIG. 3C, when the oxidation is performed on the silicon substrate 100, the oxidation proceeds rapidly on the exposed side of the polysilicon film 105, and the surface of the silicon substrate 100 is thin film silicon nitride film 103. ) Blocks the oxidation from proceeding, so that the silicon substrate 100 does not proceed with oxidation. Therefore, the oxide film 108 is formed only on the exposed side of the polysilicon film 105. In addition, according to a preferred embodiment of the present invention, in the step of oxidizing the polysilicon film 105, a lot of oxidation occurs at the bottom by using the difference in the oxidation rate at the interface of the oxide.

도 3d에 도시한 바와 같이, 실리콘질화막(106)을 하드 마스크로 이용하여 ㅋ탄소(C)와 플로린(F)을 포함하는 플라즈마를 이용하여 폴리실리콘막이 산화되어 형성된 산화막(108)과 버퍼산화막(104)을 식각한다. 그리고 나서, CH2F2 또는 CHF3를 포함하는 플라즈마를 이용하여 박막 실리콘질화막(103)을 식각하고 탄소(C)와 플로린(F)을 포함하는 플라즈마를 이용하여 패드산화막(102)을 식각한다. 이어서, 실리콘 기판(100)을 클로린(Cl2)을 포함하는 플라즈마와 HBr 또는 HeO2을 첨가제로 사용하여 트렌치 식각을 진행한다.As shown in FIG. 3D, the oxide film 108 and the buffer oxide film formed by oxidizing the polysilicon film using a plasma including a carbon (C) and a florin (F) using the silicon nitride film 106 as a hard mask. Etch 104). Then, the thin film silicon nitride film 103 is etched using a plasma containing CH 2 F 2 or CHF 3 and the pad oxide film 102 is etched using a plasma containing carbon (C) and florin (F). . Subsequently, the trench is etched using the plasma containing chlorine (Cl 2 ) and HBr or HeO 2 as an additive.

다음 단계로, 도 3e에 도시한 바와 같이, 트렌치 식각된 실리콘 기판(100)의 상부에 트렌치가 충진되도록 필드산화막(109)을 고밀도 플라즈마 화학기상 증착(high density plasma chemical vapor deposition; HDP CVD) 방법으로 형성한다.
이어서, 도 3f에 도시한 바와 같이, 필드산화막(109)을 화학적 기계적 연마(chemical mechanical polishing; CMP)를 이용하여 실리콘질화막(106)의 상부면이 나타날 때까지 평탄화를 진행한다.Next, as shown in FIG. 3E, the field oxide film 109 is subjected to high density plasma chemical vapor deposition (HDP CVD) to fill the trench on the trench-etched silicon substrate 100. To form.
Subsequently, as shown in FIG. 3F, the field oxide film 109 is planarized using chemical mechanical polishing (CMP) until the top surface of the silicon nitride film 106 appears.

삭제delete

그리고 나서, 도 3g에 도시한 바와 같이, 실리콘질화막과 폴리실리콘막을 제거한다.Then, as shown in Fig. 3G, the silicon nitride film and the polysilicon film are removed.

마지막으로, 도 3h에 도시한 바와 같이, 버퍼산화막, 박막 실리콘질화막(103)을 제거한다. 이때, 활성영역의 에지 부분에는 박막 실리콘질화막의 일부분(110)이 여전히 남아있게 되고, 트렌지내에 형성된 증착된 필드산화막(109)은 실리콘 기판(100)의 상부면 보다 높게 두껍게 형성되어 있어서 화학공정에 의하여 활성영역의 에지 부분이 공격받는 것을 방지하게 된다. 따라서, 본 발명에 따르면 에지모트 현상을 방지할 수 있게 된다.Finally, as shown in FIG. 3H, the buffer oxide film and the thin film silicon nitride film 103 are removed. At this time, the portion 110 of the thin film silicon nitride film still remains at the edge of the active region, and the deposited field oxide film 109 formed in the trench is formed thicker than the upper surface of the silicon substrate 100, thereby forming a chemical process. This prevents the edge portion of the active area from being attacked. Therefore, according to the present invention, it is possible to prevent the edge-mot phenomenon.

상기한 바와 같이 본 발명은 STI 에지 부분에 노출된 필드산화물이 화학 세정 공정을 거치면서 침식되는 현상인 에지모트 현상을 방지하기 위하여, 실리콘질화막을 증착하기 전에 박막 실리콘질화막, 버퍼산화막, 폴리실리콘막을 증착한 후 폴리실리콘막을 산화시킴으로서 최종적으로 형성된 STI 에지 부분에 박막 실리콘질화막을 남겨두고 필드산화막을 두껍게 하여 후속 화학 공정에서 활성영역의 에지 부분이 침식되는 현상을 방지할 수 있는 이점이 있다. As described above, the present invention provides a thin film silicon nitride film, a buffer oxide film, and a polysilicon film before depositing the silicon nitride film in order to prevent edge mott phenomenon, which is a phenomenon in which the field oxide exposed to the STI edge portion is eroded through the chemical cleaning process. By oxidizing the polysilicon film after deposition, the thin film silicon nitride film is left on the finally formed STI edge portion and the field oxide film is thickened to prevent the edge portion of the active region from being eroded in a subsequent chemical process.

또한, 에지모트는 험프(hump), INWE(inverse narrow width effect)와 같은 트랜지스터의 전기적 특성을 열화시키는 현상을 수반하기 때문에, 본 발명은 에지모트 현상을 제거함으로써 험프 및 INWE와 같이 트랜지스터의 전기적 특성을 열화시키는 현상을 동시에 제거함으로써 트랜지스터의 전기적 특성을 향상시킬 수 있는 장점을 갖게 된다.In addition, since edge-mot involves deterioration of electrical characteristics of transistors such as hump and inverse narrow width effect (INWE), the present invention eliminates the edge-moting phenomenon, thereby eliminating the electrical characteristics of transistors such as hump and INWE. By simultaneously eliminating the phenomenon of deterioration of the transistor has the advantage of improving the electrical characteristics of the transistor.

Claims (6)

실리콘기판 상에 패드산화막, 박막 실리콘질화막, 버퍼산화막, 폴리실리콘막 및 실리콘질화막을 순차적으로 형성하는 단계;Sequentially forming a pad oxide film, a thin film silicon nitride film, a buffer oxide film, a polysilicon film, and a silicon nitride film on a silicon substrate; 소자분리영역의 상기 실리콘질화막 및 폴리실리콘막을 식각하는 단계;Etching the silicon nitride film and the polysilicon film in the device isolation region; 식각에 의해 노출된 상기 폴리실리콘막의 측면을 산화시키는 단계;Oxidizing side surfaces of the polysilicon film exposed by etching; 상기 실리콘질화막을 마스크로 이용하여 상기 버퍼산화막, 박막 실리콘질화막 및 패드산화막을 식각하여 상기 실리콘기판을 노출시키는 단계;Etching the buffer oxide film, the thin film silicon nitride film, and the pad oxide film using the silicon nitride film as a mask to expose the silicon substrate; 노출된 영역의 상기 실리콘기판을 식각하여 트렌치를 형성하는 단계;Etching the silicon substrate in the exposed region to form a trench; 상기 트렌치가 매립되도록 필드산화막을 형성하는 단계;Forming a field oxide layer to fill the trench; 상기 실리콘질화막의 상부면이 노출될 때까지 상기 필드산화막을 평탄화하는 단계;Planarizing the field oxide layer until the top surface of the silicon nitride layer is exposed; 상기 실리콘질화막과 폴리실리콘막을 제거하는 단계; 및Removing the silicon nitride film and the polysilicon film; And 상기 버퍼산화막, 박막 실리콘질화막 및 패드산화막을 제거함으로써 상기 필드산화막의 에지에 상기 박막 실리콘질화막의 일부가 남도록 하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.And removing the buffer oxide film, the thin film silicon nitride film, and the pad oxide film so that a part of the thin film silicon nitride film remains at the edge of the field oxide film. 제1항에 있어서, The method of claim 1, 상기 폴리실리콘막의 측면을 산화시키는 단계에서,In the step of oxidizing the side of the polysilicon film, 산화물의 계면에서의 산화 속도의 차이를 이용하여 상기 폴리실리콘막의 측면 중 아래쪽에서 산화가 많이 일어나게 하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.The method of forming a device isolation film of a semiconductor device, characterized in that the oxidation occurs a lot from the lower side of the side of the polysilicon film by using the difference in the oxidation rate at the interface of the oxide. 제1항에 있어서,The method of claim 1, 상기 버퍼산화막, 박막 실리콘질화막 및 패드산화막을 식각하는 단계에서,Etching the buffer oxide film, the thin film silicon nitride film and the pad oxide film, 상기 버퍼산화막 및 패드산화막은 탄소(C)와 플로린(F)을 포함하는 플라즈마를 이용하여 식각하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.And the buffer oxide film and the pad oxide film are etched using a plasma containing carbon (C) and florin (F). 제3항에 있어서,The method of claim 3, 상기 버퍼산화막, 박막 실리콘질화막 및 패드산화막을 식각하는 단계에서,Etching the buffer oxide film, the thin film silicon nitride film and the pad oxide film, 상기 탄소(C)와 플로린(F)을 포함하는 플라즈마를 이용하여 상기 버퍼산화막 및 패드산화막을 식각할 때 상기 폴리실리콘막의 측면에 산화로 형성된 산화막이 동시에 식각되도록 하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.When etching the buffer oxide film and the pad oxide film using a plasma containing the carbon (C) and florin (F), the oxide film formed by oxidation on the side of the polysilicon film to be etched at the same time device Separator Formation Method. 제1항에 있어서, The method of claim 1, 상기 버퍼산화막, 박막 실리콘질화막 및 패드산화막을 식각하는 단계에서,Etching the buffer oxide film, the thin film silicon nitride film and the pad oxide film, 상기 박막 실리콘질화막은 CH2F2 또는 CHF3를 포함하는 플라즈마를 사용하여 식각하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.The thin film silicon nitride film is a method of forming a device isolation film of a semiconductor device, characterized in that the etching using a plasma containing CH 2 F 2 or CHF 3 . 제1항에 있어서, 상기 실리콘기판을 식각하여 트렌치를 형성하는 단계에서, 클로린(Cl2)을 포함하는 플라즈마와 HBr 또는 HeO2를 첨가제로 사용하여 식각하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.The method of claim 1, wherein in the forming of the trench by etching the silicon substrate, the device isolation film is formed using a plasma containing chlorine (Cl 2 ) and HBr or HeO 2 as an additive. Way.
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