KR20040068269A - 박형 산화물 라이너를 포함하는 반도체 소자 및 그 제조방법 - Google Patents

박형 산화물 라이너를 포함하는 반도체 소자 및 그 제조방법 Download PDF

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Publication number
KR20040068269A
KR20040068269A KR10-2004-7009490A KR20047009490A KR20040068269A KR 20040068269 A KR20040068269 A KR 20040068269A KR 20047009490 A KR20047009490 A KR 20047009490A KR 20040068269 A KR20040068269 A KR 20040068269A
Authority
KR
South Korea
Prior art keywords
substrate
oxide liner
semiconductor device
gate electrode
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR10-2004-7009490A
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English (en)
Korean (ko)
Inventor
루닝스코트
카도시다니엘
치크존디.
벌러제임스에프.
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20040068269A publication Critical patent/KR20040068269A/ko
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H10P30/212—Through-implantation

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
KR10-2004-7009490A 2001-12-19 2002-12-19 박형 산화물 라이너를 포함하는 반도체 소자 및 그 제조방법 Ceased KR20040068269A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US2103701A 2001-12-19 2001-12-19
US10/021,037 2001-12-19
PCT/US2002/041103 WO2003054951A1 (en) 2001-12-19 2002-12-19 Semiconductor device comprising a thin oxide liner and method of manufacturing the same

Publications (1)

Publication Number Publication Date
KR20040068269A true KR20040068269A (ko) 2004-07-30

Family

ID=21801954

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2004-7009490A Ceased KR20040068269A (ko) 2001-12-19 2002-12-19 박형 산화물 라이너를 포함하는 반도체 소자 및 그 제조방법

Country Status (7)

Country Link
JP (1) JP2005517285A (https=)
KR (1) KR20040068269A (https=)
CN (1) CN1322565C (https=)
AU (1) AU2002358269A1 (https=)
DE (1) DE10297582T5 (https=)
GB (1) GB2399222B (https=)
WO (1) WO2003054951A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583016B1 (en) * 2002-03-26 2003-06-24 Advanced Micro Devices, Inc. Doped spacer liner for improved transistor performance
JP2008124441A (ja) * 2006-10-19 2008-05-29 Tokyo Electron Ltd 半導体装置の製造方法
DE102011005641B4 (de) * 2011-03-16 2018-01-04 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Verfahren zur Leistungssteigerung in Transistoren durch Reduzierung der Absenkung aktiver Gebiete und durch Entfernen von Abstandshaltern

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868617A (en) * 1988-04-25 1989-09-19 Elite Semiconductor & Sytems International, Inc. Gate controllable lightly doped drain mosfet devices
US5714413A (en) * 1995-12-11 1998-02-03 Intel Corporation Method of making a transistor having a deposited dual-layer spacer structure
US6472281B2 (en) * 1998-02-03 2002-10-29 Matsushita Electronics Corporation Method for fabricating semiconductor device using a CVD insulator film
US6162692A (en) * 1998-06-26 2000-12-19 Advanced Micro Devices, Inc. Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor
US6251764B1 (en) * 1999-11-15 2001-06-26 Chartered Semiconductor Manufacturing Ltd. Method to form an L-shaped silicon nitride sidewall spacer
US6294480B1 (en) * 1999-11-19 2001-09-25 Chartered Semiconductor Manufacturing Ltd. Method for forming an L-shaped spacer with a disposable organic top coating
US6156598A (en) * 1999-12-13 2000-12-05 Chartered Semiconductor Manufacturing Ltd. Method for forming a lightly doped source and drain structure using an L-shaped spacer
US6277700B1 (en) * 2000-01-11 2001-08-21 Chartered Semiconductor Manufacturing Ltd. High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness

Also Published As

Publication number Publication date
GB0412884D0 (en) 2004-07-14
CN1322565C (zh) 2007-06-20
AU2002358269A1 (en) 2003-07-09
GB2399222B (en) 2005-07-20
JP2005517285A (ja) 2005-06-09
WO2003054951A1 (en) 2003-07-03
GB2399222A (en) 2004-09-08
CN1606801A (zh) 2005-04-13
DE10297582T5 (de) 2004-11-11

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