KR20040059454A - Method for forming storage node contact in semiconductor - Google Patents
Method for forming storage node contact in semiconductor Download PDFInfo
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- KR20040059454A KR20040059454A KR1020020086202A KR20020086202A KR20040059454A KR 20040059454 A KR20040059454 A KR 20040059454A KR 1020020086202 A KR1020020086202 A KR 1020020086202A KR 20020086202 A KR20020086202 A KR 20020086202A KR 20040059454 A KR20040059454 A KR 20040059454A
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- storage node
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000003860 storage Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000005498 polishing Methods 0.000 claims abstract description 21
- 239000000126 substance Substances 0.000 claims abstract description 20
- 150000004767 nitrides Chemical class 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 239000002002 slurry Substances 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 239000003082 abrasive agent Substances 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
본 발명은 반도체 소자의 스토리지 노드 컨택 형성 방법에 관한 것으로서, 보다 상세하게는 비트 라인의 상부에 버퍼 산화막을 증착하여 화학기계적 연마에서의 디싱(Dishing) 현상을 방지한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a storage node contact of a semiconductor device, and more particularly, to prevent dishing in chemical mechanical polishing by depositing a buffer oxide layer on an upper portion of a bit line.
종래의 반도체 소자의 스토리지 노드 컨택 형성 방법에 따르면, 화학기계적 연마에 대하여 막질의 특성 별로 연마 속도가 상이하기 때문에 디싱이 발생되는 문제가 있다.According to the conventional method for forming a storage node contact of a semiconductor device, dishing occurs because the polishing rate is different depending on the characteristics of the film with respect to chemical mechanical polishing.
도 1을 참조하면, 비트 라인은 메탈 라인(1)의 상부에 마스크 질화막(2)이 형성되고, 이들의 측벽에 스페이서(3)가 형성된 구조를 갖는다.Referring to FIG. 1, the bit line has a structure in which a mask nitride film 2 is formed on the metal line 1, and spacers 3 are formed on sidewalls thereof.
그리고, 비트 라인이 형성된 상부에 비트 라인 분리를 위한 산화막(4)을 증착한 후 이를 라인 형태를 갖도록 식각하며, 전면에 다시 폴리 실리콘(5)을 증착한다.Then, the oxide film 4 for the bit line separation is deposited on the bit line formed thereon, and then etched to have a line shape, and polysilicon 5 is deposited on the entire surface.
그 후, 스토리지 노드 컨택을 형성하기 위한 화학기계적 연마가 수행된다.Thereafter, chemical mechanical polishing is performed to form the storage node contacts.
그러나, 비트 라인의 상부 마스크 질화막(2)은 산화막(4)과 폴리 실리콘(5)과 비교하여 화학기계적 연마가 느리게 진행된다.However, the chemical mechanical polishing is slower in the upper mask nitride film 2 of the bit line than in the oxide film 4 and the polysilicon 5.
그러므로, 비트 라인의 상부에 위치한 마스크 질화막(2)이 노출되는 시점까지 화학기계적 연마가 진행되면, 도 2와 같이 마스크 비트 라인의 측방향에 위치한 산화막(4)과 폴리 실리콘(5)의 연마된 레벨이 질화막(2) 보다 낮아지는 디싱 현상이 발생된다.Therefore, when the chemical mechanical polishing is performed until the mask nitride film 2 positioned on the bit line is exposed, the oxide film 4 and the polysilicon 5 polished as shown in FIG. A dishing phenomenon occurs in which the level is lower than that of the nitride film 2.
상기한 디싱은 후속 캐패시터 제조 공정에서 패터닝을 어렵게 만드는 등 반도체 소자의 신뢰성을 저하시키는 주 요인이 되는 문제점이 있다.The dishing has a problem in that reliability of the semiconductor device is deteriorated, such as making patterning difficult in a subsequent capacitor manufacturing process.
본 발명의 목적은 비트 라인의 상부에 버퍼 산화막을 형성함으로써 반도체 소자의 스토리지 노드 컨택 형성 과정에 있어서 발생되는 디싱 현상을 해소함에 있다.An object of the present invention is to form a buffer oxide layer on an upper part of a bit line, thereby eliminating dishing occurring during a storage node contact formation process of a semiconductor device.
도 1 및 도 2는 종래의 반도체 소자의 스토리지 노드 컨택 형성 방법의 공정도1 and 2 are process diagrams of a method for forming a storage node contact of a conventional semiconductor device
도 3 내지 도 6은 본 발명에 따른 반도체 소자의 스토리지 노드 컨택 형성 방법의 바람직한 실시예를 나타내는 공정도3 to 6 are process diagrams showing a preferred embodiment of the method for forming a storage node contact of a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 스토리지 노드 컨택 형성 방법은, 메탈 라인과 마스크 질화막 및 버퍼 산화막을 적층하고 스페이서를 형성하여 비트 라인들을 형성하는 제 1 공정; 산화막을 전면 도포하고 상기 비트라인들 상부의 스토리지 컨택 노드를 형성할 영역에 대하여 식각하고, 전면에 걸쳐서 폴리 실리콘을 증착하는 제 2 공정; 화학기계적 연마를 진행하여 마스크 질화막까지 연마하여 스토리지 노드 컨택을 형성하는 제 3 공정을 구비한다.A method of forming a storage node contact of a semiconductor device according to the present invention includes: a first process of stacking a metal line, a mask nitride film, and a buffer oxide film, and forming a spacer to form bit lines; A second process of applying an oxide layer over the entire surface, etching the region to form a storage contact node over the bit lines, and depositing polysilicon over the entire surface; And a third process of performing chemical mechanical polishing to polish the mask nitride film to form a storage node contact.
여기에서, 상기 버퍼 산화막은 BPSG(boron/phosphorus-doped silicon oxide) 또는 FSG(Fluorine-doped silicon oxide) 중 어느 하나의 증착될 수 있으며, 그 두께는 200Å 내지 1000Å으로 형성됨이 바람직하다.Here, the buffer oxide film may be deposited of any one of BPSG (boron / phosphorus-doped silicon oxide) or FSG (Fluorine-doped silicon oxide), the thickness is preferably formed of 200 ~ 1000Å.
이하, 본 발명에 따른 반도체 소자의 스토리지 노드 컨택 형성 방법의 바람직한 실시예에 대하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a preferred embodiment of a method of forming a storage node contact of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
본 발명은 비트 라인의 상부에 화학기계적 연마에 대한 연마 속도가 분리 산화막 및 폴리실리콘에 비하여 빠른 버퍼 산화막을 형성하며, 그에 따라서 디싱이 발생하지 않는 스토리지 노드 컨택을 형성한다.The present invention forms a buffer oxide film on the upper part of the bit line with a faster polishing rate for chemical mechanical polishing than a separate oxide film and polysilicon, thereby forming a storage node contact in which dishing does not occur.
도 3 내지 도 6을 참조하여 본 발명에 따른 실시예를 설명한다.An embodiment according to the present invention will be described with reference to FIGS. 3 to 6.
비트 라인들이 도 3과 같이 형성되며, 각 비트 라인은 메탈 라인(1)과 마스크 질화막(2) 및 버퍼 산화막(8)이 순차적으로 적층되고, 이들의 양측에 스페이서(3)가 형성된 구조를 갖는다.Bit lines are formed as shown in FIG. 3, and each bit line has a structure in which a metal line 1, a mask nitride film 2, and a buffer oxide film 8 are sequentially stacked, and spacers 3 are formed on both sides thereof. .
비트 라인은 마스크 질화막(2) 대신 마스크 SiON이 증착된 구조를 가질 수 있다.The bit line may have a structure in which a mask SiON is deposited instead of the mask nitride film 2.
버퍼 산화막은 BPSG(boron/phosphorus-doped silicon oxide), FSG(Fluorine-doped silicon oxide) 등으로 화학기상증착되는 것이며, 200Å 내지 1000Å의 두께를 갖도록 형성됨이 바람직하다. 버퍼 산화막은 포토레지스트를 이용하여 형성될수 있다.The buffer oxide film is chemical vapor deposited by boron / phosphorus-doped silicon oxide (BPSG), fluorine-doped silicon oxide (FSG), or the like, and is preferably formed to have a thickness of 200 kV to 1000 kPa. The buffer oxide film can be formed using a photoresist.
스토리지 노드 컨택은 비트 라인들의 상부에 형성되며, 이를 위하여 분리 산화막으로서 산화막(4)이 전면에 증착된 후 라인 형태의 해당 영역을 제외한 나머지가 식각으로 제거된다. 그 후 전면에 걸쳐서 폴리 실리콘(5)이 증착된다.The storage node contacts are formed on the bit lines, and for this purpose, after the oxide layer 4 is deposited on the front surface as a separate oxide layer, the remaining portions except for the corresponding region in the form of lines are etched away. Then polysilicon 5 is deposited over the entire surface.
분리 산화막인 산화막(4)은 고밀도 플라즈마 산화막(고밀도 플라즈마 화학기상증착 산화막) 또는 PE-TEOS, O3-TEOS 등으로 형성될 수 있다.The oxide film 4, which is a separation oxide film, may be formed of a high density plasma oxide film (high density plasma chemical vapor deposition oxide film) or PE-TEOS, O 3 -TEOS, or the like.
상기한 산화막(4)과 폴리 실리콘(5)은 스토리지 노드 컨택을 형성하기 위하여 화학기계적 연마에 의하여 연마되며, 이를 위한 화학기계적 연마에 사용되는 슬러리는 50㎚ 내지 300㎚ 크기의 실리카, 알루미나 연마제가 첨가되고 pH 8 내지 pH 11을 유지함이 바람직하다. 그리고, 실리카 연마제 대신 세리아-베이스(Ceria-base) 연마제가 이용될 수 있다.The oxide film 4 and the polysilicon 5 are polished by chemical mechanical polishing to form a storage node contact. The slurry used for the chemical mechanical polishing includes silica and alumina abrasives having a size of 50 nm to 300 nm. It is preferred to add and maintain pH 8 to pH 11. And, instead of silica abrasive, Ceria-base abrasive may be used.
버퍼 산화막(8)은 폴리실리콘(5)이나 산화막(4)에 비하여 화학기계적 연마가 빠르게 진행되는 특성을 갖는다.The buffer oxide film 8 has a characteristic that the chemical mechanical polishing proceeds faster than the polysilicon 5 or the oxide film 4.
그러므로, 화학기계적 연마가 버퍼 산화막(8)이 제거되어 비트 라인의 마스크 질화막(2)이 드러날 때까지 계속되면, 도 5의 A와 같은 험프(Hump)가 형성된다.Therefore, if the chemical mechanical polishing is continued until the buffer oxide film 8 is removed and the mask nitride film 2 of the bit line is exposed, a Hump as shown in FIG. 5A is formed.
이 상태에서 화학기계적 연마가 계속되면, 마스크 질화막(2)이 폴리실리콘(5)이나 산화막(4)에 비하여 화학기계적 연마가 느리게 진행되므로 펌프가 제거되며, 결국 도 6과 같이 디싱이 발생되지 않는 스토리지 컨택 노드가 형성된다.If the chemical mechanical polishing is continued in this state, since the chemical mechanical polishing proceeds slower than that of the polysilicon 5 or the oxide film 4, the pump is removed, and as a result, dishing does not occur as shown in FIG. A storage contact node is formed.
상기한 도 6과 같이 화학기계적 연마가 완료되면 클리닝 공정이 후속된다.As shown in FIG. 6, when the chemical mechanical polishing is completed, the cleaning process is followed.
따라서, 본 발명에 의하면 스토리지 컨택 노드 형성 과정에서 디싱의 발생이 방지되며, 그에 의하여 후속 캐패시터 제조 공정에서 패터닝이 용이해지고, 반도체 소자의 신뢰성이 확보되는 효과가 있다.Therefore, according to the present invention, dishing is prevented during the storage contact node formation process, thereby facilitating patterning in a subsequent capacitor manufacturing process and securing reliability of a semiconductor device.
Claims (10)
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| KR (1) | KR100881837B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170002769U (en) | 2016-01-26 | 2017-08-03 | 주식회사 영일프레시젼 | Supporting Part with Heat Sink and Stacking Structure thereof |
| KR20180002793U (en) | 2017-03-21 | 2018-10-01 | 주식회사 영일프레시젼 | Heat Sink with Bottom Portion |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100333543B1 (en) * | 1998-12-30 | 2002-09-17 | 주식회사 하이닉스반도체 | Method for forming gate electrode of semiconductor device |
| KR100352909B1 (en) * | 2000-03-17 | 2002-09-16 | 삼성전자 주식회사 | Method of forming self-aligned contact structure in semiconductor device and self-aligned contact structure fabricated thereby |
| KR100598165B1 (en) * | 2000-08-31 | 2006-07-10 | 주식회사 하이닉스반도체 | Method For Forming The Contact Of Semi-conductor Device |
| KR100623611B1 (en) * | 2000-12-18 | 2006-09-12 | 주식회사 하이닉스반도체 | Method for chemical mechanical polishing of semiconductor device |
-
2002
- 2002-12-30 KR KR1020020086202A patent/KR100881837B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170002769U (en) | 2016-01-26 | 2017-08-03 | 주식회사 영일프레시젼 | Supporting Part with Heat Sink and Stacking Structure thereof |
| KR20180002793U (en) | 2017-03-21 | 2018-10-01 | 주식회사 영일프레시젼 | Heat Sink with Bottom Portion |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100881837B1 (en) | 2009-02-03 |
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