JP4039504B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including an element isolation portion.
[0002]
[Prior art]
In order to electrically isolate elements in a semiconductor integrated circuit, a method of selectively oxidizing a semiconductor substrate to form a thick field oxide film, a so-called mouth cost method (LOCOS method) has been used. However, since the bird's beak appears at the end of the field oxide film in the LOCOS method, a wide element isolation portion is required. Therefore, the element must be designed in consideration of this, and there is a problem that the element region becomes narrow.
[0003]
With the recent high integration of semiconductor integrated circuits, a method using trench isolation that can make the element isolation portion smaller is being adopted. In the trench isolation method, a trench (trench) having a depth necessary for electrically isolating elements is provided in a region where the elements are to be isolated, and this trench is buried by an insulator or the like. In this method, electrical insulation is performed between regions sandwiching a trench. By this method, a sufficiently small trench can be formed as compared with the element size, and higher integration of the semiconductor integrated circuit can be achieved.
[0004]
For example, in Japanese Patent Publication No. 7-79127, a trench is formed in a semiconductor substrate, and an insulating film such as TEOS (Tetra-Ethyl-Ortho-Silicate) is deposited on the substrate so as to fill the trench, and the substrate is exposed. Until now, a method of forming an element isolation portion by performing an etch back method or a chemical mechanical polishing (CMP) method is described.
[0005]
Further, with the progress of semiconductor integrated circuit technology, a method has been proposed in which not only one type of element isolation portion but also trench element isolation portions having different depths are used as needed in the circuit.
[0006]
For example, in a CMOS circuit, a deep element isolation part is provided for element isolation between different wells, and a shallow element isolation part is provided for element isolation in the same well, thereby reliably preventing latch-up and Can also be achieved. On the other hand, in the bipolar circuit, a high-speed, high-breakdown-voltage bipolar element can be formed by providing a shallow isolation region for improving the base-collector breakdown voltage in addition to the normal deep element isolation portion. Furthermore, even in a circuit where both bipolar and CMOS exist, element isolation of two kinds of depths is necessary. Such trenches having different depths are conventionally formed by repeating a normal trench forming process twice or more and changing the etching time and etching conditions in the etching process for forming each trench.
[0007]
For example, a method for forming trenches having different depths described as a conventional example in Japanese Patent Laid-Open No. 7-66276 will be described below.
[0008]
First, SiO for use as an etching mask when performing trench etching later on the surface of a silicon wafer used as a semiconductor substrate. ₂ A film is formed.
[0009]
Then, by photolithography, SiO ₂ A resist pattern having an opening only in the first trench region is formed on the film, and the resist pattern is used as an etching mask to form SiO. ₂ The film is etched by a dry etching method.
[0010]
Furthermore, SiO ₂ After removing the resist pattern used as an etching mask for the film, SiO is opened only in the first trench region ₂ A first trench is obtained by etching the surface of the silicon wafer using the film as an etching mask. Next, the inside of the formed first trench is SiO 2 by thermal oxidation and CVD. ₂ The first trench isolation region is formed by filling in and planarizing the surface. Next, SiO that functions as an etching mask used to form the second trench region ₂ A film is formed, and then a resist pattern having an opening only in the second trench region is formed by photolithography as in the case of the first trench, and this resist pattern is used as an etching mask to form SiO. ₂ The film is etched by a dry etching method.
[0011]
Furthermore, SiO ₂ After removing the resist pattern used as an etching mask for the film, SiO is opened only in the second trench region ₂ A second trench is formed by etching the silicon wafer surface using the film as an etching mask. At this time, a second trench having a different depth and shape can be formed by changing the trench etching conditions from those in the first trench formation process.
[0012]
Next, SiO into the second trench ₂ The trench isolation region having two different depths can be formed by embedding and further planarizing the wafer surface.
[0013]
[Problems to be solved by the invention]
However, in the conventional method as described above, in order to form trenches having different depths, the entire trench isolation formation process must be repeated according to the number of types of trenches, so the number of steps is greatly increased. There was a problem of doing. Furthermore, in order to form a resist, each exposure that requires alignment must be performed independently. For this reason, there has been a problem that an alignment error occurs between the trenches.
[0014]
In order to solve such a problem, the above-mentioned Japanese Patent Application Laid-Open No. 7-66276 proposes a method for devising an etching mask and a method using ion implantation. However, in any method, it is necessary to use the photolithography method twice, and an extra step is included, resulting in a decrease in throughput.
[0015]
On the other hand, Japanese Patent Laid-Open No. 9-260485 discloses a method of forming trench element isolation portions having different depths by using a microloading effect during etching. When this method is used, the element isolation depth depends on the element isolation width, that is, the trench opening width when the trench is formed by etching. Specifically, it is formed deep in a region having a wide trench opening width and shallow in a region sandwiching the trench opening width.
[0016]
According to this method, when a trench is buried by an insulator after the trench is formed by etching, the trench having a wide opening width and a deep depth is buried in the deposited film thickness of a layer such as an insulating film deposited thereon. There was a problem that it had to be made large and manufacturing was very difficult. For example, as shown in FIG. 10, a trench 12 having a wide opening width and a trench 13 having a narrow opening width formed on a semiconductor substrate 11 are buried by depositing an insulator material to form a buried insulator film 14. In some cases, a portion 15 is formed in the trench 12 which is not well filled. Therefore, there is a problem that a dent (step) is formed on the wafer substrate, dust is generated and etching is defective, and the yield is lowered. Further, such a step also affects electrical performance, causing a kink phenomenon in the current-voltage characteristics of the transistor, and a stable device design cannot be performed.
[0017]
On the other hand, in a region where the trench opening width is narrow, the design is generally performed with a minimum processing dimension. When manufacturing trench element isolations having different depths using the microloading effect as described above, the microloading effect is more noticeable as the trench opening width is smaller. Therefore, when the trench opening width is designed with the minimum processing dimension, there is a problem that the etching depth is easily influenced depending on a slight variation in the opening width and the shape of the etching pattern, and the trench depth changes greatly. Therefore, there is a problem that it is difficult to stably operate the device and it is difficult to design the device.
[0018]
An object of the present invention is to solve the above-described problems, minimize the increase in the number of steps of the trench formation process, and form a trench having different depths with good control and without causing an alignment error. It is to provide a method for manufacturing an apparatus.
[0019]
A method for manufacturing a semiconductor device of the present invention includes: A step of depositing a mask layer on the oxide film of the semiconductor substrate on which the oxide film is formed, and a first opening and a second opening respectively reaching the oxide film on the mask layer, the second opening A step of forming under the condition that the opening width of the portion is wider than the opening width of the first opening portion and a reverse microloading effect is generated by plasma etching in the oxide film, and then the oxidation is performed using the mask layer as a mask. By performing plasma etching on the film, a third opening that reaches the semiconductor substrate corresponding to the first opening and a fourth that does not reach the semiconductor substrate corresponding to the second opening are formed in the oxide film. Forming the openings, and then using the oxide film as a mask, the oxide film and the semiconductor substrate, and the etching rate of the semiconductor substrate is higher than the etching rate of the oxide film. By etching under a larger condition, a trench is formed in the region of the semiconductor substrate corresponding to each of the third opening and the fourth opening than in the region corresponding to the fourth opening. Forming deep in a region corresponding to the portion. .
[0020]
In a preferred embodiment, Following the step of forming the trench, depositing a dielectric material on the semiconductor substrate, filling the trench with the dielectric material, and then exposing the surface of the semiconductor substrate to expose the dielectric And further removing the material. .
[0026]
The operation of the present invention will be described below.
[0027]
According to the present invention, the first region and the second region wider than the first region are formed in the mask layer by etching, and the semiconductor substrate is etched using the mask layer as a mask to form the second region in the first region. A trench deeper than the region is formed. The two types of trenches formed in this manner have a shallower depth when they are wider, and therefore show good step coverage (step coverage) when an element isolation portion is formed by embedding them. Such a method of forming two types of trenches having a wider width and a shallower depth is that the etching rate of the semiconductor substrate and / or the mask layer is higher than that of the first region and the second region wider than the first region. This is achieved by utilizing different phenomena (microloading effect and / or reverse microloading effect).
[0028]
In a preferred embodiment of the present invention, the etching rate in the first region of the semiconductor substrate is faster than the etching rate in the second region wider than the first region. This is achieved by appropriately selecting etching conditions such as pressure and utilizing the reverse microloading effect. In a preferred embodiment, the pressure during etching of the semiconductor substrate is 1 mTorr or more and 90 mTorr or less. Thus, the reverse microloading effect can be effectively brought about by making the pressure condition relatively low.
[0029]
In a preferred embodiment of the present invention, in the mask layer etching step, mask layers having different thicknesses remain in the first region and the second region. This is because the etching conditions of the mask layer are appropriately selected so that the etching rate in the first region is higher than the etching rate in the second region which is wider than the first region, that is, the reverse microloading effect is brought about. Is achieved. The mask layer residual film thickness of the first region thus formed is thinner than that of the second region. By using the mask layer having the first region whose mask layer residual film thickness is thinner than that of the second region as a mask, it is possible to use the fact that the etching selectivity between the mask layer and the semiconductor substrate is different. Therefore, it is possible to form two types of trenches having a shallower depth with a wider width.
[0030]
Alternatively, in the above mask layer etching process, leaving the mask layers having different thicknesses in the first region and the second region may cause the etching rate in the first region as shown in a preferred embodiment of the present invention. This is achieved by plasma etching the mask layer including the antioxidant film so as to be slower than the etching rate in the second region wider than the first region, that is, to provide a microloading effect. The mask layer residual film thickness of the first region thus formed is thicker than that of the second region. Furthermore, as shown in a preferred embodiment of the present invention, by oxidizing the semiconductor substrate using a mask layer having a first region that includes an antioxidant film and has a mask layer residual film thickness larger than that of the second region as a mask, An oxide film can be selectively formed only in the second region. Thereby, it can be used that the etching selectivity of the mask layer and the oxide film and the semiconductor substrate is different. Therefore, it is possible to form two types of trenches having a shallower depth with a wider width.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
Throughout this specification, the term “opening” shall indicate that the entire layer need not be removed in that “opening” region, but that the layer has at least a recess. At this time, the width of the “opening” region in the direction horizontal to the substrate surface is set to “opening width” or “trench opening width” because it is equal to the width of the trench formed in this “opening” region.
[0032]
In general, when a trench is formed by etching a substrate through regions having different opening widths, the etched depth is not substantially constant and depends on the size of the opening width (trench opening width). For example, when etching is performed under a relatively high pressure condition, the etching rate decreases as the opening width becomes narrower. Such a phenomenon is generally called “microloading effect” and is well known.
[0033]
As shown in FIG. 1A, the microloading effect becomes more prominent as the trench opening width becomes narrower, and the etching rate also decreases rapidly. It is generally said that such a phenomenon is caused by the fact that radicals in the plasma are affected by the shape of the trench during etching, and the amount of penetration into the deep portion of the trench is limited. In FIG. 2A, a region having an opening width of about 0.3 μm and about 2.0 μm is formed in the silicon oxide film 22, and Cl 2 is used under relatively high pressure conditions (eg, using a magnetron RIE apparatus). ₂ = 40 sccm, O ₂ = 6 sccm, gas pressure = 100 mTorr, RF power = 1000 W) The shape of the trench after etching is shown. The trench 23 having an opening width of about 0.3 μm has an etching depth of about 0.5 μm, and the trench 24 having an opening width of about 2.0 μm has an etching depth of about 1.0 μm.
[0034]
On the other hand, the present inventors have found that when etching is performed by high-density plasma etching under low pressure conditions, in addition to the microloading effect, changes as shown in FIG. I found it. In the region (x) in FIG. 1B, the micro-rotating effect occurs as in the conventional case. However, in the region (y) in FIG. 1B, the etching rate is higher than that in the region (z). Such a phenomenon is contrasted with the microloading effect and is attributed to the “reverse microloading effect”. FIG. 2B shows a case where a region having an opening width of about 0.3 μm and about 2.0 μm is formed in the silicon oxide film 22 under a relatively low pressure condition (for example, using an ECR apparatus, Cl ₂ = 40 sccm, O ₂ The shape of the trench after etching under the conditions of = 6 sccm, gas pressure = 3 mTorr, microwave power = 220 W, and RF power = 90 W is shown. The trench 23 having an opening width of about 0.3 μm has an etching depth of about 1.05 μm, and the trench 24 having an opening width of about 2.0 μm has an etching depth of about 0.8 μm.
[0035]
The range in which such a phenomenon occurs varies depending on the etching gas, but hardly occurs when the pressure during etching is relatively high, and occurs when the pressure is relatively low. Specifically, it occurred when the pressure was in the range of about 1 mTorr to about 90 mTorr, and was particularly noticeable when the pressure was in the range of about 1 mTorr to about 10 mTorr. Under relatively low conditions where the etching pressure is in the range of about 1 mTorr to about 90 mTorr, the microloading effect is less likely to occur, and this reverse microloading effect is considered to occur.
[0036]
By appropriately selecting the etching conditions as described above, it is possible to increase the etching rate and deepen the trench to be formed in the narrower opening width region than in the wider opening width region. It is.
[0037]
In the present invention, in order to control the depth of the trench formed in this way, as shown in FIG. 1B, the relationship between the opening width and the etched depth was measured in advance. Considering the effect of variations in trench depth on the device, the etching rate changes (in the figure, the etching depth varies so that the variation in trench depth corresponding to the design variation in the opening width has little effect on the device. The range of the sufficiently small opening width (corresponding to a change) is determined in each of the region (y) and the region (z) in FIG. The size of the trench opening width of the mask pattern is determined based on the range of the opening width thus determined. And a device is designed based on this size. In the device designed in this way, the trench depth is shallow in the region where the trench opening width is wide, and the trench depth is set deep in the region where the trench opening width is narrow.
[0038]
The mechanism that causes the reverse microloading effect is considered as follows, but the present invention is not limited to this. In the case of trench etching and the case of mask etching, the gas species (etchant) used are different, and it is considered that the mechanism in which the reverse microloading effect occurs is also different.
[0039]
In the case of trench etching, it is considered to be caused by high energy ions incident at a shallow angle with respect to the sidewall of the trench. Reflected ions in which ions incident at a shallow angle are reflected on the trench sidewall and / or high-energy ions generated by sputtering the trench sidewall by the incident ions collide with the bottom of the trench, It is thought that the etching rate at that place is improved. Alternatively, it is considered that the etchant adsorbed on the side wall of the trench is sputtered by the incident ions as described above and supplied to the bottom of the trench, thereby improving the etching rate at that location. It is considered that the mechanism by which these etching rates increase is remarkably caused in a trench having a narrow opening width than in a trench having a wide opening width under the conditions of the present invention, and the reverse microloading effect occurs. Furthermore, when etching products from the mask or the like, or depositing radicals, are deposited in the trench and affect the etching rate, it is easy to deposit at the bottom of the trench having a wide opening width under the conditions of the present invention. Therefore, it is difficult to deposit at the bottom of a trench having a narrow opening width, and it is considered that a trench having a narrow opening width has a lower etching rate than a trench having a wide opening width. In practice, these mechanisms are combined to produce a reverse microloading effect.
[0040]
In the case of mask etching, the etching rate usually increases as the amount of etchant (radical) increases, but if the amount of radicals is too large, excessive radicals accumulate at the bottom of the trench and the etching rate decreases. . In a mask having a narrow opening width, radicals adhere to the side wall portion of the mask and do not easily reach the bottom portion. Therefore, under conditions such as those of the present invention, radicals are excessively deposited in a mask having a wide opening width and the etching rate at the bottom is reduced, but such a mask is not excessively deposited in a mask having a narrow opening width. Therefore, it is considered that the etching rate is higher than that of the trench having a wide opening width.
[0041]
Hereinafter, embodiments of the present invention will be described in detail.
[0042]
First, a mask layer is formed on the entire surface of the semiconductor substrate. As the semiconductor substrate material, any appropriate material can be used, and examples thereof include compound semiconductors such as silicon and GaAs. Examples of the mask layer include a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, a photoresist, a multilayer resist, and the like.
[0043]
This mask layer is etched by, for example, photolithography to form regions with different opening widths set as described above.
[0044]
Using this mask layer as a mask, the semiconductor substrate is etched to form trenches having different depths on the substrate surface. Here, the etching is performed under the condition that the difference in the etching depth is used between the different opening widths used when the opening width is previously determined. This step is preferably performed under relatively low pressure conditions. Specifically, it is preferably about 1 mTorr or more and about 90 mTorr or less, more preferably about 1 mTorr or more and about 10 mTorr or less. Under such pressure conditions, the effect of causing a difference in etching depth is significant. The absolute value of the etching depth shown in FIG. 1B is not limited to this example. Further, the conditions such as the etching gas type, the flow rate, and the RF power can take any appropriate conditions. It is only necessary to appropriately select a condition that provides a depth necessary for each device as necessary.
[0045]
Thereby, a deeper trench can be formed in a region with a narrower opening width and a shallower trench can be formed in a region with a wider opening width with good control. Thus, since the relationship between the opening width and the trench depth is defined, the subsequent trench filling can be easily performed.
[0046]
In another embodiment of the present invention, when the mask layer is etched, the mask layer is not etched until it reaches the semiconductor substrate, and a part of the mask layer is left on the semiconductor substrate in the opening region, thereby reducing the opening width. The layer thickness in which the mask layer remains may be changed between the wider region and the narrower opening width region. In this method, the remaining film of the mask is changed by performing etching under the etching conditions in which the etching depth varies depending on the opening width of the mask, that is, under the condition where the microloading effect occurs or under the condition where the reverse microloading effect occurs. Can be implemented. This step may be performed, for example, by plasma etching that generates a microloading effect.
[0047]
After the mask layer is etched, etching for forming a trench is performed. In an etching process for forming the trench (hereinafter referred to as a trench etching process), it is not always necessary to select an etching condition that causes the reverse microloading effect. In this trench etching process, the remaining portion of the mask layer is first etched, and then the semiconductor substrate is etched. That is, the etching of the semiconductor substrate is not performed until the etching of the remaining portion of the mask layer is completed. As a result, the time for starting the etching of the semiconductor substrate differs between the wide opening area and the narrow opening area, and thus the depth of the formed trench differs. The depth of the trench thus formed is determined by the residual layer thickness of the mask layer and the ratio of the etching rate between the mask layer and the semiconductor substrate in the trench etching process. Therefore, by changing the etching conditions in the trench etching process, the ratio of the etching rates can be changed to control the depth of the formed trench.
[0048]
In another embodiment of the present invention, the mask layer includes an antioxidant film made of a silicon nitride film or the like, and the semiconductor substrate is oxidized between the step of etching the mask layer and the trench etching step. A process may be further included.
[0049]
The mask layer is etched under conditions that cause a difference in etching rate depending on the opening width of the trench. For example, this can be achieved by plasma etching that generates a microloading effect. Thereby, the antioxidant film layer is preferably left in a region having a narrower opening width, preferably about 5 nm or more, and the antioxidant layer is completely removed in a region having a wider opening width. Thereafter, the semiconductor substrate is selectively oxidized. Next, trench etching is performed using the mask layer.
[0050]
As a result, a trench having a small opening width can be deepened and a trench having a wide opening width can be shallowed, and a trench that can be easily embedded can be formed.
[0051]
【Example】
( Reference example 1)
Book Reference example Forming a silicon oxide film layer on a semiconductor substrate, using this silicon oxide film layer as an etching mask, forming trenches with different depths by etching, and then filling the trenches to form trench element isolation portions Is a manufacturing example of a semiconductor device. More books Reference example These are examples of manufacturing a semiconductor device in which the reverse microloading effect is applied during trench etching.
[0052]
Hereinafter, the book will be described with reference to FIGS. Reference example Will be explained.
[0053]
Referring to FIG. 3A, a semiconductor substrate 31 made of silicon is thermally oxidized to form a silicon oxide film 32 having a thickness of about 0.2 μm. This silicon oxide film 32 is used as an etching mask when a trench is later formed by etching. A resist mask 33 was patterned on the silicon oxide film 32 by photolithography. Here, a chemically amplified resist was used as the resist, and exposure was performed with an excimer stepper. At this time, the opening width of the resist mask 33 in the narrow opening (left side in the figure), which is a portion for forming the deep trench, is in the range of about 0.2 to about 0.5 μm, for example, 0.3 μm, and the shallow trench. The opening width of the resist mask 33 at the wide opening (the right side in the figure), which is a portion for forming the film, is about 1 μm or more, for example, 1.5 μm.
[0054]
Next, as shown in FIG. 3B, the silicon oxide film 32 was etched using the resist mask 33. Here, a magnetron RIE apparatus was used as the etching apparatus. The mask etching conditions at this time are shown below.
[0055]
CHF _Three = About 60 sccm
CF _Four = About 30 sccm
Ar = about 10 sccm
Gas pressure = about 50mTorr
RF power = about 700W (about 13.56MHz)
In this etching step, overetching was performed about 50%. As a result, the silicon oxide film 32 was completely removed by etching both at the opening width of about 0.2 to about 0.5 μm and at the opening width of about 1.0 μm or more.
[0056]
Next, after ashing and washing to remove the resist mask 33, as shown in FIG. 3C, the silicon oxide film 32 is used as an etching mask to form trenches 34 and 35. The etching (trench etching) conditions for forming the trenches 34 and 35 at this time are shown below.
[0057]
Cl ₂ = About 40 sccm
O ₂ = Approx. 6 sccm
Gas pressure = about 3m
Torr microwave power = about 220W
RF bias power = about 90W (about 2MHz)
When the above conditions are used, the trench opening width (this Reference example 4 shows that the relationship between the opening width of the silicon oxide film 32) and the etching depth is as shown in FIG. From FIG. 4, when the trench opening width is in the range of about 0.2 to about 0.5 μm, the etching rate is fast, and when the trench opening width is about 1 μm or more, the etching rate is slow. In addition, when the trench opening width is in the range of about 0.2 to about 0.5 μm, the etching depth is substantially constant with respect to the change in the opening width, and is relatively stable. On the other hand, when the opening width is in the range of about 0.6 to about 0.9 μm, the etching depth changes rapidly with respect to the change in the opening width. Further, in the range where the opening width is about 1.0 μm or more, the etching depth is substantially constant with respect to the change in the opening width, and is relatively stable. When designing the opening width in advance, it is necessary to determine the dimension of the opening width so that the variation in the etching depth due to the variation in the opening width does not increase.
[0058]
So book Reference example Then, as described above, the opening width of the trench was set to about 0.2 to about 0.5 μm and about 1 μm or more. As a result, when the mask opening width is about 0.2 to about 0.5 μm as shown in FIG. 3C, a trench 34 having a depth of about 1.05 μm is formed, and the mask opening width is about 1 μm. In the above case, the trench 35 having a depth of about 0.8 μm was formed.
[0059]
Next, after cleaning the substrate, a dielectric material made of silicon oxide is deposited on the entire surface of the substrate by CVD as shown in FIG. 3 (d), and the trenches 34 and 35 are stepped by the silicon oxide film 36. Embedded with good coverage. In this trench embedding step, the trench portion having the wide opening portion has a shallow trench depth, and therefore, the trench portion can be easily embedded even in the trench portion having the wide opening portion.
[0060]
Next, as shown in FIG. 3E, the silicon oxide films 36 and 32 were etched until the silicon substrate was exposed by an etch back method.
[0061]
As described above, a trench element isolation portion in which the trenches 34 and 35 were embedded was obtained. Furthermore, the trench element isolation part could be formed without causing a depression on the silicon substrate.
[0062]
Book Reference example In this embodiment, the SiO2 layer is used as an etching mask for trench etching, but an SiNx layer, a SiOxNy layer, or an inorganic mask such as various metal films may be used. Alternatively, a resist mask, a multilayer resist mask, or the like may be used.
[0063]
( Example )
This embodiment is an example of manufacturing a semiconductor device in which a silicon oxide film layer is formed on a semiconductor substrate, and trenches having different depths are formed by etching using the silicon oxide film layer as an etching mask. Furthermore, this embodiment is an example of manufacturing a semiconductor device in which the reverse microloading effect is applied when processing a silicon oxide film layer.
[0064]
Hereinafter, the present embodiment will be described with reference to FIGS.
[0065]
Referring to FIG. 5A, the semiconductor substrate 51 made of silicon was thermally oxidized to form a silicon oxide film having a thickness of about 0.35 μm. On this silicon oxide film 52 Reference example 1 Similarly to the above, the resist mask 53 was patterned by photolithography. At this time, the opening width of the resist mask 53 in the narrow opening (left side in the figure), which is a portion for forming the deep trench, is in the range of about 0.2 to about 0.5 μm, for example, 0.24 μm, and the shallow trench. The opening width of the resist mask 53 in the wide opening (the right side in the figure), which is a portion for forming the film, is about 1 μm or more, for example, 1.8 μm.
[0066]
Next, as shown in FIG. 5B, the silicon oxide film 52 was etched using the resist mask 53. Here, an ICP plasma type apparatus was used as the etching apparatus. The mask etching conditions at this time are shown below.
[0067]
C ₂ F ₆ = About 30 sccm
Gas pressure = about 3mTorr
RF power = about 700W
Upper electrode power = about 2500W
In this etching process, overetching was not performed, and the silicon oxide film 52 was completely etched in a narrow opening of about 0.2 to about 0.5 μm, and the etching was finished when the semiconductor substrate 51 was exposed.
[0068]
When the above conditions are used, the relationship between the trench opening width (the opening width of the resist mask 53 in this embodiment) and the etching depth is as shown in FIG. Yes. From FIG. 6, the etching rate is fast when the trench opening width is in the range of about 0.2 to about 0.5 μm, and the rate is slow when the trench opening width is about 1 μm or more.
[0069]
Accordingly, as shown in FIG. 5B, when the silicon oxide film 53 is completely etched in the narrow opening and the semiconductor substrate 51 is exposed, the etching is finished, and about 0.05 μm of silicon is formed in the wide opening. The remaining oxide film was left.
[0070]
Next, after ashing and cleaning were performed to remove the resist mask 53, referring to FIG. 5C, etching was performed using the silicon oxide film 52 as an etching mask to form trenches 54 and 55. Here, an ECR plasma apparatus was used as the etching apparatus. The trench etching conditions for forming the trenches 54 and 55 at this time are shown below.
[0071]
Cl ₂ = About 40 sccm
O ₂ = About 2 sccm
Gas pressure = about 20 mTorr
Microwave power = about 220W
RF bias power = about 90W (about 13.56MHz)
Under this condition, since the selection ratio of silicon substrate 51 / silicon oxide film 52 for trench etching is set to 20, not only silicon but also silicon oxide film 52 as a mask is etched in advance in the trench etching process. know.
[0072]
Therefore, when the silicon substrate 51 is etched by about 1 μm in a narrow opening of about 0.2 to about 0.5 μm, the silicon oxide film 52 is about the etching depth of the silicon substrate 51 in a wide opening of about 1 μm or more. Etched 20 times, or about 0.05 μm. As a result, the silicon oxide film 52 was completely removed even in the wide opening, and the silicon substrate 51 was exposed.
[0073]
After the silicon substrate 51 was exposed through a wide opening of about 1 μm or more, further etching was continued, and etching was performed at a silicon etching depth of about 0.5 μm. At this time, the silicon oxide film 52 is also etched in the region where the trench is not formed. However, as described above, the etching rate of the silicon oxide film is very slow, and the silicon oxide film 52 is sufficiently large so that the semiconductor substrate 51 is not exposed in this region. Therefore, the semiconductor substrate 51 was not exposed.
[0074]
As a result, as shown in FIG. 5C, a trench 54 having a depth of about 1.5 μm was formed in a narrow opening of about 0.2 to about 0.5 μm. On the other hand, a trench 55 having a depth of about 0.5 μm was formed in a wide opening of about 1 μm or more.
[0075]
Then Reference example 1 3D and 3E, trenches 54 and 55 were buried, and then the silicon oxide film was etched to expose the silicon substrate 51.
[0076]
As described above, a trench element isolation portion in which the trenches 54 and 55 are embedded is obtained. Also in this example, Reference example 1 It was possible to embed without dents as in the case. In this embodiment, the trench depth can be controlled by changing the etching selection ratio between the silicon substrate 51 and the silicon oxide film 52.
[0077]
( Reference example 2 )
Book Reference example Is a manufacturing example of a semiconductor device in which a silicon nitride layer is formed on a semiconductor substrate, and trenches having different depths are formed by etching using the silicon nitride layer as an etching mask. Here, the silicon nitride layer is used as a polishing stopper layer in a subsequent CMP (Chemical Mechanical Polishing) step. More books Reference example Is an example of manufacturing a semiconductor device in which the microloading effect is applied during the processing of the silicon nitride layer.
[0078]
Hereinafter, the book will be described with reference to FIGS. Reference example Will be explained.
[0079]
Referring to FIG. 7A, a silicon oxide film (not shown) is formed as a stress relaxation layer with a thickness of about 0.02 μm on a semiconductor substrate 71 made of silicon, and a silicon nitride layer 72 is formed thereon using a CVD apparatus. About 0.25 μm. next, Reference example 1 and Example Similarly to the above, the resist mask 73 was patterned by photolithography. At this time, the opening width of the resist mask 73 in the narrow opening (the left side in the figure), which is a portion forming the deep trench, is in the range of about 0.2 to about 0.5 μm, for example, 0.2 μm, and the shallow trench The opening width of the resist mask 73 in the wide opening (the right side in the figure), which is a portion for forming the film, is about 1 μm or more, for example, 2.0 μm.
[0080]
next, FIG. As shown in (b), the silicon nitride layer 72 was etched using the resist mask 73 under plasma etching conditions using a magnetron RIE apparatus. The mask etching conditions at this time are shown below.
[0081]
CHF _Three = About 46 sccm
O ₂ = About 4 sccm
Gas pressure = about 100 mTorr
RF power = about 1.0kW (about 13.56MHz)
When the above conditions are used, the trench opening width (this Reference example 8 shows that the relationship between the opening width of the resist mask 73) and the etching depth is as shown in FIG. From FIG. 8, when the trench opening width is in the range of about 0.2 to about 0.5 μm, the etching rate is low, and when the opening width of the mask is about 1 μm or more, the etching rate is high.
[0082]
Using this condition, the silicon nitride film layer 72 is etched, and as shown in FIG. 7B, the etching progresses using an etching end point detector (EPD) or the like to open a wide opening (right side in the figure). The etching was completed when the silicon nitride film layer 72 was etched and the silicon substrate 71 as the underlying layer was exposed. At this time, due to the microloading effect, in the narrow opening (left side in the figure), the silicon nitride film layer 72 was not etched and remained with a film thickness of about 10 nm or more.
[0083]
Next, ashing and cleaning were performed to remove the resist mask 73, and then the substrate was thermally oxidized using an oxidation furnace as shown in FIG. 7C.
[0084]
In this thermal oxidation process, the narrow opening was covered with the silicon nitride film layer 72, and the semiconductor substrate 71 was not exposed, so the thermal oxide film was not formed. On the other hand, since the wide opening is not covered with the silicon nitride film layer 72 and the semiconductor substrate 71 is exposed, a thermal oxide film 74 having a film thickness of about 0.1 μm is formed.
[0085]
FIG. 9 shows the relationship between the residual film thickness of the silicon nitride film under the oxidizing conditions as described above and the amount of the silicon substrate 71 oxidized under the silicon nitride film in the remaining part of the silicon nitride film. FIG. As can be seen from FIG. 9, when the residual film thickness of the silicon nitride film is about 5 nm or more, no silicon oxide film is formed. This is because if the silicon nitride film has a certain thickness, the oxidized species cannot diffuse into the silicon nitride layer and reach the silicon substrate.
[0086]
Thereafter, referring to FIG. 7D, trench etching was performed using this silicon nitride layer 72 as a mask. This trench etching will be described in detail below.
[0087]
First, the remaining film of the silicon nitride film layer 72 remaining in the narrow opening was etched. At this time, in the wide opening, the silicon oxide film 74 was simultaneously etched by about 10 nm. Here, since the silicon oxide film 74 originally had a thickness of about 0.1 μm, about 90 nm of the thermal oxide film 74 remained without being etched.
[0088]
next, Example Etching was performed under the same trench etching conditions. The substrate 71 was etched in the narrow opening. On the other hand, since the silicon oxide film 74 exists in the wide opening, the substrate 71 was not etched until the etching of the silicon oxide film 74 was completed. While the thermal oxide film 74 is etched by about 90 nm in the wide opening and all of it is removed, the selectivity ratio of the silicon substrate 71 / silicon oxide film 74 for trench etching is set to 20, so in the narrow opening The silicon substrate 71 was etched by about 1.8 μm. After all the silicon oxide film 74 was removed at the wide opening, the silicon substrate 71 was further etched by about 0.3 μm.
[0089]
As a result, as shown in FIG. 7D, a trench 76 having a depth of about 0.3 μm was formed in a wide opening, and a trench 75 having a depth of about 2.1 μm was manufactured in a narrow opening.
[0090]
Then Reference example 1 and Example Similarly, trenches 75 and 76 were filled with silicon oxide using a CVD apparatus. Next, as shown in FIG. 7E, the substrate was planarized by polishing with a CMP apparatus, and then the silicon nitride film layer 72 was removed. As described above, a trench element isolation portion in which the trenches 75 and 76 are embedded is formed.
[0091]
Book Reference example Then, in the etching of the first silicon nitride film layer 72, the silicon nitride film layer 72 in the narrow opening may be larger than the thickness that can suppress the thermal oxidation of the subsequent silicon substrate. It is not necessary to strictly control the thickness of the remaining silicon nitride film layer 72. The depths of the two different trenches can be set only by the amount of oxidation of the silicon substrate 71 occurring in the wide opening and the trench etching conditions (silicon substrate / silicon oxide film selection ratio). That is, the degree of the microloading effect does not remarkably affect the trench depth, and the microloading effect occurs so that the remaining film of the silicon nitride film layer 72 remains in the narrow opening to some extent. Therefore, the trench depth can be formed with good control.
[0092]
Book Reference example The silicon nitride film layer 72 is used as an etching mask layer having a different opening width and a CMP stopper layer.
[0093]
This etching mask layer does not need to be a single layer. For example, if a selection ratio is required during trench etching, the etching ratio is higher for a silicon oxide film than for a silicon nitride film under trench etching conditions. It is also possible to make a multilayer by depositing an oxide film on the silicon nitride layer by CVD. In this case, the oxide film deposited by this CVD hardly affects the film thickness of the oxide film of the silicon substrate 71 in the thermal oxidation process.
[0094]
Book Reference example In the mask etching process of the first silicon nitride film layer 72, the microloading effect is used, but the reverse microloading effect can be used instead. In this case, a deep trench is formed with a wide opening, and a shallow trench is formed with a narrow opening.
[0095]
As above Example and Reference examples 1 and 2 In this case, a silicon substrate is used as the semiconductor substrate material, but a compound semiconductor substrate such as GaAs may be used.
[0096]
Furthermore, in addition to a magnetron RIE apparatus and a substrate bias application type ECR plasma etching apparatus as an etching apparatus, an arbitrary etching apparatus such as a general parallel plate RIE apparatus, an inductively coupled plasma etching apparatus, and a helicon wave plasma etching apparatus may be used. It may be used. Here, depending on the characteristics of each etching apparatus, the gas pressure and aspect ratio at which the microloading effect or reverse microloading effect occurs vary depending on the apparatus factor, so it is possible to set the etching conditions by creating a graph or the like in advance. desirable.
[0097]
Furthermore, although the description has been made using the oxide film for filling the trench, it is also possible to use a method of filling the trench wall surface with polysilicon after the trench wall surface is oxidized. In this case, since the polysilicon film has better embedding characteristics than the oxide film, it is suitable for using the method of the present invention.
[0098]
【The invention's effect】
As described above, according to the semiconductor device manufacturing method of the present invention, trenches having different depths can be simultaneously formed by one etching. Therefore, trenches having different depths, that is, trench element isolation portions can be easily formed.
[0099]
Further, this eliminates the need for alignment between trenches when the trench element isolation portion is formed by a plurality of etching processes. Therefore, it is not necessary to design the semiconductor device in consideration of the alignment margin, the semiconductor cell can be reduced, and the cost can be reduced.
[0100]
Furthermore, a photolithography process for forming a mask necessary for etching can be reduced. Therefore, the semiconductor device can be manufactured with high throughput.
[0101]
Furthermore, the manufacturing method of the present invention can be applied to manufacturing a plurality of trench capacitors having different capacitances.
[0102]
Further, in the manufacturing method of the present invention, since the trench having a narrow opening width can be formed deep and the trench having a wide opening width can be formed shallowly, the trench can be easily embedded, and the trench portion having a wide opening width can be formed. It is possible to make it difficult for the concave step to occur, and to prevent the occurrence of kinks in the transistor current-voltage characteristics.
[Brief description of the drawings]
FIGS. 1A and 1B are diagrams illustrating a relationship between a trench opening width and an etching depth, in which FIG. 1A is a diagram illustrating a conventional manufacturing method, and FIG. 1B is a diagram illustrating a manufacturing method according to the present invention;
FIGS. 2A and 2B are schematic cross-sectional views showing the relationship between the trench opening width and the trench depth to be formed. FIG. 2A is a schematic cross-sectional view of the conventional manufacturing method, and FIG.
FIG. 3 of the present invention Reference example 1 It is a cross-sectional schematic diagram explaining a manufacturing process.
[Fig. 4] Reference example 1 It is a figure showing the relationship between the trench opening width and etching depth used when setting the opening width of.
FIG. 5 shows the present invention. Example It is a cross-sectional schematic diagram explaining a manufacturing process.
FIG. 6 is a diagram illustrating the relationship between the trench opening width and the etching depth used when setting the opening width of the example.
[Fig. 7] of the present invention. Reference example 2 It is a cross-sectional schematic diagram explaining a manufacturing process.
[Fig. 8] Reference example 2 It is a figure showing the relationship between the trench opening width and etching depth used when setting the opening width of.
FIG. 9 Reference example 2 It is a figure which shows the relationship between the residual film thickness of the silicon nitride film on this oxidation condition, and the quantity of the silicon substrate oxidized under the silicon nitride film in the part which a silicon nitride film remains.
FIG. 10 is a schematic cross-sectional view of a trench element isolation portion manufactured by a conventional manufacturing method.

Claims (2)

Depositing a mask layer on the oxide film of the semiconductor substrate on which the oxide film is formed;
The mask layer includes a first opening and a second opening that respectively reach the oxide film, the opening width of the second opening is wider than the opening width of the first opening, and the oxide film Forming under conditions that cause a reverse microloading effect by plasma etching,
Next, by plasma etching the oxide film using the mask layer as a mask, the oxide film corresponds to the first opening and the third opening reaching the semiconductor substrate, and the second opening. Forming a fourth opening that does not reach the semiconductor substrate,
Next, using the oxide film as a mask, the oxide film and the semiconductor substrate are etched under the condition that the etching rate of the semiconductor substrate is higher than the etching rate of the oxide film, so that the third opening and the second substrate are etched. Forming a trench deeper in the region corresponding to the third opening than in the region corresponding to the fourth opening in the region of the semiconductor substrate corresponding to each of the four openings;
A method for manufacturing a semiconductor device, comprising: Subsequent to forming the trench, depositing a dielectric material on the semiconductor substrate and filling the trench with the dielectric material;
The method for manufacturing a semiconductor device according to claim 1 , further comprising a step of removing the dielectric material so that a surface of the semiconductor substrate is exposed.

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