KR100400324B1 - Method for manufacturing a semiconductor device - Google Patents
Method for manufacturing a semiconductor device Download PDFInfo
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- KR100400324B1 KR100400324B1 KR10-2001-0084894A KR20010084894A KR100400324B1 KR 100400324 B1 KR100400324 B1 KR 100400324B1 KR 20010084894 A KR20010084894 A KR 20010084894A KR 100400324 B1 KR100400324 B1 KR 100400324B1
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- Prior art keywords
- insulating film
- interlayer insulating
- entire surface
- forming
- mechanical polishing
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 18
- 125000006850 spacer group Chemical group 0.000 claims abstract description 15
- 239000000126 substance Substances 0.000 claims abstract description 13
- 238000005498 polishing Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 8
- 238000007517 polishing process Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims description 3
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 239000002002 slurry Substances 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 62
- 239000010409 thin film Substances 0.000 description 2
- 230000002378 acidificating effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 층간절연막을 평탄화시키기 위한 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정을 실시하고, 콘택 마스크를 식각마스크로 상기 층간절연막을 식각하여 콘택홀을 형성한 다음, 전체표면 상부에 소정 두께의 버퍼절연막을 증착한 후 전면식각하여 콘택홀 측벽에 절연막 스페이서를 형성하여 상기 CMP공정 발생한 스크래치영역에 의해 형성된 터널(tunnel)을 차단함으로써 콘택 플러그 간에 브리지(bridge)가 발생하는 것을 방지하여 소자의 공정 수율 및 신뢰성을 향상시키는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a semiconductor device, comprising performing a chemical mechanical polishing (CMP) process to planarize an interlayer insulating film, and etching the interlayer insulating film with an etch mask as a contact mask. And then deposit a buffer insulating film of a predetermined thickness over the entire surface, and then etch the entire surface to form insulating film spacers on the sidewalls of the contact holes, thereby blocking tunnels formed by the scratch regions generated in the CMP process. This technology improves process yield and reliability of devices by preventing bridges from occurring.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게 층간절연막을 평탄화시키기 위한 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정에 의한 스크래치영역을 절연막 스페이서를 이용하여 차단함으로써 콘택 플러그 간에 브리지가 발생하는 것을 방지하는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to close contact between contact plugs by blocking a scratch region by a chemical mechanical polishing (CMP) process to planarize an interlayer insulating film using an insulating film spacer. The present invention relates to a method for manufacturing a semiconductor device that prevents bridges from occurring.
반도체소자가 고집적화됨에 따라 소자의 형성공정 중 단차의 발생이 증가하면서, 사진공정이 더욱 더 어렵게 되었다. 그런 이유로 평탄화 공정의 중요성은 날로 증가되고 있다.As semiconductor devices are highly integrated, the generation of steps increases during the process of forming the devices, and the photo process becomes more difficult. That is why the importance of the planarization process is increasing day by day.
최근 각광 받고 있는 CMP공정은 이에 적합한 공정이라 할 수 있으나, 직접 웨이퍼의 표면을 물리적인 마찰에 의해 연마하기 때문에 파티클(particle)이 많이 발생하고, 미세한 패턴을 보호하는 데에 문제점이 발생하였다. 특히, 경도가 낮은 박막을 CMP공정으로 평탄화시키는 경우 스크래치영역이 발생하여 소자의 신뢰성을 저하시키는 문제점이 있다.The CMP process, which has recently been in the spotlight, may be referred to as a suitable process. However, since the surface of the wafer is directly polished by physical friction, a lot of particles are generated and a problem occurs in protecting a fine pattern. In particular, when the thin film having a low hardness is planarized by the CMP process, a scratch region is generated, thereby lowering the reliability of the device.
이하, 첨부된 도면을 참고로 하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.
도 1a 내지 도 1e 는 종래기술에 따른 반도체소자의 제조방법을 도시한 공정 단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
먼저, 반도체기판(11) 상부에 워드라인 또는 비트라인 등의 도전배선(13)을 형성한다. 이때, 상기 도전배선(13)의 상부에는 마스크절연막패턴(15)이 적층되어 있고, 상기 도전배선(13)과 마스크절연막패턴(15)의 측벽에는 도전배선(13) 간의절연을 위한 절연막 스페이서(17)가 구비되어 있다.First, a conductive wiring 13 such as a word line or a bit line is formed on the semiconductor substrate 11. In this case, a mask insulating film pattern 15 is stacked on the conductive wiring 13, and an insulating film spacer for insulating between the conductive wiring 13 is formed on sidewalls of the conductive wiring 13 and the mask insulating film pattern 15. 17).
다음, 전체표면 상부에 층간절연막(19)을 형성한다. 이때, 상기 층간절연막(19)은 매립 특성이 우수한 BPSG(boro phospho silicate glass)막으로 형성되고, 도전배선(13) 두께의 2 ∼ 3배의 두께로 형성된다. (도 1a 참조)Next, an interlayer insulating film 19 is formed over the entire surface. In this case, the interlayer insulating film 19 is formed of a borophospho silicate glass (BPSG) film having excellent embedding characteristics, and is formed to have a thickness of 2 to 3 times the thickness of the conductive wiring 13. (See Figure 1A)
그 다음, 상기 층간절연막(19)을 평탄화시키는 CMP공정을 실시한다. 이때, 상기 CMP공정에 의해 상기 층간절연막(19)의 표면으로부터 2000Å 깊이에 스크래치영역(21)이 형성된다. (도 1b 참조)Next, a CMP process is performed to planarize the interlayer insulating film 19. At this time, the scratch region 21 is formed at a depth of 2000 microseconds from the surface of the interlayer insulating film 19 by the CMP process. (See FIG. 1B)
다음, 콘택마스크를 식각마스크로 이용하여 상기 층간절연막(19)을 식각하여 콘택홀(23)을 형성한다. 이때, 상기 층간절연막(19)의 스크래치영역(21)은 상기 콘택홀(23) 간을 연결하는 터널(22)로 형성된다. (도 1c 참조)Next, the interlayer insulating layer 19 is etched using a contact mask as an etch mask to form a contact hole 23. In this case, the scratch region 21 of the interlayer insulating layer 19 is formed as a tunnel 22 connecting the contact holes 23. (See Figure 1C)
그 다음, 전체표면 상부에 다결정실리콘층(25)을 형성한다. 이때, 상기 다결정실리콘층(25)은 상기 스크래치에 의한 터널(22)에도 매립된다. (도 1d 참조)Then, the polysilicon layer 25 is formed on the entire surface. At this time, the polysilicon layer 25 is also embedded in the tunnel 22 by the scratch. (See FIG. 1D)
다음, 상기 다결정실리콘층(25)을 식각하여 콘택 플러그(27)를 형성한다. 이때, 상기 터널(22)에 의해 상기 콘택 플러그(27) 간에 브리지가 발생한다. (도 1e 참조)Next, the polysilicon layer 25 is etched to form a contact plug 27. At this time, a bridge is generated between the contact plugs 27 by the tunnel 22. (See Figure 1E)
도 2 는 종래기술에 따른 반도체소자의 제조방법으로 콘택 플러그를 형성한 후 층간절연막이 제거된 사진으로서, CMP공정으로 발생된 스크래치에 의한 터널을 통해 도전층이 매립되어 콘택 플러그 간에 브리지가 발생한 것을 나타낸다.FIG. 2 is a view illustrating a method of manufacturing a semiconductor device according to the related art, in which a contact plug is formed and an interlayer insulating film is removed, and a bridge is formed between the contact plugs by filling a conductive layer through a tunnel caused by a scratch generated by a CMP process. Indicates.
상기와 같은 종래기술에 따른 반도체소자의 제조방법은 층간절연막으로 사용되는 BPSG막은 경도가 낮기 때문에 CMP공정으로 평탄화시키는 경우 스크래치영역을발생시키고, 상기 스크래치영역은 터널형태로 형성되어 콘택 플러그 간에 브리지를 발생시킨다. 그리고, 상기 BPSG막보다 경도가 높은 박막을 층간절연막으로 사용하는 경우에는 매립 특성이 저하되어 콘택 플러그 간에 브리지를 발생시켜 소자의 공정 수율 및 신뢰성을 저하시키는 문제점이 있다.In the method of manufacturing a semiconductor device according to the prior art as described above, since the BPSG film used as the interlayer insulating film has a low hardness, a scratch region is generated when planarized by the CMP process, and the scratch region is formed in a tunnel shape to form a bridge between contact plugs. Generate. In addition, when a thin film having a hardness higher than that of the BPSG film is used as an interlayer insulating film, embedding properties are deteriorated, thereby generating bridges between contact plugs, thereby lowering process yield and reliability of the device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 층간절연막을 평탄화시키는 CMP공정을 실시하고, 콘택마스크를 식각마스크로 이용하여 상기 층간절연막을 식각하여 콘택홀을 형성한 다음, 전체표면 상부에 버퍼절연막을 형성하고 상기 버퍼절연막을 전면식각공정을 제거하여 상기 콘택홀 측벽에 절연막 스페이서를 형성함으로써 상기 CMP공정으로 발생된 스크래치영역에 의해 형성된 터널을 차단시켜 콘택 플러그 간에 브리지가 발생하는 것을 방지하고 그에 따른 반도체소자의 공정 수율 및 신뢰성을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the present invention performs a CMP process to planarize the interlayer insulating film, and forms a contact hole by etching the interlayer insulating film using a contact mask as an etch mask, and then over the entire surface. By forming a buffer insulating film and removing the entire surface etching process of the buffer insulating film to form an insulating film spacer on the sidewall of the contact hole, the tunnel formed by the scratch region generated by the CMP process is blocked to prevent the bridge from being generated between the contact plugs. Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device, which improves process yield and reliability of the semiconductor device.
도 1a 내지 도 1e 는 종래기술에 따른 반도체소자의 제조방법을 도시한 공정 단면도.1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2 는 종래기술에 따른 반도체소자의 제조방법으로 콘택 플러그를 형성한 후 층간절연막이 제거된 사진.2 is a photo of the interlayer insulating film removed after the contact plug is formed by a method of manufacturing a semiconductor device according to the prior art.
도 3a 내지 도 3g 는 본 발명에 따른 반도체소자의 제조방법을 도시한 공정 단면도.3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
< 도면의 주요부분에 대한 부호 설명 ><Explanation of Signs of Major Parts of Drawings>
11, 31 : 반도체기판 13, 33 : 도전배선11, 31: semiconductor substrate 13, 33: conductive wiring
15, 35 : 마스크절연막패턴 17 : 절연막 스페이서15, 35: mask insulating film pattern 17: insulating film spacer
19, 39 : 층간절연막 21, 41 : 스크래치영역19, 39: interlayer insulating film 21, 41: scratch area
22, 42 : 터널 23, 43 : 콘택홀22, 42: tunnel 23, 43: contact hole
25, 47 : 다결정실리콘층 27, 49 : 콘택 플러그25, 47: polysilicon layer 27, 49: contact plug
37 : 제1절연막 스페이서 45 : 버퍼절연막37: first insulating film spacer 45: buffer insulating film
46 : 제2절연막 스페이서46: second insulating film spacer
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,
층간절연막을 평탄화시키는 화학적 기계적 연마공정으로 발생된 스크래치영역을 제거하는 반도체소자의 제조방법에 있어서,In the method of manufacturing a semiconductor device to remove the scratch region generated by a chemical mechanical polishing process to planarize the interlayer insulating film,
반도체기판 상부에 마스크절연막패턴이 적층된 도전배선을 형성하는 공정과,Forming a conductive wiring in which a mask insulating film pattern is stacked on the semiconductor substrate;
전체표면 상부에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film over the entire surface;
상기 층간절연막을 평탄화시키는 화학적 기계적 연마공정을 실시하는공정과,Performing a chemical mechanical polishing step of planarizing the interlayer insulating film;
콘택마스크를 식각마스크로 이용하여 상기 층간절연막을 식각하여 콘택홀을 형성하는 공정과,Forming a contact hole by etching the interlayer insulating layer using a contact mask as an etching mask;
전체표면 상부에 버퍼절연막을 소정 두께 형성하는 공정과,Forming a predetermined thickness over the entire surface of the buffer insulating film;
상기 버퍼절연막을 전면식각공정을 제거하여 상기 콘택홀의 측벽에 절연막 스페이서를 형성하여 상기 화학적 기계적 연마공정 시 상기 층간절연막에 발생된 스크래치영역에 의해 형성된 터널을 차단하는 공정과,Removing an entire surface etching process of the buffer insulating film to form an insulating film spacer on the sidewall of the contact hole to block a tunnel formed by the scratch region generated in the interlayer insulating film during the chemical mechanical polishing process;
전체표면 상부에 다결정실리콘층을 형성하는 공정과,Forming a polysilicon layer on the entire surface,
상기 다결정실리콘층을 식각하여 콘택플러그를 형성하는 공정과,Etching the polysilicon layer to form a contact plug;
상기 층간절연막은 BPSG막인 것과,The interlayer insulating film is a BPSG film,
상기 버퍼절연막은 산화막, 질화막 또는 산화질화막으로 형성되는 것과,The buffer insulating film is formed of an oxide film, a nitride film or an oxynitride film,
상기 다결정실리콘층은 전면식각공정 또는 화학적 기계적 연마공정으로 제거하는 것과,The polysilicon layer is removed by a front etching process or a chemical mechanical polishing process,
상기 다결정실리콘층은 실리카(silica), 세리아(ceria) 또는 알루미나(alumina)를 연마제로 함유하는 pH1 ∼ 5의 산성슬러리를 사용하는 화학적 기계적 연마공정으로 제거하는 것을 특징으로 한다.The polysilicon layer is removed by a chemical mechanical polishing process using an acid slurry of pH 1-5 containing silica, ceria or alumina as an abrasive.
본 발명의 원리는 경도가 낮은 BPSG막을 평탄화시키기 위한 CMP공정 시 발생된 스크래치영역에 의해 형성된 터널을 절연막 스페이서로 차단시켜 콘택홀 간에 브리지가 발생하는 것을 방지하는 것이다.The principle of the present invention is to prevent the bridge between contact holes by blocking the tunnel formed by the scratch region generated during the CMP process to planarize the BPSG film having a low hardness with the insulating film spacer.
이하, 첨부된 도면을 참고로 하여 본 발명에 따른 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail according to the present invention.
도 3a 내지 도 3g 는 본 발명에 따른 반도체소자의 제조방법을 도시한 공정 단면도이다.3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
먼저, 반도체기판(31) 상부에 워드라인 또는 비트라인 등의 도전배선(33)을 형성한다. 이때, 상기 도전배선(33)의 상부에는 마스크절연막패턴(35)이 적층되어 있고, 상기 도전배선(33)과 마스크절연막패턴(35)의 측벽에는 도전배선(33) 간의 절연을 위한 제1절연막 스페이서(37)가 구비되어 있다.First, a conductive wiring 33 such as a word line or a bit line is formed on the semiconductor substrate 31. In this case, a mask insulating film pattern 35 is stacked on the conductive wiring 33, and a first insulating film for insulating between the conductive wiring 33 is formed on sidewalls of the conductive wiring 33 and the mask insulating film pattern 35. The spacer 37 is provided.
여기서, 상기 마스크절연막패턴(35)과 제1절연막 스페이서(37)는 질화막으로 형성된 것이다.Here, the mask insulating film pattern 35 and the first insulating film spacer 37 are formed of a nitride film.
다음, 전체표면 상부에 층간절연막(39)을 형성한다. 이때, 상기 층간절연막(39)은 매립 특성이 우수한 BPSG막으로 형성되고, 상기 도전배선(33) 두께의 2 ∼ 3배 두껍게 형성한다. (도 3a 참조)Next, an interlayer insulating film 39 is formed over the entire surface. At this time, the interlayer insulating film 39 is formed of a BPSG film having excellent embedding characteristics, and is formed two to three times thicker than the thickness of the conductive wiring 33. (See Figure 3A)
그 다음, 상기 층간절연막(39)을 CMP공정으로 소정 두께 제거하여 평탄화시킨다. 이때, 상기 CMP공정 후 상기 평탄화된 층간절연막(39)에 표면으로부터 2000Å 정도의 깊이에 스크래치영역(41)이 형성된다. (도 3b 참조)Then, the interlayer insulating film 39 is removed by a CMP process to have a predetermined thickness to be flattened. At this time, a scratch region 41 is formed in the planarized interlayer insulating film 39 at a depth of about 2000 으로부터 from the surface after the CMP process. (See Figure 3b)
다음, 콘택마스크를 식각마스크로 상기 층간절연막(39)을 식각하여 콘택홀(43)을 형성한다. 이때, 상기 층간절연막(39)의 스크래치영역(41)은 상기 콘택홀(43) 간을 연결하는 터널(42)로 형성된다. (도 3c 참조)Next, the interlayer insulating layer 39 is etched using a contact mask as an etch mask to form a contact hole 43. In this case, the scratch region 41 of the interlayer insulating layer 39 is formed as a tunnel 42 connecting the contact holes 43. (See Figure 3c)
그 다음, 전체표면 상부에 버퍼절연막(45)을 소정 두께 증착한다. 이때, 상기 버퍼절연막(45)은 산화막, 질화막 또는 산화질화막(SiON)으로 형성된다. (도 3d참조)Then, a buffer insulating film 45 is deposited on the entire surface by a predetermined thickness. In this case, the buffer insulating layer 45 is formed of an oxide film, a nitride film, or an oxynitride film (SiON). (See FIG. 3D)
다음, 상기 버퍼절연막(45)을 전면식각공정으로 제거하여 상기 콘택홀(43)의 측벽에 제2절연막 스페이서(46)를 형성한다. 이때, 상기 제2절연막 스페이서(46)에 의해 상기 터널(42)이 차단된다. (도 3e 참조)Next, the buffer insulating layer 45 is removed by the entire surface etching process to form a second insulating layer spacer 46 on the sidewall of the contact hole 43. In this case, the tunnel 42 is blocked by the second insulating layer spacer 46. (See Figure 3E)
그 다음, 전체표면 상부에 다결정실리콘층(47)을 형성한다. (도 3f 참조)Next, a polysilicon layer 47 is formed over the entire surface. (See Figure 3f)
그 다음, 상기 다결정실리콘층(47)을 CMP공정 또는 전면식각공정으로 제거하여 콘택 플러그(49)를 형성한다. 이때, 상기 전면식각공정은 건식식각공정으로 실시되고, 상기 CMP공정은 상기 층간절연막(39)을 연마장벽으로 사용하여 실시되며, 실리카(silica), 세리아(ceria) 또는 알루미나(alumina)를 연마제로 함유하는 pH1 ∼ 5의 산성슬러리로 실시하여 디싱 현상을 최소화시킨다. (도 3g 참조)Next, the polysilicon layer 47 is removed by a CMP process or a front etching process to form a contact plug 49. In this case, the front etching process is performed by a dry etching process, and the CMP process is performed using the interlayer insulating layer 39 as a polishing barrier, and silica, ceria, or alumina as an abrasive. It is carried out with an acidic slurry containing pH 1-5 to minimize dishing phenomenon. (See Figure 3g)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 층간절연막을 평탄화시키기 위한 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정을 실시하고, 콘택 마스크를 식각마스크로 상기 층간절연막을 식각하여 콘택홀을 형성한 다음, 전체표면 상부에 소정 두께의 버퍼절연막을 증착한 후 전면식각하여 콘택홀 측벽에 절연막 스페이서를 형성하여 상기 CMP공정 발생한 스크래치영역에 의해 형성된 터널(tunnel)을 차단함으로써 콘택 플러그 간에 브리지(bridge)가 발생하는 것을 방지하여 소자의 공정 수율 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a chemical mechanical polishing (CMP) process is performed to planarize an interlayer insulating film, and the interlayer insulating film is formed by using a contact mask as an etching mask. After etching to form contact holes, a buffer insulating film having a predetermined thickness is deposited on the entire surface, and then etched to form insulating film spacers on the sidewalls of the contact holes to block tunnels formed by scratch regions generated in the CMP process. There is an advantage of improving the process yield and reliability of the device by preventing bridges between contact plugs.
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