KR20030054672A - Method for manufacturing a semiconductor device - Google Patents
Method for manufacturing a semiconductor device Download PDFInfo
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- KR20030054672A KR20030054672A KR1020010084885A KR20010084885A KR20030054672A KR 20030054672 A KR20030054672 A KR 20030054672A KR 1020010084885 A KR1020010084885 A KR 1020010084885A KR 20010084885 A KR20010084885 A KR 20010084885A KR 20030054672 A KR20030054672 A KR 20030054672A
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- interlayer insulating
- insulating film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게 층간절연막을 평탄화시키기 위한 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정에 의해 형성된 스크래치영역을 매립시켜 콘택 플러그 간에 브리지가 발생하는 것을 방지하는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to form a bridge between contact plugs by filling a scratch region formed by a chemical mechanical polishing (CMP) process to planarize an interlayer insulating film. The present invention relates to a method for manufacturing a semiconductor device.
반도체소자가 고집적화됨에 따라 소자의 형성공정 중 단차의 발생이 증가하면서, 사진공정이 더욱 더 어렵게 되었다. 그런 이유로 평탄화 공정의 중요성은 날로 증가되고 있다.As semiconductor devices are highly integrated, the generation of steps increases during the process of forming the devices, and the photo process becomes more difficult. That is why the importance of the planarization process is increasing day by day.
최근 각광 받고 있는 CMP공정은 이에 적합한 공정이라 할 수 있으나, 직접 웨이퍼의 표면을 물리적인 마찰에 의해 연마하기 때문에 파티클(particle)이 많이 발생하고, 미세한 패턴을 보호하는 데에 문제점이 발생하였다. 특히, 경도가 낮은 박막을 CMP공정으로 평탄화시키는 경우 스크래치 영역이 발생하여 소자의 신뢰성을 저하시키는 문제점이 있다.The CMP process, which has recently been in the spotlight, may be referred to as a suitable process. However, since the surface of the wafer is directly polished by physical friction, a lot of particles are generated and a problem occurs in protecting a fine pattern. In particular, when the thin film having a low hardness is planarized by a CMP process, a scratch region is generated, thereby lowering the reliability of the device.
이하, 첨부된 도면을 참고로 하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.
도 1a 내지 도 1e 는 종래기술에 따른 반도체소자의 제조방법을 도시한 공정 단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
먼저, 반도체기판(11) 상부에 워드라인 또는 비트라인 등의 도전배선(13)을 형성한다. 이때, 상기 도전배선(13)의 상부에는 마스크절연막패턴(15)이 적층되어 있고, 상기 도전배선(13)과 마스크절연막패턴(15)의 측벽에는 도전배선(13) 간의 절연을 위한 절연막 스페이서(17)가 구비되어 있다.First, a conductive wiring 13 such as a word line or a bit line is formed on the semiconductor substrate 11. In this case, a mask insulating film pattern 15 is stacked on the conductive wiring 13, and insulating film spacers for insulating the conductive wiring 13 are formed on sidewalls of the conductive wiring 13 and the mask insulating film pattern 15. 17).
다음, 전체표면 상부에 층간절연막(19)을 형성한다. 이때, 상기층간절연막(19)은 매립 특성이 우수한 BPSG(boro phospho silicate glass)막으로 형성된다. (도 1a 참조)Next, an interlayer insulating film 19 is formed over the entire surface. In this case, the interlayer insulating film 19 is formed of a borophospho silicate glass (BPSG) film having excellent buried characteristics. (See Figure 1A)
그 다음, 상기 층간절연막(19)을 평탄화시키는 CMP공정을 실시한다. 이때, 상기 CMP공정에 의해 층간절연막(19)의 표면으로부터 2000Å 깊이에 스크래치영역(21)이 발생된다. (도 1b 참조)Next, a CMP process is performed to planarize the interlayer insulating film 19. At this time, the scratch region 21 is generated at a depth of 2000 microseconds from the surface of the interlayer insulating film 19 by the CMP process. (See FIG. 1B)
다음, 콘택마스크를 식각마스크로 이용하여 상기 층간절연막(19)을 식각하여 콘택홀(23)을 형성한다. 이때, 상기 층간절연막(19)의 스크래치영역(21)은 상기 콘택홀(23) 간을 연결하는 터널(22)로 형성된다. (도 1c 참조)Next, the interlayer insulating layer 19 is etched using a contact mask as an etch mask to form a contact hole 23. In this case, the scratch region 21 of the interlayer insulating layer 19 is formed as a tunnel 22 connecting the contact holes 23. (See Figure 1C)
그 다음, 전체표면 상부에 다결정실리콘층(25)을 형성한다. 이때, 상기 다결정실리콘층(25)은 상기 터널(22)에도 매립된다. (도 1d 참조)Then, the polysilicon layer 25 is formed on the entire surface. In this case, the polysilicon layer 25 is also embedded in the tunnel 22. (See FIG. 1D)
다음, 상기 다결정실리콘층(25)을 식각하여 콘택 플러그(27)를 형성한다. 이때, 상기 터널(22)에 의해 상기 콘택 플러그(27) 간에 브리지가 발생한다. (도 1e 참조)Next, the polysilicon layer 25 is etched to form a contact plug 27. At this time, a bridge is generated between the contact plugs 27 by the tunnel 22. (See Figure 1E)
도 2 는 종래기술에 따른 반도체소자의 제조방법으로 콘택 플러그를 형성한 후 층간절연막이 제거된 사진으로서, CMP공정으로 발생된 스크래치로 형성된 터널에 도전층이 매립되어 콘택 플러그 간에 브리지가 발생한 것을 나타낸다.FIG. 2 is a view illustrating a method of manufacturing a semiconductor device according to the related art, in which an interlayer insulating film is removed after a contact plug is formed, showing that a bridge is formed between the contact plugs by filling a conductive layer in a tunnel formed of a scratch generated by a CMP process. .
상기와 같은 종래기술에 따른 반도체소자의 제조방법은 층간절연막으로 사용되는 BPSG막은 경도가 낮기 때문에 CMP공정으로 평탄화시키는 경우 스크래치영역을 발생시키고, 상기 스크래치영역은 터널형태로 형성되어 콘택 플러그 간에 브리지를 발생시킨다. 그리고, 상기 BPSG막보다 경도가 높은 박막을 층간절연막으로 사용하는 경우에는 매립 특성이 저하되어 콘택 플러그 간에 브리지를 발생시켜 소자의 공정 수율 및 신뢰성을 저하시키는 문제점이 있다.In the method of manufacturing a semiconductor device according to the prior art as described above, since the BPSG film used as the interlayer insulating film has a low hardness, a scratch region is generated when planarized by the CMP process, and the scratch region is formed in a tunnel shape to form a bridge between contact plugs. Generate. In addition, when a thin film having a hardness higher than that of the BPSG film is used as an interlayer insulating film, embedding properties are deteriorated, thereby generating bridges between contact plugs, thereby lowering process yield and reliability of the device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 층간절연막을 평탄화시키는 CMP공정을 진행하고, SOG막의 도포 공정 또는 열처리공정을 실시하여 상기 CMP공정에 의한 스크래치영역을 매립시켜 콘택 플러그 간에 브리지가 발생하는 것을 방지하는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the CMP process of planarizing the interlayer insulating film is performed, and the SOG film is applied or the heat treatment is performed to fill the scratch region by the CMP process so that the bridge between contact plugs is formed. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that prevents the semiconductor device from occurring.
도 1a 내지 도 1e 는 종래기술에 따른 반도체소자의 제조방법을 도시한 공정 단면도.1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2 는 종래기술에 따른 반도체소자의 제조방법으로 콘택 플러그를 형성한 후 층간절연막이 제거된 사진.2 is a photo of the interlayer insulating film removed after the contact plug is formed by a method of manufacturing a semiconductor device according to the prior art.
도 3a 내지 도 3f 는 본 발명에 따른 반도체소자의 제조방법을 도시한 공정 단면도.3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
< 도면의 주요부분에 대한 부호 설명 ><Explanation of Signs of Major Parts of Drawings>
11, 31 : 반도체기판 13, 33 : 도전배선11, 31: semiconductor substrate 13, 33: conductive wiring
15, 35 : 마스크절연막패턴 17, 37 : 절연막 스페이서15, 35 mask insulating film pattern 17, 37 insulating film spacer
19, 39 : 층간절연막 21, 41 : 스크래치영역19, 39: interlayer insulating film 21, 41: scratch area
22 : 터널 23, 45 : 콘택홀22: tunnel 23, 45: contact hole
25, 47 : 다결정실리콘층 27, 49 : 콘택 플러그25, 47: polysilicon layer 27, 49: contact plug
43 : SOG막43: SOG film
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,
층간절연막을 평탄화시키는 화학적 기계적 연마공정으로 발생된 스크래치영역을 제거하는 반도체소자의 제조방법에 있어서,In the method of manufacturing a semiconductor device to remove the scratch region generated by a chemical mechanical polishing process to planarize the interlayer insulating film,
반도체기판 상부에 도전배선을 형성하는 공정과,Forming a conductive wiring on the semiconductor substrate;
전체표면 상부에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film over the entire surface;
상기 층간절연막을 평탄화시키는 화학적 기계적 연마공정을 실시하는 공정과,Performing a chemical mechanical polishing step of planarizing the interlayer insulating film;
상기 화학적 기계적 연마공정으로 발생된 스크래치영역을 매립시키는 공정과,Embedding the scratch area generated by the chemical mechanical polishing process;
콘택마스크를 식각마스크로 이용하여 상기 층간절연막을 식각하여 콘택홀을 형성하는 공정과,Forming a contact hole by etching the interlayer insulating layer using a contact mask as an etching mask;
상기 콘택홀을 매립하는 콘택플러그를 형성하는 공정과,Forming a contact plug to fill the contact hole;
상기 층간절연막은 BPSG막인 것과,The interlayer insulating film is a BPSG film,
상기 화학적 기계적 연마공정으로 발생된 스크래치영역은 SOG막 또는 열처리공정으로 매립시키는 공정을 포함하는 것을 제1특징으로 한다.The first feature is that the scratch region generated by the chemical mechanical polishing process includes a process of filling the SOG film or the heat treatment process.
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,
층간절연막을 평탄화시키는 화학적 기계적 연마공정으로 발생된 스크래치영역을 제거하는 반도체소자의 제조방법에 있어서,In the method of manufacturing a semiconductor device to remove the scratch region generated by a chemical mechanical polishing process to planarize the interlayer insulating film,
반도체기판 상부에 도전배선을 형성하는 공정과,Forming a conductive wiring on the semiconductor substrate;
전체표면 상부에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film over the entire surface;
상기 층간절연막을 평탄화시키는 화학적 기계적 연마공정을 실시하는 공정과,Performing a chemical mechanical polishing step of planarizing the interlayer insulating film;
전체표면 상부에 SOG막을 도포하여 상기 화학적 기계적 연마공정으로 발생된 스크래치영역을 매립시키는 공정과,Applying a SOG film over the entire surface to bury the scratch region generated by the chemical mechanical polishing process;
콘택마스크를 식각마스크로 이용하여 상기 SOG막과 층간절연막을 식각하여 콘택홀을 형성하는 공정과,Forming a contact hole by etching the SOG film and the interlayer insulating film using a contact mask as an etching mask;
상기 콘택홀을 매립하는 콘택플러그를 형성하는 공정과,Forming a contact plug to fill the contact hole;
상기 층간절연막은 BPSG막인 것과,The interlayer insulating film is a BPSG film,
상기 SOG막은 유기계 SOG막 또는 무기계 SOG막인 것과,The SOG film is an organic SOG film or an inorganic SOG film,
상기 SOG막은 100 ∼ 1000Å 두께로 형성되는 것과,The SOG film is formed to a thickness of 100 ~ 1000Å,
상기 SOG막은 400 ∼ 450℃에서 20 ∼ 60분간 열처리되는 것을 포함하는 것을 제2특징으로 한다.A second feature of the SOG film includes a heat treatment at 400 to 450 ° C. for 20 to 60 minutes.
또한, 이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In addition, the method of manufacturing a semiconductor device according to the present invention in order to achieve the above object,
층간절연막을 평탄화시키는 화학적 기계적 연마공정으로 발생된 스크래치영역을 제거하는 반도체소자의 제조방법에 있어서,In the method of manufacturing a semiconductor device to remove the scratch region generated by a chemical mechanical polishing process to planarize the interlayer insulating film,
반도체기판 상부에 도전배선을 형성하는 공정과,Forming a conductive wiring on the semiconductor substrate;
전체표면 상부에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film over the entire surface;
상기 층간절연막을 평탄화시키는 화학적 기계적 연마공정을 실시하는 공정과,Performing a chemical mechanical polishing step of planarizing the interlayer insulating film;
상기 층간절연막을 플로우시켜 상기 화학적 기계적 연마공정으로 발생된 스크래치영역을 매립시키는 열처리공정과,A heat treatment process of flowing the interlayer insulating film to fill in the scratch region generated by the chemical mechanical polishing process;
콘택마스크를 식각마스크로 이용하여 상기 층간절연막을 식각하여 콘택홀을 형성하는 공정과,Forming a contact hole by etching the interlayer insulating layer using a contact mask as an etching mask;
상기 콘택홀을 매립하는 콘택플러그를 형성하는 공정과,Forming a contact plug to fill the contact hole;
상기 층간절연막은 BPSG막인 것과,The interlayer insulating film is a BPSG film,
상기 열처리공정은 800 ∼ 1500℃의 N2분위기에서 20 ∼ 60분간 실시되는 것과,The heat treatment step is performed for 20 to 60 minutes in an N 2 atmosphere of 800 ~ 1500 ℃,
상기 열처리공정은 800 ∼ 1500℃의 H2/O2를 이용한 습식분위기에서 20 ∼ 60분간 실시되는 것을 포함하는 것을 제3특징으로 한다.A third feature of the heat treatment step includes performing 20 to 60 minutes in a wet atmosphere using H 2 / O 2 at 800 to 1500 ° C.
본 발명의 원리는 경도가 낮은 BPSG막을 평탄화시키기 위한 CMP공정 시 발생된 스크래치영역을 SOG막으로 매립시키거나 열처리공정을 실시하여 상기 BPSG막을 플로우시켜 매립시켜 콘택 플러그 간에 브리지가 발생하는 것을 방지하는 것이다.The principle of the present invention is to prevent the bridges between contact plugs by embedding the scratch region generated during the CMP process to planarize the low hardness BPSG film with SOG film or by performing heat treatment to flow the BPSG film into the buried film. .
이하, 첨부된 도면을 참고로 하여 본 발명에 따른 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail according to the present invention.
도 3a 내지 도 3f 는 본 발명에 따른 반도체소자의 제조방법을 도시한 공정 단면도이다.3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
먼저, 반도체기판(31) 상부에 워드라인 또는 비트라인 등의 도전배선(33)을 형성한다. 이때, 상기 도전배선(33)의 상부에는 마스크절연막패턴(35)이 적층되어 있고, 상기 도전배선(33)과 마스크절연막패턴(35)의 측벽에는 도전배선(33) 간의 절연을 위한 절연막 스페이서(37)가 구비되어 있다.First, a conductive wiring 33 such as a word line or a bit line is formed on the semiconductor substrate 31. In this case, a mask insulating film pattern 35 is stacked on the conductive wiring 33, and an insulating film spacer for insulating between the conductive wiring 33 is formed on sidewalls of the conductive wiring 33 and the mask insulating film pattern 35. 37).
다음, 전체표면 상부에 층간절연막(39)을 형성한다. 이때, 상기 층간절연막(39)은 매립 특성이 우수한 BPSG막으로 형성된다. (도 3a 참조)Next, an interlayer insulating film 39 is formed over the entire surface. In this case, the interlayer insulating film 39 is formed of a BPSG film having excellent embedding characteristics. (See Figure 3A)
그 다음, 상기 층간절연막(39)을 평탄화시키는 CMP공정을 실시한다. 이때, 상기 CMP공정에 의해 상기 층간절연막(39)의 표면으로부터 2000Å 깊이에 스크래치영역(41)이 형성된다. (도 3b 참조)Next, a CMP process is performed to planarize the interlayer insulating film 39. At this time, the scratch region 41 is formed at a depth of 2000 microseconds from the surface of the interlayer insulating film 39 by the CMP process. (See Figure 3b)
다음, 전체표면 상부에 SOG막(43)을 도포하여 상기 스크래치영역(41)을 매립시킨다. 이때, 상기 SOG막(43)은 유기계 또는 무기계 SOG막이 사용되며, 상기 층간절연막(39) 상에 최소한의 두께가 남도록 100 ∼ 1000Å 두께 형성된다.Next, an SOG film 43 is applied over the entire surface to fill the scratch region 41. In this case, the SOG film 43 may be formed of an organic or inorganic SOG film, and may be formed to have a thickness of 100 to 1000 Å so that the minimum thickness remains on the interlayer insulating film 39.
한편, 상기 SOG막(43)을 도포한 후 400 ∼ 450℃에서 20 ∼ 60분간 열처리공정을 실시할 수도 있다. (도 3c 참조)In addition, after apply | coating the said SOG film 43, you may perform the heat processing process at 400-450 degreeC for 20 to 60 minutes. (See Figure 3c)
그 다음, 콘택마스크를 식각마스크로 이용하여 상기 SOG막(43)과 층간절연막(39)을 식각하여 콘택홀(45)을 형성한다. (도 3d 참조)Next, the SOG film 43 and the interlayer insulating film 39 are etched using the contact mask as an etch mask to form the contact hole 45. (See FIG. 3D)
다음, 전체표면 상부에 다결정실리콘층(47)을 형성한다. (도 3e 참조)Next, a polysilicon layer 47 is formed over the entire surface. (See Figure 3E)
그 다음, 상기 다결정실리콘층(47)을 식각하여 콘택 플러그(49)를 형성한다. 여기서, 상기 콘택 플러그(49) 형성 후 상기 SOG막(43)은 거의 남지 않는다. (도 3f 참조)Next, the polysilicon layer 47 is etched to form a contact plug 49. Here, the SOG film 43 hardly remains after the contact plug 49 is formed. (See Figure 3f)
또한, 본 발명에 따른 다른 실시예로서 도 3b 까지의 공정을 실시한 다음, 열처리공정을 실시하여 층간절연막으로 사용되는 BPSG막을 플로우시켜 스크래치영역을 매립시킬 수도 있다. 그리고, 상기 스크래치영역을 매립시킨 후 후속 공정은 도 3d 내지 도 3f 까지의 공정과 같다.In addition, as another embodiment according to the present invention, the process up to FIG. 3B may be performed, and then a heat treatment process may be performed to flow the BPSG film used as the interlayer insulating film to fill the scratch region. Subsequently, the subsequent process after filling the scratch region is the same as the process of FIGS. 3D to 3F.
여기서, 상기 열처리공정은 800 ∼ 1500℃의 N2분위기 또는 H2/O2를 이용한 습식분위기에서 20 ∼ 60분간 실시된다.Here, the heat treatment step is performed for 20 to 60 minutes in a N 2 atmosphere of 800 ~ 1500 ℃ or a wet atmosphere using H 2 / O 2 .
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 층간절연막을 평탄화시키기 위한 CMP공정으로 발생한 스크래치영역을 SOG막 또는 열처리공정으로 매립함으로써 콘택 플러그 간에 브리지가 발생하는 것을 방지하여 소자의 공정 수율 및 신뢰성을 향상시키는 이점이 있다.As described above, the method of manufacturing a semiconductor device according to the present invention prevents bridges from occurring between contact plugs by filling a scratch region generated by a CMP process for planarizing an interlayer insulating film by an SOG film or a heat treatment process. There is an advantage in improving yield and reliability.
Claims (12)
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20050070891A (en) * | 2003-12-31 | 2005-07-07 | 동부아남반도체 주식회사 | Method for preventing micro scratch defect |
| KR100693785B1 (en) * | 2004-12-27 | 2007-03-12 | 주식회사 하이닉스반도체 | Method for forming interlayer dielectric in semiconductor memory device |
| CN111554576A (en) * | 2020-05-18 | 2020-08-18 | 中国科学院微电子研究所 | Planarization method |
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| JPH10150035A (en) * | 1996-11-18 | 1998-06-02 | Asahi Chem Ind Co Ltd | Manufacture of semiconductor device |
| KR19980018994A (en) * | 1996-08-30 | 1998-06-05 | 다까노 야스아끼 | Fabrication Method of Semiconductor Device and Abrasive Liquid Used Therein |
| KR19980075804A (en) * | 1997-04-02 | 1998-11-16 | 윤종용 | Planarization Method of Semiconductor Device |
| JP2000012679A (en) * | 1998-06-06 | 2000-01-14 | United Microelectronics Corp | Method for manufacturing shallow trench insulation structure part |
| KR20010092398A (en) * | 2000-03-21 | 2001-10-24 | 니시가키 코지 | Method for forming element isolation region |
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| KR19980018994A (en) * | 1996-08-30 | 1998-06-05 | 다까노 야스아끼 | Fabrication Method of Semiconductor Device and Abrasive Liquid Used Therein |
| JPH10150035A (en) * | 1996-11-18 | 1998-06-02 | Asahi Chem Ind Co Ltd | Manufacture of semiconductor device |
| KR19980075804A (en) * | 1997-04-02 | 1998-11-16 | 윤종용 | Planarization Method of Semiconductor Device |
| JP2000012679A (en) * | 1998-06-06 | 2000-01-14 | United Microelectronics Corp | Method for manufacturing shallow trench insulation structure part |
| KR20010092398A (en) * | 2000-03-21 | 2001-10-24 | 니시가키 코지 | Method for forming element isolation region |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20050070891A (en) * | 2003-12-31 | 2005-07-07 | 동부아남반도체 주식회사 | Method for preventing micro scratch defect |
| KR100693785B1 (en) * | 2004-12-27 | 2007-03-12 | 주식회사 하이닉스반도체 | Method for forming interlayer dielectric in semiconductor memory device |
| CN111554576A (en) * | 2020-05-18 | 2020-08-18 | 中国科学院微电子研究所 | Planarization method |
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