KR100370162B1 - method for manufacturing semiconductor device - Google Patents

method for manufacturing semiconductor device Download PDF

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Publication number
KR100370162B1
KR100370162B1 KR10-2000-0077112A KR20000077112A KR100370162B1 KR 100370162 B1 KR100370162 B1 KR 100370162B1 KR 20000077112 A KR20000077112 A KR 20000077112A KR 100370162 B1 KR100370162 B1 KR 100370162B1
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South Korea
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film
forming
metal silicide
nitride film
oxide
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KR10-2000-0077112A
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Korean (ko)
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KR20020046781A (en
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허태형
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 게이트 라인을 수직 형태로 형성하여 랜딩 플러그에 의한 브릿지 현상을 방지하도록 한 반도체 소자의 제조방법에 관한 것으로서, 절연 기판상에 폴리 실리콘막 및 금속 실리사이드막을 차례로 형성하는 단계와, 상기 금속 실리사이드막상에 제 1 질화막을 형성하는 단계와, 상기 제 1 질화막상에 산화막을 형성하고 선택적으로 패터닝하여 산화막 패턴을 형성하는 단계와, 상기 산화막 패턴의 양측면에 제 2 질화막 측벽을 형성하는 단계와, 상기 산화막 패턴을 마스크로 이용하여 상기 제 1 질화막, 금속 실리사이드막, 폴리 실리콘막을 선택적으로 제거하여 게이트 라인을 형성하는 단계를 포함하여 형성함을 특징으로 한다.The present invention relates to a method of manufacturing a semiconductor device in which a gate line is formed in a vertical shape to prevent a bridge phenomenon caused by a landing plug. The method includes sequentially forming a polysilicon film and a metal silicide film on an insulating substrate, and the metal silicide. Forming a first nitride film on the film, forming an oxide film on the first nitride film and selectively patterning the oxide film pattern, and forming second nitride film sidewalls on both sides of the oxide pattern; And forming a gate line by selectively removing the first nitride film, the metal silicide film, and the polysilicon film using an oxide pattern as a mask.

Description

반도체 소자의 제조방법{method for manufacturing semiconductor device}Method for manufacturing semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 게이트 라인 사이에 랜딩 플러그(landing plug) 형성시 브릿지(bridge) 발생을 방지하는데 적당한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for preventing the occurrence of bridges when a landing plug is formed between gate lines.

일반적으로, 반도체 소자의 집적도가 높아짐에 따라 비트 라인 또는 캐패시터의 하부 전극을 형성하는 방법으로, 먼저 콘택 플러그를 형성하고 콘택 플러그위에 비트 라인과 캐패시터의 하부 전극을 형성하는 방법이 개발되었다.In general, as a method of forming a lower electrode of a bit line or a capacitor as the degree of integration of semiconductor devices increases, a method of first forming a contact plug and then forming a lower electrode of the bit line and the capacitor on the contact plug has been developed.

상기와 같은 콘택 플러그를 형성하기 위해서는 콘택홀을 폴리실리콘으로 매립한 후 평탄화와, 각 콘택 플러그간의 절연을 위한 에치 백(etch back)이나 화학기계적 연마 공정 등을 거쳐야 하는데, 평탄화 특성과 절연 특성에서 우수한 화학기계적 연마 공정을 주로 사용하고 있다.In order to form the contact plug as described above, the contact hole must be filled with polysilicon and then planarized, and subjected to an etch back or chemical mechanical polishing process for insulation between the contact plugs. Excellent chemical mechanical polishing process is mainly used.

256M 급 이상의 소자에서 워드 라인 스페이서(word line spacer)로 질화막을 사용하면 질화막과 층간 절연막으로 사용하는 산화막간의 연마비(polishing rate)의 선택비로 인하여 셀 지역의 질화막 바로 위까지 층간 절연막을 연마할 수 있으며, 질화막과 폴리실리콘간의 연마비의 선택비로 인하여 스페이서의 손상 없이 랜딩 플러그 폴리실리콘(콘택 플러그) 화학기계적 연마 공정을 진행할 수 있다.When the nitride film is used as a word line spacer in a device of 256M or more, the interlayer insulating film can be polished up to the nitride film in the cell region due to the selection ratio of the polishing rate between the nitride film and the oxide film used as the interlayer insulating film. In addition, the landing plug polysilicon (contact plug) chemical mechanical polishing process may be performed without damaging the spacer due to the selection ratio of the polishing ratio between the nitride film and the polysilicon.

한편, 현재의 64M급 이상의 디바이스들은 대부분 캐패시터 콘택을 실리콘 기판에 직접 형성하지 않고 랜딩 플러그(landing plug)를 사용하여 간접적으로 실리콘 기판과 연결하고 있다.On the other hand, most current devices of 64M or more are indirectly connected to the silicon substrate by using a landing plug instead of forming a capacitor contact directly on the silicon substrate.

상기 랜딩 플러그는 일반적으로 게이트 라인을 형성한 후 그 사이에 섬 패턴(island pattern)으로 형성하게 된다.The landing plug generally forms a gate line and then forms an island pattern therebetween.

상기와 같이 섬 패턴을 형성하기 위해 에칭을 할 때 그 폴리 실리콘이 게이트 라인의 측벽을 따라서 남게 된다.When etched to form an island pattern as described above, the polysilicon remains along the sidewall of the gate line.

즉, 게이트 라인의 높이가 2500 ~ 4500Å정도일 때 게이트 라인의 측벽을 따라 형성된 랜딩 플러그의 높이도 이 만큼 높아지게 되고 이것을 잔류물(residue)이 남지 않게 에칭하는 것이 어렵다.That is, when the height of the gate line is about 2500 to 4500Å, the height of the landing plug formed along the sidewall of the gate line is also increased as much as this, and it is difficult to etch it so that no residue remains.

따라서 상기와 같은 문제를 해결하기 위해 타겟 대비 추가 에칭을 하게 되고, 여러 가지 장비의 의존성, CD 문제 등 여러 각도로 해결을 하려고 하지만 이것으로도 해결은 완벽하게 되지 않고 있다.Therefore, in order to solve the above problems, additional etching is performed against the target, and various solutions such as dependency of various equipments and CD problems are attempted to be solved at various angles, but this is not a perfect solution.

도 1은 종래의 게이트 라인을 나타낸 구조 단면도이다.1 is a structural cross-sectional view showing a conventional gate line.

도 1에서와 같이, 종래의 게이트 라인은 폴리 실리콘막(11)과 금속 실리사이드막(12) 그리고 질화막(13)과 산화막(14)으로 적층된 절연막의 3중 구조로 되어 있다.As shown in FIG. 1, the conventional gate line has a triple structure of an insulating film laminated with a polysilicon film 11, a metal silicide film 12, and a nitride film 13 and an oxide film 14.

이때 상기 금속 실리사이드막(12)쪽이 역기울기(negative slope)를 갖거나 안으로 패인 모습을 보이고 있다.At this time, the metal silicide layer 12 has a negative slope or is indented.

도 2는 종래의 게이트 라인 사이에 형성되는 랜딩 플러그를 나타낸 평면도이다.2 is a plan view illustrating a landing plug formed between a conventional gate line.

도 2에서와 같이, 일정한 간격을 갖고 형성되는 복수개의 게이트 라인(21)과, 상기 게이트 라인(21) 사이에 형성되는 랜딩 플러그(22)로 구성된다.As shown in FIG. 2, the plurality of gate lines 21 are formed at regular intervals and the landing plugs 22 are formed between the gate lines 21.

여기서 미설명한 23은 랜딩 플러그(22) 형성시 게이트 라인(21)의 측벽을 따라 형성되는 폴리 잔유물이다.23, which is not described herein, is a poly residue formed along sidewalls of the gate line 21 when the landing plug 22 is formed.

한편, 상기 폴리 잔유물(23)은 게이트 라인(21)의 높이가 높기 때문에 평면 사진으로는 잘 안보이고 게이트 라인(21)의 중간 혹은 바닥에 많이 남게 된다.On the other hand, since the height of the gate line 21 is high, the poly residue 23 is hard to see in a planar picture and remains in the middle or bottom of the gate line 21.

따라서 종래의 도 1과 같이, 역기울기를 갖는 게이트 라인 사이에 랜딩 플러그(22)를 형성할 때 이웃하는 게이트 라인을 측벽을 따라 폴리 잔류물(23)이 존재하여 게이트 라인간에 브릿지가 유발된다.Accordingly, as shown in FIG. 1, when the landing plugs 22 are formed between gate lines having inverse slopes, poly residues 23 exist along sidewalls of neighboring gate lines, thereby causing bridges between the gate lines.

즉, 게이트 라인을 형성한 후 게이트 라인의 사이에 랜딩 플러그용 폴리 실리콘을 매립하고 식각시 에칭 가스(SF6)의 직진성에 의해 에칭이 안되는 부분이 생긴다. 따라서 추가 에칭시 실리콘 기판에 맞고 반사되어 올라온 가스에 의해 대부분 에칭이 되지만 브릿지 발생 가능성을 많아지게 된다.That is, after the gate line is formed, the landing plug polysilicon is embedded between the gate lines, and a portion which cannot be etched due to the straightness of the etching gas SF6 is formed during etching. Therefore, in the case of further etching, most of the etching is performed by the gas that is reflected and reflected on the silicon substrate, but the possibility of bridge generation increases.

이상과 같은 종래의 반도체 소자의 제조방법에 있어서 다음과 같은 문제점이 있었다.In the conventional method of manufacturing a semiconductor device as described above has the following problems.

즉, 게이트 라인이 역기울기를 갖거나 안으로 패인 형태를 가지고 있음으로 게이트 라인의 사이에 형성된 랜딩 플러그는 게이트 라인의 측벽을 따라 형성된 랜딩 플러그가 제거되지 않고 잔류하여 이웃하는 게이트 라인간에 브릿지를 유발한다.That is, the landing plugs formed between the gate lines because the gate lines have an inclination or inwardly inclined shape, the landing plugs formed along the sidewalls of the gate lines are not removed but remain bridges between neighboring gate lines. .

본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 게이트 라인을 수직 형태로 형성하여 랜딩 플러그에 의한 브릿지 현상을 방지하도록 한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made in view of the above-described problems, and an object thereof is to provide a method of manufacturing a semiconductor device in which a gate line is vertically formed to prevent a bridge phenomenon caused by a landing plug.

도 1은 종래의 게이트 라인을 나타낸 구조 단면도1 is a structural cross-sectional view showing a conventional gate line

도 2는 종래의 게이트 라인 사이에 형성되는 랜딩 플러그를 나타낸 평면도2 is a plan view showing a landing plug formed between a conventional gate line

도 3a 내지 도 3d는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

31 : 폴리 실리콘막 32 : 금속 실리사이드막31 polysilicon film 32 metal silicide film

33 : 제 1 질화막 34 : 산화막 패턴33: first nitride film 34: oxide film pattern

35 : 제 2 질화막 측벽35: second nitride film sidewall

상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 제조방법은 절연 기판상에 폴리 실리콘막 및 금속 실리사이드막을 차례로 형성하는 단계와, 상기 금속 실리사이드막상에 제 1 질화막을 형성하는 단계와, 상기 제 1 질화막상에 산화막을 형성하고 선택적으로 패터닝하여 산화막 패턴을 형성하는 단계와, 상기 산화막 패턴의 양측면에 제 2 질화막 측벽을 형성하는 단계와, 상기 산화막 패턴을 마스크로 이용하여 상기 제 1 질화막, 금속 실리사이드막, 폴리 실리콘막을 선택적으로 제거하여 게이트 라인을 형성하는 단계를 포함하여 형성함을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of sequentially forming a polysilicon film and a metal silicide film on an insulating substrate, forming a first nitride film on the metal silicide film, Forming an oxide layer on the first nitride layer and selectively patterning the oxide layer to form an oxide layer pattern, forming sidewalls of the second nitride layer on both sides of the oxide layer pattern, using the oxide layer pattern as a mask, And selectively removing the metal silicide layer and the polysilicon layer to form a gate line.

이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3d는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도이다.3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

도 3a에 도시된 바와 같이, 절연 기판(도시되지 않음)상에 폴리 실리콘막(31)과 금속 실리사이드막(32)을 차례로 증착하고, 상기 금속 실리사이드막(32)상에 제 1 질화막(33)을 형성한다.As shown in FIG. 3A, a polysilicon film 31 and a metal silicide film 32 are sequentially deposited on an insulating substrate (not shown), and the first nitride film 33 is disposed on the metal silicide film 32. To form.

여기서 상기 금속 실리사이드막(32)은 텅스텐 또는 텅스텐 실리사이드막을 사용할 수 있다.Here, the metal silicide layer 32 may use tungsten or a tungsten silicide layer.

이어, 상기 제 1 질화막(33)상에 산화막을 형성하고, 포토 및 식각공정을 통해 상기 산화막을 패터닝하여 산화막 패턴(34)을 형성한다.Subsequently, an oxide layer is formed on the first nitride layer 33, and the oxide layer is patterned through photo and etching processes to form an oxide layer pattern 34.

여기서 상기 산화막 패턴(34)이 형성된 부분이 게이트 영역이다.The portion where the oxide layer pattern 34 is formed is a gate region.

도 3b에 도시한 바와 같이, 상기 산화막 패턴(34)을 포함한 절연 기판의 전면에 제 2 질화막(35)을 형성한다.As shown in FIG. 3B, a second nitride film 35 is formed on the entire surface of the insulating substrate including the oxide film pattern 34.

도 3c에 도시한 바와 같이, 상기 제 2 질화막(35)의 전면에 에치백 공정을 실시하여 상기 산화막 패턴(34)의 양측면에 제 2 질화막 측벽(35a)을 형성한다.As illustrated in FIG. 3C, an etch back process is performed on the entire surface of the second nitride film 35 to form second nitride film sidewalls 35a on both sides of the oxide film pattern 34.

도 3d에 도시한 바와 같이, 상기 산화막 패턴(34)을 마스크로 이용하여 상기제 1 질화막(33), 금속 실리사이드막(32), 폴리 실리콘막(31)을 선택적으로 제거하여 게이트 라인을 형성한다.As shown in FIG. 3D, the first nitride layer 33, the metal silicide layer 32, and the polysilicon layer 31 are selectively removed to form a gate line using the oxide layer pattern 34 as a mask. .

여기서 종래의 도 1과 같이 금속 실리사이드막(12)의 측면에 발생한 역기울기 및 패임 현상은 본 발명에서 제 2 질화막 측벽(35a)의 두께가 얇아지면서 사라지게 된다. 즉, 도 3c에 비해 도 3d의 경우 제 2 질화막 측벽(35a)이 많이 얇아져 있음을 볼 수 있다.Here, as shown in FIG. 1, the reverse slope and dents occurring on the side surfaces of the metal silicide layer 12 disappear as the thickness of the second nitride layer sidewall 35a becomes thin in the present invention. That is, in FIG. 3D, the second nitride film sidewall 35a is much thinner than in FIG. 3C.

따라서 상기와 같이 수직한 게이트 라인을 형성함으로서 이후 게이트 라인의 사이에 랜딩 플러그를 형성하더라도 브릿지 현상을 방지한다.Therefore, by forming the vertical gate line as described above, even if the landing plug is formed between the gate lines, the bridge phenomenon is prevented.

한편, 본 발명의 다른 실시예로 상기 산화막 패턴(34)의 양측면에 제 2 질화막 측벽(35)을 형성하지 않고, 상기 산화막 패턴(34)을 포함한 절연 기판의 전면에 제 2 질화막(35)을 형성한 후 이방성 에칭을 통해 제 2 질화막(35), 제 1 질화막(33), 금속 실리사이드막(32), 폴리 실리콘막(31)을 선택적으로 제거하여 게이트 라인을 형성할 수도 있다.Meanwhile, in another embodiment of the present invention, the second nitride film 35 is formed on the entire surface of the insulating substrate including the oxide film pattern 34 without forming the second nitride film sidewalls 35 on both sides of the oxide film pattern 34. After forming, the gate line may be formed by selectively removing the second nitride film 35, the first nitride film 33, the metal silicide film 32, and the polysilicon film 31 through anisotropic etching.

이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 제조방법은 다음과 같은 효과가 있다.As described above, the method for manufacturing a semiconductor device according to the present invention has the following effects.

즉, 게이트 라인을 수직한 형태로 형성함으로서 게이트 라인의 사이에 랜딩 플러그를 형성하더라도 브릿지 현상을 방지할 수 있다.That is, by forming the gate lines in a vertical shape, even when a landing plug is formed between the gate lines, the bridge phenomenon can be prevented.

Claims (2)

절연 기판상에 폴리 실리콘막 및 금속 실리사이드막을 차례로 형성하는 단계;Sequentially forming a polysilicon film and a metal silicide film on the insulating substrate; 상기 금속 실리사이드막상에 제 1 질화막을 형성하는 단계;Forming a first nitride film on the metal silicide film; 상기 제 1 질화막상에 산화막을 형성하고 선택적으로 패터닝하여 산화막 패턴을 형성하는 단계;Forming an oxide film on the first nitride film and selectively patterning the oxide film to form an oxide film pattern; 상기 산화막 패턴의 양측면에 제 2 질화막 측벽을 형성하는 단계;Forming sidewalls of the second nitride film on both sides of the oxide film pattern; 상기 산화막 패턴을 마스크로 이용하여 상기 제 1 질화막, 금속 실리사이드막, 폴리 실리콘막을 선택적으로 제거하여 게이트 라인을 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 제조방법.And forming a gate line by selectively removing the first nitride film, the metal silicide film, and the polysilicon film by using the oxide pattern as a mask. 삭제delete
KR10-2000-0077112A 2000-12-15 2000-12-15 method for manufacturing semiconductor device KR100370162B1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03114225A (en) * 1989-09-28 1991-05-15 Sony Corp Manufacture of semiconductor device
KR19980040676A (en) * 1996-11-29 1998-08-17 김광호 Gate Forming Method of Semiconductor Device
JPH11204659A (en) * 1998-01-14 1999-07-30 Sony Corp Semiconductor device
KR19990066542A (en) * 1998-01-30 1999-08-16 윤종용 Gate electrode formation method using spacer and self-alignment contact formation method using same
JP2000022009A (en) * 1998-07-01 2000-01-21 Nec Corp Manufacture of non-volatile semiconductor storage device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03114225A (en) * 1989-09-28 1991-05-15 Sony Corp Manufacture of semiconductor device
KR19980040676A (en) * 1996-11-29 1998-08-17 김광호 Gate Forming Method of Semiconductor Device
JPH11204659A (en) * 1998-01-14 1999-07-30 Sony Corp Semiconductor device
KR19990066542A (en) * 1998-01-30 1999-08-16 윤종용 Gate electrode formation method using spacer and self-alignment contact formation method using same
JP2000022009A (en) * 1998-07-01 2000-01-21 Nec Corp Manufacture of non-volatile semiconductor storage device

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