KR20040059261A - shallow trench isolation of semiconductor device and its manufacturing method - Google Patents

shallow trench isolation of semiconductor device and its manufacturing method Download PDF

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KR20040059261A
KR20040059261A KR1020020085848A KR20020085848A KR20040059261A KR 20040059261 A KR20040059261 A KR 20040059261A KR 1020020085848 A KR1020020085848 A KR 1020020085848A KR 20020085848 A KR20020085848 A KR 20020085848A KR 20040059261 A KR20040059261 A KR 20040059261A
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silicon substrate
trench
teos
etching
predetermined
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KR1020020085848A
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Korean (ko)
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김인수
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동부전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

Abstract

PURPOSE: An STI(Shallow Trench Isolation) structure and a method for manufacturing the same are provided to restrain void and to improve CD(Critical Dimension) of a trench by forming a dry-etched recess plane on a substrate. CONSTITUTION: A dry-etched recess plane(11) with a relatively wide width is formed by locally etching a silicon substrate. A trench(14) with a relatively narrow width is formed in the substrate. An isolation layer(16) is formed by growing an insulating layer in the trench.

Description

반도체 소자의 샐로우 트렌치 분리막 구조 및 그 제조 방법{shallow trench isolation of semiconductor device and its manufacturing method}Shallow trench isolation structure of semiconductor device and its manufacturing method

본 발명은 반도체 소자의 샐로우 트렌치 분리막 구조 및 그 제조 방법에 관한 것으로, 보다 상세하게 설명하면 트렌치의 임계 칫수를 작게 하여 소자 집적도를 향상시키고, 절연막의 보이드를 억제할 수 있는 반도체 소자의 샐로우 트렌치 분리막 구조 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a structure of a shallow trench separator of a semiconductor device and a method of manufacturing the same. More specifically, the present invention relates to a shallow method of a semiconductor device capable of improving device integration by reducing a critical dimension of a trench and suppressing voids in an insulating film. It relates to a trench separator structure and a method of manufacturing the same.

반도체 소자에는 트랜지스터, 커패시터 등의 단위 소자로 된 셀들이 반도체 소자의 용량에 따라 존재하는데 이러한 셀들은 서로 독립적인 동작 특성을 위해 전기적으로 분리될 필요가 있다.In the semiconductor device, cells of unit devices such as transistors and capacitors exist according to the capacity of the semiconductor device, and these cells need to be electrically separated for operation characteristics independent of each other.

이와 같은 전기적 분리를 위해 통상 두가지 분리 방법이 사용된다. 첫번째 방법은 LOCOS(Local Oxidation of Silicon)이고, 두번째 방법은 STI(Shallow Trench Isolation)이다. 한편, 반도체 소자의 사이즈 및 두께가 점차 작아짐에 따라, 액티브 영역의 침식(active area encroachment), 보다 작은 졍션 모서리의 캐패시터(smaller junction edge capacitance), 평탄 표면 구조(planar surface topography) 등에서 장점을 가지고 있는 STI 기술이 주로 사용되고 있으며, LOCOS 기술은 잘 사용되지 않고 있다.Two separation methods are commonly used for such electrical separation. The first method is Local Oxidation of Silicon (LOCOS) and the second method is Shallow Trench Isolation (STI). Meanwhile, as the size and thickness of semiconductor devices become smaller, they have advantages in active area encroachment, smaller junction edge capacitance, and planar surface topography. STI technology is mainly used, and LOCOS technology is not used well.

그러나, 위와 같은 STI 기술도 현재 비교적 넓은 트렌치의 임계 칫수를 가지고 있기 때문에, 소자의 집적도 향상에 한계가 있다. 더불어, 넓은 트렌치의 내측에 절연막을 성장시키기 때문에, 절연막 내측에 다수의 보이드가 발생하여 소자 특성도 저하되는 문제가 있다.However, such STI technology also currently has a critical dimension of relatively wide trenches, and thus there is a limit to improving the integration of the device. In addition, since the insulating film is grown inside the wide trench, a large number of voids are generated inside the insulating film, thereby deteriorating device characteristics.

따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 본 발명의 목적은 트렌치의 임계 칫수를 작게 하여 소자 집적도를 향상시키고, 또한 보이드를 억제할 수 있는 반도체 소자의 샐로우 트렌치 분리막 구조 및 그 제조 방법을 제공하는데 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to reduce the depth of the trench to improve device integration and suppress voids. It is to provide a structure and a method of manufacturing the same.

도1은 본 발명에 의한 반도체 소자의 샐로우 트렌치 분리막 구조를 도시한 단면도이다.1 is a cross-sectional view illustrating a structure of a shallow trench separator of a semiconductor device according to the present invention.

도2a 내지 도2g는 본 발명에 의한 반도체 소자의 샐로우 트렌치 분리막 제조 방법을 도시한 순차 설명도다.2A to 2G are sequential diagrams illustrating a method of manufacturing a shallow trench separator of a semiconductor device according to the present invention.

-도면중 주요 부호에 대한 설명-Description of the main symbols in the drawings

2; 실리콘 서브스트레이트 4; 패드 산화막2; Silicon substrate 4; Pad oxide

6; 패드 질화막 8; TEOS6; Pad nitride film 8; TEOS

10; 포토 패턴 11; 화학적 드라이 에칭면10; Photo pattern 11; Chemical dry etching surface

12; 스페이서 TEOS 14; 트렌치12; Spacer TEOS 14; Trench

16; 절연막16; Insulating film

상기한 목적을 달성하기 위해 본 발명은 실리콘 서브스트레이트에서 다수의 반도체 소자를 전기적으로 분리하기 위한 샐로우 트렌치 분리막 구조에 있어서, 상기 실리콘 서브스트레이트의 표면에 형성된 일정 폭의 화학적 드라이 에칭면과, 상기 화학적 드라이 에칭면의 폭보다 작은 폭를 가지며, 일정 깊이로 에칭된 트렌치와, 상기 트렌치 내측에서 상부로 일정 두께만큼 성장된 절연막을 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a shallow trench separator structure for electrically separating a plurality of semiconductor devices from a silicon substrate, the chemical dry etching surface having a predetermined width formed on a surface of the silicon substrate, and It has a width smaller than the width of the chemical dry etching surface, and comprises a trench etched to a predetermined depth, and an insulating film grown by a predetermined thickness from the inside of the trench to the top.

또한, 상기한 목적을 달성하기 위해 본 발명에 의한 반도체 소자의 샐로우 트렌치 분리막 제조 방법은 실리콘 서브스트레이트 위에 순차적으로 실리콘 산화막, 실리콘 질화막 및 TEOS(Tetra Ethyl Ortho Silicate)를 형성하고, 상기 TEOS 위에 포토 패턴을 형성하는 단계와, 상기 포토 패턴을 마스크로 하여, 상기 실리콘 서브스트레이트의 표면이 노출될 때까지, 상기 TEOS, 질화막 및 산화막을 일정 영역만큼 에칭하여 일정 크기의 에칭홀을 형성하는 단계와, 상기 노출된 실리콘 서브스트레이트의 표면에 화학적 드라이 에칭을 수행하여, 상기 실리콘 서브스트레이트의 표면 결함을 제거하는 단계와, 상기 노출된 실리콘 서브스트레이트 및 그 주변에 일정 두께의 스페이서 TEOS를 더 형성하는 단계와, 상기 에칭홀의 크기보다 작은 크기를 갖도록 상기 스페이서 TEOS를 에칭하여, 상기 실리콘 서브스트레이트의 표면이 노출되도록 하는 단계와, 상기 스페이서 TEOS를 마스크로 하여, 상기 실리콘 서브스트레이트를 일정 깊이까지 에칭하여 트렌치를 형성하는 단계와, 상기 트렌치의 내측에 절연막을 성장시켜 소자 분리 영역을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In addition, in order to achieve the above object, the method of manufacturing a shallow trench separator of a semiconductor device according to the present invention sequentially forms a silicon oxide film, a silicon nitride film, and TEOS (Tetra Ethyl Ortho Silicate) on a silicon substrate, and then forms a photo on the TEOS. Forming a pattern, etching the TEOS, nitride film, and oxide film by a predetermined area until the surface of the silicon substrate is exposed using the photo pattern as a mask to form etching holes having a predetermined size; Performing chemical dry etching on the exposed silicon substrate surface to remove surface defects of the silicon substrate, further forming a spacer TEOS of a predetermined thickness around the exposed silicon substrate and its surroundings; The spacer TEOS may have a size smaller than that of the etching hole. Etching to expose the surface of the silicon substrate; etching the silicon substrate to a predetermined depth using the spacer TEOS as a mask; forming a trench; growing an insulating film inside the trench; And forming a device isolation region.

여기서, 상기 화학적 드라이 에칭 단계는 압력 30~40Pa, 파워 300~600watt, 유량 40~100sccm의 CF4, 유량 100~300sccm의 O2 조건에서 수행됨이 바람직하다.Here, the chemical dry etching step is preferably performed under pressure conditions of 30 ~ 40Pa, power 300 ~ 600watts, CF 4 of the flow rate 40 ~ 100sccm, O 2 of the flow rate 100 ~ 300sccm.

상기와 같이 하여 본 발명에 의한 반도체 소자의 샐로우 트렌치 분리막 구조 및 그 제조 방법에 의하면, 반도체 소자의 트렌치를 스페이서 TEOS 증착후 블랑켓(blanket) 에칭을 통해 수행함으로써, 원하는 사이즈의 트렌치를 쉽게 구현할 수 있는 장점이 있다.According to the shallow trench separator structure of the semiconductor device and the method for manufacturing the same according to the present invention as described above, a trench of a desired size can be easily implemented by performing a trench etching of the semiconductor device after spacer TEOS deposition. There are advantages to it.

또한, 트렌치의 임계 칫수를 작게 하여 소자 집적도를 향상시킴은 물론, 트렌치의 사이즈가 작음으로써, 절연막의 보이드도 억제할 수 있는 장점이 있다.In addition, the critical dimension of the trench is reduced to improve the device integration degree, and the size of the trench is small, and thus the void of the insulating film can be suppressed.

이하 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art may easily implement the present invention.

도1을 참조하면, 본 발명에 의한 반도체 소자의 샐로우 트렌치 분리막 구조가 도시되어 있다.Referring to Fig. 1, a shallow trench isolation structure of a semiconductor device according to the present invention is shown.

도시된 바와 같이 표면에 각종 반도체 소자가 제조 되는 실리콘 서브스트레이트(2)가 구비되어 있고, 상기 실리콘 서브스트레이트(2)의 표면에는 일정 폭의 화학적 드라이 에칭면(11)이 형성되어 있다. 이러한 화학적 드라이 에칭면(11)은 실리콘 서브스트레이트(2)의 표면 결함을 제거하기 위해 수행된 화학적 드라이 에칭에 의해 수행된 것이며, 이러한 화학적 드라이 에칭면(11)은 통상 종래의 트렌치크기와 유사한 크기를 갖는다. 이어서, 상기 화학적 드라이 에칭면(11)의 폭보다는 작은 폭을 가지며, 일정 깊이를 갖는 트렌치(14)가 에칭되어 형성되어 있다. 또한, 상기 트렌치(14)에는 실제 반도체 소자를 절연시키기 위한 절연막(16)이 일정두께로 성장되어 있다.As shown in the drawing, a silicon substrate 2 on which various semiconductor devices are manufactured is provided, and a chemical dry etching surface 11 having a predetermined width is formed on the surface of the silicon substrate 2. This chemical dry etching surface 11 is performed by chemical dry etching performed to remove surface defects of the silicon substrate 2, and this chemical dry etching surface 11 is usually similar in size to a conventional trench size. Has Subsequently, a trench 14 having a width smaller than that of the chemical dry etching surface 11 and having a predetermined depth is etched and formed. In the trench 14, an insulating film 16 for insulating an actual semiconductor device is grown to a predetermined thickness.

이와 같이 하여, 본 발명에 의한 샐로우 트렌치 분리막 구조는 종래에 비해 그 폭이 대폭 축소 형성됨으로써, 그만큼 반도체 소자의 집적도를 향상시킬 수 있고, 또한 절연막의 형성시 보이드 형성도 억제할 수 있게 된다.In this way, the width of the shallow trench isolation film structure according to the present invention is significantly reduced compared to the conventional one, whereby the degree of integration of the semiconductor element can be improved, and void formation can be suppressed when the insulating film is formed.

도2a 내지 도2g를 참조하면, 본 발명에 의한 반도체 소자의 샐로우 트렌치 분리막 제조 방법이 도시되어 있다.2A to 2G, a method of manufacturing a shallow trench separator of a semiconductor device according to the present invention is shown.

먼저, 도2a에 도시된 바와 같이, 다수의 반도체 소자가 형성되는 실리콘 서브스트레이트(2) 위에 순차적으로 실리콘 산화막(4), 실리콘 질화막(6) 및 TEOS(8)(Tetra Ethyl Ortho Silicate)를 형성하고, 상기 TEOS(8) 위에는 소자 분리를 위한 포토 패턴(10)을 형성한다.First, as shown in FIG. 2A, a silicon oxide film 4, a silicon nitride film 6, and a TEOS 8 (Tetra Ethyl Ortho Silicate) are sequentially formed on a silicon substrate 2 on which a plurality of semiconductor devices are formed. In addition, a photo pattern 10 for device isolation is formed on the TEOS 8.

이어서, 도2b에 도시된 바와 같이, 상기 포토 패턴(10)을 마스크로 하여, 상기 실리콘 서브스트레이트(2)의 표면이 노출될 때까지, 상기 TEOS(8), 질화막(6) 및 산화막(4)을 일정 영역만큼 에칭하여 일정 크기의 에칭홀(13)을 형성한다.Subsequently, as shown in FIG. 2B, using the photo pattern 10 as a mask, the TEOS 8, the nitride film 6 and the oxide film 4 until the surface of the silicon substrate 2 is exposed. ) Is etched by a predetermined area to form an etching hole 13 of a predetermined size.

이어서, 도2c에 도시된 바와 같이 상기 에칭홀(13)을 통하여 노출된 실리콘 서브스트레이트(2)의 표면에 화학적 드라이 에칭(CDE; Chemical Dry Etching)을 수행하여, 상기 실리콘 서브스트레이트(2)의 표면 결함을 제거한다. 도면중 미설명부호 11은 상기 에칭에 의해 형성된 화학적 드라이 에칭면이다.Subsequently, as shown in FIG. 2C, chemical dry etching (CDE) is performed on the surface of the silicon substrate 2 exposed through the etching hole 13, thereby removing the silicon substrate 2. Remove surface defects. Reference numeral 11 in the drawings is a chemical dry etching surface formed by the above etching.

이어서, 도2d에 도시된 바와 같이, 상기 노출된 실리콘 서브스트레이트(2) 및 그 주변의 TEOS(8) 위에 일정 두께의 스페이서 TEOS(12)를 더 형성한다.Subsequently, as shown in FIG. 2D, a spacer TEOS 12 of a certain thickness is further formed on the exposed silicon substrate 2 and the surrounding TEOS 8.

이어서, 도2e에 도시된 바와 같이, 상기 에칭홀(13) 즉, 에칭면(11)의 폭보다 작은 폭을 갖도록 상기 스페이서 TEOS(12)를 에칭하여, 상기 실리콘 서브스트레이트(2)의 표면이 직접 노출되도록 한다.Subsequently, as shown in FIG. 2E, the spacer TEOS 12 is etched to have a width smaller than that of the etching hole 13, that is, the etching surface 11, so that the surface of the silicon substrate 2 is etched. Allow direct exposure.

이어서, 도2f에 도시된 바와 같이, 상기 스페이서 TEOS(12)를 마스크로 하여, 상기 실리콘 서브스트레이트(2)를 일정 깊이까지 에칭하여 트렌치(14)를 형성한다.Next, as shown in FIG. 2F, the silicon substrate 2 is etched to a predetermined depth using the spacer TEOS 12 as a mask to form the trench 14.

이어서, 도2g에 도시된 바와 같이, 상기 트렌치(14)의 내측에 절연막(16)을 성장시켜, 각종 반도체 소자가 전기적으로 분리될 수 있도록 함으로써, 본 발명에 의한 반도체 소자의 샐로우 트렌치 분리막 제조 공정을 완료한다. 여기서, 상기 트렌치(14)의 폭은 종래에 비해 대폭 축소됨으로써, 상기 절연막(16)의 성장시 종래와 같은 보이드는 발생하지 않게 된다.Subsequently, as shown in FIG. 2G, the insulating trench 16 is grown inside the trench 14 to allow various semiconductor devices to be electrically separated, thereby manufacturing a shallow trench separator of the semiconductor device according to the present invention. Complete the process. Here, the width of the trench 14 is significantly reduced compared to the conventional, so that voids as in the prior art do not occur when the insulating layer 16 is grown.

따라서, 본 발명에 의한 반도체 소자의 샐로우 트렌치 분리막 구조 및 그 제조 방법에 의하면, 반도체 소자의 트렌치를 스페이서 TEOS 증착후 블랑켓(blanket) 에칭을 통해 수행함으로써, 원하는 사이즈의 트렌치를 쉽게 구현할 수 있는 효과가 있다.Accordingly, according to the shallow trench isolation structure of the semiconductor device and the method of manufacturing the same, the trench of the semiconductor device may be easily etched by performing blanket blanket etching after deposition of the spacer TEOS, thereby easily implementing a trench of a desired size. It works.

또한, 트렌치의 임계 칫수를 작게 하여 소자 집적도를 향상시킴은 물론, 트렌치의 사이즈가 작음으로써, 절연막의 보이드도 억제할 수 있는 효과가 있다.In addition, the critical dimension of the trench is reduced to improve the device integration degree, and the size of the trench is small, so that the void of the insulating film can be suppressed.

이상에서 설명한 것은 본 발명에 따른 반도체 소자의 샐로우 트렌치 분리막 구조 및 그 제조 방법을 실시하기 위한 하나의 실시예에 불과한 것으로서, 본 발명은 상기한 실시예에 한정되지 않고, 이하의 특허청구범위에서 청구하는 바와같이 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자가라면 누구든지 다양한 변경 실시가 가능한 범위까지 본 발명의 기술적 정신이 있다고 할 것이다.What has been described above is just one embodiment for carrying out the structure of the shallow trench isolation structure and the manufacturing method of the semiconductor device according to the present invention, the present invention is not limited to the above-described embodiment, in the claims As claimed, any person having ordinary skill in the art without departing from the gist of the present invention will have the technical spirit of the present invention to the extent that various modifications can be made.

Claims (3)

실리콘 서브스트레이트에서 다수의 반도체 소자를 전기적으로 분리하기 위한 샐로우 트렌치 분리막 구조에 있어서,In a shallow trench separator structure for electrically separating a plurality of semiconductor devices from a silicon substrate, 상기 실리콘 서브스트레이트의 표면에 형성된 일정 폭의 화학적 드라이 에칭면;A chemical dry etching surface having a predetermined width formed on a surface of the silicon substrate; 상기 화학적 드라이 에칭면의 폭보다 작은 폭를 가지며, 일정 깊이로 에칭된 트렌치; 및,A trench having a width smaller than that of the chemical dry etching surface and etched to a predetermined depth; And, 상기 트렌치 내측에서 상부로 일정 두께만큼 성장된 절연막을 포함하여 이루어진 반도체 소자의 샐로우 트렌치 분리막 구조.A shallow trench isolation structure of a semiconductor device including an insulating film grown from the inside of the trench by a predetermined thickness. 실리콘 서브스트레이트 위에 순차적으로 실리콘 산화막, 실리콘 질화막 및 TEOS(Tetra Ethyl Ortho Silicate)를 형성하고, 상기 TEOS 위에 포토 패턴을 형성하는 단계;Sequentially forming a silicon oxide film, a silicon nitride film and a tetra ethyl ortho silicate (TEOS) on the silicon substrate, and forming a photo pattern on the TEOS; 상기 포토 패턴을 마스크로 하여, 상기 실리콘 서브스트레이트의 표면이 노출될 때까지, 상기 TEOS, 질화막 및 산화막을 일정 영역만큼 에칭하여 일정 크기의 에칭홀을 형성하는 단계;Etching the TEOS, the nitride film, and the oxide film by a predetermined area until the surface of the silicon substrate is exposed using the photo pattern as a mask to form etching holes having a predetermined size; 상기 노출된 실리콘 서브스트레이트의 표면에 화학적 드라이 에칭을 수행하여, 상기 실리콘 서브스트레이트의 표면 결함을 제거하는 단계;Performing a chemical dry etch on the surface of the exposed silicon substrate to remove surface defects of the silicon substrate; 상기 노출된 실리콘 서브스트레이트 및 그 주변에 일정 두께의 스페이서TEOS를 더 형성하는 단계;Forming a spacer TEOS of a predetermined thickness around the exposed silicon substrate and its surroundings; 상기 에칭홀의 크기보다 작은 크기를 갖도록 상기 스페이서 TEOS를 에칭하여, 상기 실리콘 서브스트레이트의 표면이 노출되도록 하는 단계;Etching the spacer TEOS to have a size smaller than the size of the etching hole, so that the surface of the silicon substrate is exposed; 상기 스페이서 TEOS를 마스크로 하여, 상기 실리콘 서브스트레이트를 일정 깊이까지 에칭하여 트렌치를 형성하는 단계; 및,Etching the silicon substrate to a predetermined depth using the spacer TEOS as a mask to form a trench; And, 상기 트렌치의 내측에 절연막을 성장시켜 소자 분리 영역을 형성하는 단계를 포함하여 이루어진 반도체 소자의 샐로우 트렌치 분리막 제조 방법.And forming an isolation region by growing an insulating layer inside the trench. 제2항에 있어서, 상기 화학적 드라이 에칭 단계는 압력 30~40Pa, 파워 300~600watt, 유량 40~100sccm의 CF4, 유량 100~300sccm의 O2 조건에서 수행됨을 특징으로 하는 반도체 소자의 샐로우 트렌치 분리막 제조 방법.3. The method of claim 2, wherein the chemical dry etching step is performed at a pressure of 30 to 40 Pa, a power of 300 to 600 watts, CF 4 at a flow rate of 40 to 100 sccm, and O 2 at a flow rate of 100 to 300 sccm. Way.
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