KR20040057754A - Method of driving plasma display panel with pause period - Google Patents

Abstract

PURPOSE: A method for driving a plasma display panel with a pause period is provided to reduce the high frequency noise of the circuit device due to the vibration of the top and bottom plate of the plasma display panel generated during the discharge. CONSTITUTION: A method for driving a plasma display panel with a pause period is characterized in that the pause period(PPk,PPk+1) is assigned to at least one of the sub-fields(SFk,SFk+1). The plasma display panel is driven by time-sharing driving with a time-sharing driving method using a plurality of sub-fields(SFk,SFk+1). One frame is divided into the plurality of the sub-fields(SFk,SFk+1). Each of the sub-fields(SFk,SFk+1) includes a reset period(RST), an address period(ADDR) and a sustain period(SUSTk,SUSTk+1).

Description

A method of driving a plasma display panel having a rest period {METHOD OF DRIVING PLASMA DISPLAY PANEL WITH PAUSE PERIOD}

The present invention relates to a plasma display panel, and more particularly, to a method of driving a plasma display panel to reduce noise.

Plasma Display Panel (hereinafter referred to as "PDP") is used to excite and emit phosphors by using ultraviolet rays generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is discharged. Will be displayed. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a three-electrode alternating surface discharge type PDP includes a sustain electrode pair including a scan electrode (Y) and a sustain electrode (Z) formed on the upper substrate 1, and a lower portion perpendicular to the sustain electrode pair. An address electrode X formed on the substrate 2 is provided. Each of the scan electrode Y and the sustain electrode Z is composed of a transparent electrode and a metal bus electrode formed thereon. The upper dielectric layer 6 and the MgO protective layer 7 are stacked on the upper substrate 1 on which the scan electrode Y and the sustain electrode Z are formed. The lower dielectric layer 4 is formed on the lower substrate 2 on which the address electrode X is formed to cover the address electrode X. FIG. A partition 3 is formed vertically on the lower dielectric layer 4. Phosphors 5 are formed on the surfaces of the lower dielectric layers 4 and the partition walls 3. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is injected into the discharge space provided between the upper substrate 1, the lower substrate 2, and the partition wall 3. The upper substrate 1 and the lower substrate 2 are bonded by a real material not shown.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period (or a reset period) for initializing the full screen, an address period for selecting a scan line and a cell in the selected scan line, and a sustain period for implementing gradation according to the number of discharges. . The initialization period is divided into a setup period in which the rising ramp waveform is supplied and a set down period in which the falling ramp waveform is supplied. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2,3,4,5,6) in each subfield. , 7).

FIG. 3 shows driving waveforms supplied to the PDP during two subfield periods in one frame arrangement shown in FIG.

Referring to FIG. 3, each subfield SFk, SFk + 1 includes a reset period RST for uniformly initializing discharge conditions in a cell for all cells of the PDP, an address period ADDR for selecting a cell, and The driving is performed by dividing the sustain periods (SUSTk and SUSTk + 1) to maintain the discharge of the selected cell.

During the reset period RST, the rising ramp waveform Ramp-up is supplied to all the scan electrodes Y simultaneously. Following the rising ramp waveform Ramp-up, a falling ramp waveform Ramp-down falling at a positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes Y simultaneously. Immediately after the rising ramp waveform and the falling ramp waveform are supplied, wall charges such that address discharge can stably occur in each cell remain uniformly in the cells. This reset period RST is the same for each subfield SFk, SFk + 1.

In the address period ADDR, the negative scan pulse scan is sequentially supplied to the scan electrodes Y, and the data pulse data is supplied to the address electrodes X in synchronization with the scan pulse scan. The scan pulse selects a horizontal line to which data is supplied, and the data pulse selects a discharge cell by causing an address discharge in a desired cell in the selected horizontal line. In the cells selected by the address discharge, wall charges are formed so that a discharge can occur when a sustain voltage is applied as a result of the address discharge. This address period ADDR is the same for each subfield SFk, SFk + 1.

During the period in which the falling ramp waveform Ramp-down is supplied to the scan electrode Y and the address period ADDR, the sustain electrode Z is supplied with a positive DC voltage Zdc.

In the sustain periods SUSTk and SUSTk + 1, a sustain pulse su is applied to the scan electrodes Y and the sustain electrodes Z alternately. Whenever a stain pulse (sus) is applied, a sustain discharge, that is, a display discharge occurs between the scan electrode (Y) and the sustain electrode (Z). At the end of the sustain period, the sustain electrode Z is supplied with an erase signal ers in the form of a ramp signal. The erase signal ers erases wall charges generated in the cell by the sustain discharge. Since the number of sustain pulses su is assigned differently when the luminance weights given to the subfields SFk and k + 1 are set differently, the sustain periods SSUSk and SSTk + 1 are assigned to the subfields SFk, In SFk + 1). For example, as shown in FIG. 3, k is the total number of subfields-a positive integer equal to or less than 1, and the sustain period SUSTk of the th subfield SFk is smaller than the k + 1 th subfield SFk + 1. The period becomes small.

However, in the conventional PDP, noise is generated as the upper and lower plates shake with each discharge. In addition, a conventional PDP is a flexible printed circuit for connecting a circuit element or a printed circuit board (PCB) and electrode lines on the PDP when a current generated during discharge flows into each circuit element. Circuit: FPC) is shaking and noise is generated. In particular, the high frequency noise in the 4KHz to 8KHz frequency range among the noise generated in the conventional PDP is very annoying to the human ear. Such high frequency noise is generated by driving high luminance weighted subfields in which a relatively large number of sustain pulses is allocated when displaying a bright screen. In particular, when displaying bright screens, high frequency noise is severely generated when displaying bright screens because the interval between the driven subfields is narrowed and a large number of discharges are concentrated in a short period of time.

Accordingly, it is an object of the present invention to provide a method of driving a PDP to reduce noise.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram illustrating a frame configuration of an 8-bit default code for implementing 256 gray levels.

3 is a waveform diagram showing driving waveforms for driving a conventional plasma display panel.

4 is a waveform diagram illustrating a method of driving a plasma display panel having a pause period according to a first embodiment of the present invention.

5 is a waveform diagram illustrating a method of driving a plasma display panel having a pause period according to a second embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

1: upper substrate 2: lower substrate

3: bulkhead 4,6: dielectric layer

5: phosphor 7: protective layer

X: address electrode Y: scan electrode

Z: sustain electrode

In order to achieve the above object, the driving method of the PDP according to the embodiment of the present invention allocates a rest period to at least one of the subfields.

In the idle period, the driving signal is not applied to the PDP.

The idle period is characterized in that the period is allocated differently for each of the subfields.

The idle period is characterized in that it is allocated between the sustain period and the reset period.

The PDP driving method according to another embodiment of the present invention sets the address period differently in the subfields.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 and 5.

Referring to FIG. 4, the PDP driving method according to the first embodiment of the present invention divides one frame period into a plurality of subfields for time division driving, and performs a pause period in at least one subfield of each subfield. PPk, PPk + 1) is set to make the periods of the respective subfields the same.

Assuming two subfields SFk and SFk + 1 as shown in FIG. 4, each of the subfields SFk and SFk + 1 is a reset for uniformly initializing discharge conditions within a cell for all cells of the PDP. The period RST, the address period ADDR for selecting a cell, the sustain periods SUSTk and SUSTk + 1 for maintaining the discharge of the selected cell, and the period of each subfield SFk and SFk + 1 are made equal. It is driven by dividing by the idle period (PPk, PPk + 1).

During the reset period RST, the rising ramp waveform Ramp-up is supplied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a discharge in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. Following the rising ramp waveform Ramp-up, a falling ramp waveform Ramp-down falling at a positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes Y simultaneously. Ramp-down causes a slight erase discharge in the cells, thereby partially erasing the excessively formed wall charge. By this set-down discharge, the wall charges such that the address discharge can be stably generated remain uniformly in the cells. This reset period RST is the same for each subfield SFk, SFk + 1.

In the address period ADDR, negative scan pulses are sequentially supplied to the scan electrodes Y, and data pulses are supplied to the address electrodes X in synchronization with the scan pulses. . As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the reset period RST are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed so that a discharge can occur when a sustain voltage is applied as a result of the address discharge. This address period ADDR is the same for each subfield SFk, SFk + 1.

The positive DC voltage Zdc is supplied to the sustain electrode Z during the period in which the falling ramp waveform Ramp-down is supplied to the scan electrode Y and the address period ADDR.

In the sustain periods SUSTk and SUSTk + 1, a sustain pulse su is applied to the scan electrodes Y and the sustain electrodes Z alternately. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. This will happen. At the end of the sustain period, the sustain electrode Z is supplied with an erase signal ers in the form of a ramp signal. The erase signal ers erases wall charges generated in the cell by the sustain discharge. Since the number of sustain pulses su is assigned differently when the luminance weights given to the subfields SFk and k + 1 are set differently, the sustain periods SSUSk and SSTk + 1 are assigned to the subfields SFk, In SFk + 1). For example, as shown in FIG. 3, k is the total number of subfields-a positive integer equal to or less than 1, and the sustain period SUSTk of the th subfield SFk is smaller than the k + 1 th subfield SFk + 1. The period becomes small.

The idle period (PPk, PPk + 1) is assigned a relatively long time to the subfield SFk allocated for a short time, while a short time is allocated for the subfield SFk + 1 allocated for a long time. do. By the idle period PPk and PPk + 1, the periods of the respective subfields SFk and SFk + 1 become equal, and as a result, the sustain discharge is dispersed and the interval between the subfields becomes long, so that the brightness of the screen is increased. Regardless of noise, especially high frequency noise is attenuated.

On the other hand, the idle periods PPk and PPk + 1 are allocated between the sustain periods SUSTk and SUSTk + 1 and the reset period RST in FIG. 3, but are between the reset period RST and the address period ADDR or the address period. It may be arranged between ADDR and the sustain periods SUSTk and SUSTk + 1.

5 is a waveform diagram illustrating a method of driving a PDP according to a second embodiment of the present invention.

Referring to FIG. 5, the PDP driving method according to the second embodiment of the present invention divides one frame period into a plurality of subfields for time division driving, and assigns address periods ADDRk and ADDRk to each of the subfields. By setting +1) differently, the periods of the respective subfields are equal.

Assuming two subfields SFk and SFk + 1 as shown in FIG. 5, each of the subfields SFk and SFk + 1 is a reset for uniformly initializing discharge conditions within a cell for all cells of the PDP. Period RST, address period ADDRk, ADDRk + 1 and the selected cell that are differently set for each subfield SFk, SFk + 1 such that the cell is selected and the period of each of the subfields SFk, SFk + 1 is the same. The driving is performed by dividing the sustain periods (SUSTk and SUSTk + 1) to maintain the discharge.

During the reset period RST, the rising ramp waveform Ramp-up is supplied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a discharge in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. Following the rising ramp waveform Ramp-up, a falling ramp waveform Ramp-down falling at a positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes Y simultaneously. Ramp-down causes a slight erase discharge in the cells, thereby partially erasing the excessively formed wall charge. By this set-down discharge, the wall charges such that the address discharge can be stably generated remain uniformly in the cells. This reset period RST is the same for each subfield SFk, SFk + 1.

In the address period ADDRk and ADk + 1, the negative scan pulse scan is sequentially supplied to the scan electrodes Y, and the data pulse data is applied to the address electrodes X in synchronization with the scan pulse scan. ) Is supplied. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the reset period RST are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed so that a discharge can occur when a sustain voltage is applied as a result of the address discharge. This address period ADDR is the same for each subfield SFk, SFk + 1.

The address periods ADDRk and ADDRk + 1 are allocated to the subfield SFk allocated for a short time and have a relatively long time, whereas those address periods ADDRk and ADDRk + 1 have a short time for the subfield SFk + 1 assigned to a long time. Is assigned. By this address period ADDRk and ADDRk + 1, the periods of the respective subfields SFk and SFk + 1 become the same, and as a result, the sustain discharge is dispersed and the interval between the subfields becomes long, so that the noise is reduced. .

The positive DC voltage Zdc is supplied to the sustain electrode Z during the period in which the falling ramp waveform Ramp-down is supplied to the scan electrode Y and the address period ADDR.

In the sustain periods SUSTk and SUSTk + 1, a sustain pulse su is applied to the scan electrodes Y and the sustain electrodes Z alternately. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. This will happen. At the end of the sustain period, the sustain electrode Z is supplied with an erase signal ers in the form of a ramp signal. The erase signal ers erases wall charges generated in the cell by the sustain discharge. Since the number of sustain pulses su is assigned differently when the luminance weights given to the subfields SFk and k + 1 are set differently, the sustain periods SSUSk and SSTk + 1 are assigned to the subfields SFk, In SFk + 1). For example, as shown in FIG. 3, k is the total number of subfields-a positive integer equal to or less than 1, and the sustain period SUSTk of the th subfield SFk is smaller than the k + 1 th subfield SFk + 1. The period becomes small.

Meanwhile, the address periods ADDRk and ADDRk may be set differently in the subfields SFk and SFk + 1 as shown in FIG. 5 so that the periods of the respective subfields SFk and SFk + 1 are the same. The reset period RST or the sustain periods SUSTk and SUSTk + 1 may be set differently.

As described above, the PDP driving method according to the present invention equalizes the interval between the subfields and the subfields by allocating an idle period between subfields or differently assigning an address period for each subfield. Therefore, according to the driving method of the PDP according to the present invention, since the period of the subfields and the interval between the subfields are the same, the noise caused by the shaking of the upper and lower plates of the PDP generated during discharge or the noise of the circuit element due to the discharge current In particular, high frequency noise can be reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (5)

A method of driving a plasma display panel in which time division driving is performed by dividing one frame period into a plurality of subfields each including a reset period, an address period, and a sustain period. And a rest period allocated to at least one of the subfields. The method of claim 1, And a driving signal is not applied to the plasma display panel during the idle period. The method of claim 2, And wherein the idle period is allocated differently for each of the subfields. The method of claim 2, And said rest period is allocated between said sustain period and a reset period. A method of driving a plasma display panel in which time division driving is performed by dividing one frame period into a plurality of subfields each including a reset period, an address period, and a sustain period. And the address period is different in the subfields.