KR20040055164A - method for forming landing plug contact - Google Patents
method for forming landing plug contact Download PDFInfo
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- KR20040055164A KR20040055164A KR1020020081781A KR20020081781A KR20040055164A KR 20040055164 A KR20040055164 A KR 20040055164A KR 1020020081781 A KR1020020081781 A KR 1020020081781A KR 20020081781 A KR20020081781 A KR 20020081781A KR 20040055164 A KR20040055164 A KR 20040055164A
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- gate electrode
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- landing plug
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 238000009413 insulation Methods 0.000 claims abstract description 5
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 4
- 238000001039 wet etching Methods 0.000 claims description 10
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 11
- 239000010410 layer Substances 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 구체적으로는 랜딩 플러그용 콘택영역을 안정적으로 확보할 수 있는 랜딩 플러그용 콘택 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a landing plug contact capable of stably securing a landing plug contact region.
도 1은 종래 기술에 따른 랜딩 플러그용 콘택 형성 방법을 설명하기 위한 공정단면도이다.1 is a cross-sectional view illustrating a method for forming a contact for a landing plug according to the related art.
종래 기술에 따른 랜딩 플러그용 콘택 형성 방법은, 도 1에 도시된 바와 같이, 필드격리막(3)이 구비된 반도체기판(1)을 제공한다. 이어, 상기 기판에 실리콘 산화막, 제 1다결정 실리콘막, 금속 실리사이드막 및 제 1실리콘 질화막을 차례로 형성한 후, 포토리쏘그라피 공정에 의해 상기 막들을 식각하여 각각의 게이트 산화막(5) 및 게이트 전극 패턴(7)을 형성한다. 이때, 상기 게이트 전극 패턴(7)은 제 1다결정 실리콘막, 금속 실리사이드막 및 제 1실리콘 질화막의 3중 적층 구조를 가진다.The contact forming method for a landing plug according to the prior art, as shown in FIG. 1, provides a semiconductor substrate 1 having a field isolation film 3. Subsequently, a silicon oxide film, a first polycrystalline silicon film, a metal silicide film, and a first silicon nitride film are sequentially formed on the substrate, and then the films are etched by a photolithography process to form the gate oxide film 5 and the gate electrode pattern. (7) is formed. In this case, the gate electrode pattern 7 has a triple stacked structure of a first polycrystalline silicon film, a metal silicide film, and a first silicon nitride film.
그런 다음, 상기 게이트 전극 패턴(7)을 마스크로 하고 상기 기판 전면에 불순물을 주입하여 소오스/드레인영역(9)을 형성한다.Then, the source / drain region 9 is formed by implanting impurities into the entire surface of the substrate using the gate electrode pattern 7 as a mask.
이 후, 상기 구조 전면에 제 2실리콘 질화막(미도시) 및 층간절연막(13)을 차례로 형성하고 나서, 랜딩플러그용 콘택영역이 정의된 감광막 패턴(미도시)을 이용하여 상기 층간절연막 및 제 2실리콘 질화막을 식각하여 랜딩 플러그용 콘택(14)을 형성한다. 이때, 상기 식각 공정을 통해, 상기 제 2실리콘 질화막은 게이트 전극 패턴(14)의 측면에 절연 스페이서(11)가 되며, 상기 절연 스페이서(11)는 랜딩 플러그용 콘택(14)과 게이트 전극 패턴(7)이 쇼트되는 것을 방지하는 역할을 한다.Thereafter, a second silicon nitride film (not shown) and an interlayer insulating film 13 are sequentially formed on the entire structure, and then the interlayer insulating film and the second insulating film are formed using a photosensitive film pattern (not shown) in which a contact area for landing plug is defined. The silicon nitride film is etched to form a landing plug contact 14. At this time, through the etching process, the second silicon nitride layer becomes the insulating spacer 11 on the side of the gate electrode pattern 14, and the insulating spacer 11 is the landing plug contact 14 and the gate electrode pattern ( 7) prevents short circuit.
이어, 상기 랜딩 플러그용 콘택(14)을 포함한 기판 전면에 제 2다결정 실리콘막(미도시)을 형성한 후, 상기 게이트 전극 패턴(7) 표면이 노출되는 시점까지 상기 제 2다결정 실리콘막 및 층간절연막을 씨엠피(Chemical Mechnical Polishing:CMP)하여 랜딩 플러그용 콘택(14)을 매립시키는 랜딩 플러그(15)를 형성한다.Subsequently, after forming a second polycrystalline silicon film (not shown) on the entire surface of the substrate including the landing plug contact 14, the second polycrystalline silicon film and the interlayer are formed until the surface of the gate electrode pattern 7 is exposed. The insulating film is subjected to chemical mechanical polishing (CMP) to form a landing plug 15 for embedding the landing plug contact 14.
그러나, 종래의 기술에서는 랜딩 플러그용 콘택영역을 오픈시키기 위한 감광막 패턴이 하위층과 오정렬되면 랜딩 플러그용 콘택의 오픈 면적이 감소하여 콘택 저항이 증가하였다.However, in the related art, when the photoresist pattern for opening the landing plug contact region is misaligned with the lower layer, the open area of the landing plug contact decreases and the contact resistance increases.
또한, 게이트 전극 패턴과 랜딩 플러그용 콘택 사이의 절연 스페이서가 유전율이 높은 질화막으로 형성함으로써, 커플링 노이즈(coupling noise)가 심하게 발생되는 문제점이 있었다.In addition, since the insulating spacer between the gate electrode pattern and the landing plug contact is formed of a nitride film having a high dielectric constant, there is a problem in that coupling noise is severely generated.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 랜딩플러그용 콘택영역을 안정적으로 오픈시킬 수 있는 랜딩 플러그용 콘택 형성 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a landing plug contact forming method capable of stably opening a landing plug contact region.
도 1은 종래 기술에 따른 랜딩 플러그용 콘택 형성 방법을 설명하기 위한 공정단면도.1 is a cross-sectional view illustrating a method for forming a contact for a landing plug according to the related art.
도 2a 내지 도 2f는 본 발명에 따른 랜딩 플러그용 콘택 형성 방법을 설명하기 위한 공정단면도.2A to 2F are cross-sectional views illustrating a method for forming a contact for a landing plug according to the present invention;
상기 목적을 달성하기 위한 본 발명에 따른 랜딩 플러그용 콘택 형성 방법은 반도체기판 상에 다결정 실리콘막, 텅스텐 실리사이드막 및 질화막의 3중 적층 구조를 가진 게이트 전극을 형성하는 단계와, 게이트 전극을 마스크로 하여 상기 기판 전면에 불순물을 주입하여 소오스/드레인영역을 형성하는 단계와, 소오스/드레인영역을 포함한 기판 상에 게이트 전극 패턴의 질화막을 노출시키는 산화막을 형성하는 단계와, 상기 결과의 기판 상에 랜딩플러그용 콘택영역을 덮는 감광막 패턴을 형성하는 단계와, 감광막 패턴을 마스크로 하고 상기 산화막을 소정 두께로 식각하는 단계와, 감광막 패턴을 제거하는 단계와, 게이트 전극 패턴의 최상단인 질화막을 습식 식각하는 단계와, 산화막을 습식 식각하여 게이트 전극 패턴의 폭보다 넓은 골을 형성하는 단계와, 골을 매립시키는 절연 패턴을 형성하는 단계와, 절연 패턴을 마스크로 하여 산화막을 식각하여 소오스/드레인영역을 노출시키는 각각의 랜딩플러그용 콘택을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of forming a contact for a landing plug according to the present invention includes forming a gate electrode having a triple stacked structure of a polycrystalline silicon film, a tungsten silicide film, and a nitride film on a semiconductor substrate, and using the gate electrode as a mask. Implanting impurities into the entire surface of the substrate to form a source / drain region, forming an oxide film exposing a nitride film of a gate electrode pattern on the substrate including the source / drain region, and landing on the resulting substrate Forming a photoresist pattern covering the plug contact region, etching the oxide film to a predetermined thickness using the photoresist pattern as a mask, removing the photoresist pattern, and wet etching the nitride film, which is the top of the gate electrode pattern, And wet etching the oxide layer to form a valley wider than the width of the gate electrode pattern. And forming an insulating pattern for filling the valleys, and forming respective landing plug contacts for exposing the source / drain regions by etching the oxide film using the insulating pattern as a mask.
상기 질화막 습식 식각 공정에서, 습식액으로 인산을 이용하는 것이 바람직하다.In the nitride film wet etching process, it is preferable to use phosphoric acid as the wet liquid.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명에 따른 랜딩 플러그용 콘택 형성 방법을 설명하기 위한 공정단면도이다.2A to 2F are cross-sectional views illustrating a method for forming a landing plug contact according to the present invention.
본 발명의 일실시예에 따른 랜딩 플러그용 콘택 형성 방법은, 도 2a에 도시된 바와 같이, 먼저 반도체기판(100) 상에 공지의 STI(Shallow Trench Isolation) 공정에 의해 트렌치(미도시)를 형성하고 나서, 상기 트렌치를 매립시키는 소자격리막(102)을 형성한다. 이어, 상기 소자격리막(102)을 포함한 기판 전면에 실리콘 산화막, 제 1다결정 실리콘막, 텅스텐 실리사이드막 및 제 1실리콘 질화막을 차례로 형성한 다음, 상기 막들을 선택 식각하여 각각의 게이트 산화막(104) 및 3중 적층 구조의 게이트 전극 패턴(106)을 형성한다.In the method for forming a contact for a landing plug according to an embodiment of the present invention, as shown in FIG. 2A, a trench (not shown) is first formed on a semiconductor substrate 100 by a known shallow trench isolation (STI) process. After that, the device isolation film 102 filling the trench is formed. Subsequently, a silicon oxide film, a first polycrystalline silicon film, a tungsten silicide film, and a first silicon nitride film are sequentially formed on the entire surface of the substrate including the device isolation film 102, and then the films are selectively etched to form respective gate oxide films 104 and The gate electrode pattern 106 of the triple stacked structure is formed.
그런 다음, 상기 게이트 전극 패턴(106)을 마스크로 하고 상기 기판 전면에 불순물을 주입하여 소오스/드레인영역(108)을 형성한다.Next, the source / drain region 108 is formed by implanting impurities into the entire surface of the substrate using the gate electrode pattern 106 as a mask.
이 후, 도 2b에 도시된 바와 같이, 상기 소오스/드레인영역(108)을 포함한 기판 전면에 산화막(110)을 형성하고 나서, 게이트 전극 패턴(106)의 최상단인 제 1 실리콘 질화막 표면을 노출시키는 시점까지 상기 산화막을 에치백 또는 씨엠피하여 평탄화한다.Thereafter, as shown in FIG. 2B, an oxide film 110 is formed on the entire surface of the substrate including the source / drain regions 108, and then the surface of the first silicon nitride film, which is the top of the gate electrode pattern 106, is exposed. The oxide film is etched back or CMP planarized until a point in time.
이어, 도 2c에 도시된 바와 같이, 상기 결과물 상에 랜딩플러그용 콘택영역을 덮는 감광막 패턴(120)을 형성하고 나서, 상기 감광막 패턴(120)을 마스크로 하여 상기 산화막(110)을 소정 두께로 식각한다.Subsequently, as shown in FIG. 2C, the photoresist pattern 120 covering the contact area for landing plug is formed on the resultant, and the oxide film 110 is formed to a predetermined thickness using the photoresist pattern 120 as a mask. Etch it.
그런 다음, 도 2d에 도시된 바와 같이, 감광막 패턴을 제거하고 나서, 상기 게이트 전극 패턴(106)의 최상단인 제 1실리콘 질화막을 습식 식각한다. 이때, 상기 습식 식각 공정에서, 습식액으로 인산을 이용한다. 이때, 상기 제 1실리콘 질화막 성분을 습식 식각함으로써, 산화막은 도 2d에 도시된 바와 같은 기복이 형성된다.Then, as shown in FIG. 2D, after removing the photoresist pattern, the first silicon nitride layer, which is the uppermost end of the gate electrode pattern 106, is wet etched. At this time, in the wet etching process, phosphoric acid is used as the wet liquid. At this time, by wet etching the first silicon nitride film component, the oxide film has a relief as shown in Figure 2d.
이 후, 도 2e에 도시된 바와 같이, 상기 산화막을 습식 식각 방법으로 제거함으로서, 게이트 전극 패턴(106)의 제 1다결정 실리콘막을 노출시키는 골(112)을 형성한다. 이때, 도면부호 a는 상기 습식 식각 공정을 통해 산화막이 제거되어 넓어진 폭을 의미한다. 상기 골(112)은 상기 게이트 전극 패턴(106)의 폭(b)보다 2a만큼 크게 형성된다.Thereafter, as shown in FIG. 2E, the oxide film is removed by a wet etching method to form a valley 112 exposing the first polycrystalline silicon film of the gate electrode pattern 106. In this case, reference numeral a denotes a width widened by removing an oxide layer through the wet etching process. The valley 112 is formed to be 2a larger than the width b of the gate electrode pattern 106.
이어, 상기 구조 전면에 제 2실리콘 질화막(미도시)을 형성한 후, 상기 제 2실리콘 질화막을 씨엠피하여 상기 골(112)을 매립시키는 절연 패턴(114)을 형성한다. 이때, 절연 패턴(114)은 이 후의 공정에서 게이트 전극 패턴과 랜딩플러그용 콘택 간의 일정 거리를 확보하는 역할을 한다.Subsequently, after forming a second silicon nitride film (not shown) on the entire structure, the second silicon nitride film is CMP to form an insulating pattern 114 for filling the valleys 112. In this case, the insulating pattern 114 serves to secure a predetermined distance between the gate electrode pattern and the landing plug contact in a subsequent process.
그런 다음, 도 2f에 도시된 바와 같이, 상기 절연 패턴(114)을 마스크로 하여 상기 산화막을 식각하여 소오스/드레인영역(108)을 노출시키는 랜딩플러그용 콘택(116)을 형성한다.Then, as illustrated in FIG. 2F, the landing plug contact 116 exposing the source / drain region 108 is formed by etching the oxide layer using the insulating pattern 114 as a mask.
이 후, 상기 랜딩 플러그용 콘택(116)을 포함한 기판 전면에 제 2다결정 실리콘막(미도시)을 형성한 다음, 상기 제 2다결정 실리콘막을 씨엠피하여 상기 랜딩플러그용 콘택(116)을 매립시키는 랜딩 플러그(118)을 형성한다.Thereafter, a second polycrystalline silicon film (not shown) is formed on the entire surface of the substrate including the landing plug contact 116, and then the second polycrystalline silicon film is CMP so as to fill the landing plug contact 116. The plug 118 is formed.
본 발명에 따르면, 게이트 전극 패턴 측면에 질화막 성분의 절연 스페이서를 형성하는 대신 상기 질화막보다 유전율이 낮은 산화막으로 형성함으로써, 커플링 노이즈가 적게 발생된다.According to the present invention, instead of forming an insulating spacer of a nitride film component on the side of the gate electrode pattern, the coupling noise is generated by forming an oxide film having a lower dielectric constant than the nitride film.
이상에서와 같이, 본 발명은 감광막 패턴을 이용하지 않고 게이트 전극 패턴의 폭보다 넓은 절연 패턴을 이용하여 랜딩 플러그용 콘택을 형성함으로써, 감광막 패턴과의 오정렬에 따른 랜딩플러그용 콘택의 오픈 면적이 감소됨을 방지할 수 있다. 따라서, 랜딩 플러그용 콘택을 안정적으로 확보가능하여 콘택 저항에 의한 불량을 최소화할 수 있다.As described above, the present invention forms a landing plug contact using an insulation pattern wider than the width of the gate electrode pattern without using the photoresist pattern, thereby reducing the open area of the landing plug contact due to misalignment with the photoresist pattern. Can be prevented. Therefore, the landing plug contact can be stably secured, thereby minimizing defects caused by contact resistance.
또한, 본 발명은 랜딩플러그용 콘택과 게이트 전극 패턴 사이에 기존의 질화막 성분의 절연 스페이서보다 유전율이 낮은 산화막이 개재됨으로써, 커플링 노이즈가 적게 발생되는 이점이 있다.In addition, the present invention has an advantage in that coupling noise is generated between the landing plug contact and the gate electrode pattern by having an oxide film having a lower dielectric constant than an insulating spacer of a conventional nitride film component.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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|---|---|---|---|
| KR1020020081781A KR20040055164A (en) | 2002-12-20 | 2002-12-20 | method for forming landing plug contact |
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| KR1020020081781A KR20040055164A (en) | 2002-12-20 | 2002-12-20 | method for forming landing plug contact |
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| KR20040055164A true KR20040055164A (en) | 2004-06-26 |
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