KR20040043643A - method for manufacturing metal line - Google Patents
method for manufacturing metal line Download PDFInfo
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- KR20040043643A KR20040043643A KR1020020072032A KR20020072032A KR20040043643A KR 20040043643 A KR20040043643 A KR 20040043643A KR 1020020072032 A KR1020020072032 A KR 1020020072032A KR 20020072032 A KR20020072032 A KR 20020072032A KR 20040043643 A KR20040043643 A KR 20040043643A
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- al2o3
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- 239000002184 metal Substances 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052593 corundum Inorganic materials 0.000 claims abstract description 15
- 229910001845 yogo sapphire Inorganic materials 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 229910015844 BCl3 Inorganic materials 0.000 claims 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims 1
- 239000011229 interlayer Substances 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 238000001459 lithography Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 구체적으로는 Al금속 배선 구조를 덮는 HDP(High Density Plasma) 방식의 층간절연막을 형성하는 공정에서, 상기 HDP에 의한 식각 데미지(damage)를 감소시킬 수 있는 금속 배선 형성 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, in the process of forming an HDP (High Density Plasma) type interlayer insulating film covering an Al metal wiring structure, the etching damage caused by the HDP is reduced. It relates to a metal wiring forming method that can be.
반도체 소자에서, 특히 비메모리 반도체 제조 공정에서는 하나의 반도체 칩 내에 회로를 집적하여야 하므로, 고집적화되는 현 추세에 맞춰, 다층 배선을 형성해야 한다. 그런데, 디자인 룰이 0.25㎛ 이하로 작아지면서 이러한 다층 배선 기술은 매우 어렵다.In semiconductor devices, particularly in non-memory semiconductor manufacturing processes, circuits must be integrated into one semiconductor chip, and multilayer wiring must be formed in accordance with the current trend of high integration. By the way, such a multilayer wiring technique is very difficult as the design rule becomes smaller than 0.25 mu m.
0.13㎛ 이상의 기술에서 금속막으로 Al막을 사용하며, 상기 Al막 위에 반사방지막으로서 TiN막을 형성하고 나서 상기 Al막 및 TiN막을 식각하여 금속 배선을 형성한다. 이 후, 상기 금속 배선 구조를 덮는 층간 절연막을 형성한다. 이때, 상기 층간절연막으로는 상기 금속 배선 사이의 채움 특성이 양호한 HDP(High Density Plasma)방식의 산화막을 이용한다.An Al film is used as a metal film in a technique of 0.13 µm or more, and a TiN film is formed as an antireflection film on the Al film, and then the Al film and the TiN film are etched to form metal wiring. Thereafter, an interlayer insulating film covering the metal wiring structure is formed. In this case, an HDP (High Density Plasma) type oxide film having a good filling property between the metal lines is used as the interlayer insulating film.
그러나, 종래의 기술에서는 상기 HDP 방식의 층간절연막 형성 시, 상기 HDP 내의 이온과 전자의 밀도가 불균일하기 때문에 그 하전입자가 상기 금속 배선에 차지 업(charge up)되며, 상기 차징된 입자는 금속 배선을 통해 게이트 산화막을 열화시키는 데미지를 유발하여 디바이스에 치명적인 손상을 가져오는 문제점이 있었다.However, in the related art, when the HDP type interlayer insulating film is formed, the density of ions and electrons in the HDP is uneven, so that charged particles are charged up to the metal wiring, and the charged particles are metal wiring. Through this, there is a problem of causing damage to the gate oxide film by causing damage to the device.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, HDP에 의한 데미지를 줄여 금속 배선에 차지 업되는 현상을 방지할 수 있는 금속 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring, which is devised to solve the above-described problems, and can prevent the phenomenon of being charged up on the metal wiring by reducing damage caused by HDP.
도 1a 내지 도 1d는 본 발명에 따른 금속 배선 형성 방법을 설명하기 위한 공정단면도.1A to 1D are cross-sectional views illustrating a method of forming a metal wiring according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
1. 반도체 기판 3. Al막1. Semiconductor substrate 3. Al film
5. 제 1Al2O3막 7. 유기 반사방지막5. First Al2O3 film 7. Organic antireflection film
9.금속 배선 11. 제 2Al2O3막9.Metal wiring 11.2 Al2O3 film
상기 목적을 달성하기 위한 본 발명에 따른 금속 배선 형성 방법은 반도체기판 상에 Al막을 형성하고 나서, Al막을 일정 두께로 산화하여 제 1Al2O3막을 형성하는 단계와, 제 1Al2O3막 상에 금속 배선 형성영역을 노출시키는 감광막 패턴을 차례로 형성하는 단계와, 감광막 패턴을 마스크로 하고 제 1Al2O3막 및 Al막을 플라즈마 건식 식각하여 금속 배선을 형성하는 단계와, 감광막 패턴을 제거하는 단계와, 금속 배선의 측면을 산화하여 제 2Al2O3막을 형성하는 단계를 포함한 것을 특징으로 한다.The metal wiring forming method according to the present invention for achieving the above object is to form an Al film on a semiconductor substrate, and then to oxidize the Al film to a predetermined thickness to form a first Al2O3 film, and to form a metal wiring formation region on the first Al2O3 film. Forming a exposed photoresist pattern in sequence, forming a metal wiring by plasma dry etching the first Al 2 O 3 film and an Al film using the photoresist pattern as a mask, removing the photoresist pattern, and oxidizing the side surface of the metal wiring And forming a second Al 2 O 3 film.
상기 제 1Al2O3막은 O3타입 애셔를 이용하여 50∼100Å 두께로 형성하며, 제 1Al2O3막 형성 공정은 300℃ 온도 및 15알피엠 하에서 20ℓ/min 의 O2 및 100g/Nm3의 O3 공급을 3분 동안 진행한다.The first Al 2 O 3 film is formed to have a thickness of 50 to 100 kPa using an O 3 type asher, and the first Al 2 O 3 film forming process is performed at a temperature of 300 ° C. and 15 alpha to supply 20 L / min of O 2 and 100 g / Nm 3 of O 3 for 3 minutes.
또한, 상기 Al2O3막 식각 공정은 식각 챔버 내부의 소오스 파워를 800∼1400와트(Watt)로, 바이어스 파워를 150∼200와트로, 압력을 5∼10mTorr로 각각 셋팅한 후, 상기 식각 챔버 내부에 BCl3가스를 100∼120sccm 유량으로, Cl2가스를 40∼60sccm 유량으로 각각 공급한다.In addition, in the Al2O3 film etching process, the source power of the etching chamber is set to 800 to 1400 watts (Watt), the bias power is set to 150 to 200 watts, and the pressure is set to 5 to 10 mTorr, respectively. Gas is supplied at a flow rate of 100 to 120 sccm and Cl 2 gas is supplied at a flow rate of 40 to 60 sccm.
한편, 상기 Al2O3막 제거 공정과 Al막 제거 공정은 인-시튜로 진행한다.Meanwhile, the Al 2 O 3 film removal process and the Al film removal process are performed in-situ.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명에 따른 금속 배선 형성 방법을 설명하기 위한 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a metal wiring according to the present invention.
본 발명의 일실시예에 따른 금속 배선 형성 방법은, 도 2a에 도시된 바와 같이, 먼저 반도체 기판(1) 상에 물리적 증착(Physical Vapor Deposition)방식에 의해 Al막(3)을 형성한 다음, 상기 Al막(3)을 산화하여 Al막(3) 위에 50∼100Å 두께의 제 1Al2O3막(5)을 형성한다. 이때, 상기 제 1Al2O3막(5)은 이 후의 금속 배선 형성을 위한 플라즈마 건식 식각 공정에서 반사방지막 역할을 한다.In the metal wire forming method according to the embodiment of the present invention, as shown in FIG. 2A, first, an Al film 3 is formed on a semiconductor substrate 1 by physical vapor deposition (Physical Vapor Deposition). The Al film 3 is oxidized to form a first Al 2 O 3 film 5 having a thickness of 50 to 100 GPa on the Al film 3. In this case, the first Al 2 O 3 film 5 serves as an anti-reflection film in a plasma dry etching process for forming metal wirings thereafter.
또한, 상기 산화 공정은 O3 타입 애셔(asher)(미도시)를 사용하며, 300℃ 온도 및 15알피엠(RPM) 조건 하에서, 20ℓ/min 의 O2 및 100g/Nm3의 O3 공급을 3분 동안 진행하여 제 1Al2O3막(5)을 형성한다.In addition, the oxidation process uses an O3 type asher (not shown), and under the conditions of 300 ° C. temperature and 15 Alp (RPM), 20 L / min O2 and 100 g / Nm3 O3 are supplied for 3 minutes. The first Al 2 O 3 film 5 is formed.
이어, 도 1b에 도시된 바와 같이, 상기 제 1Al2O3막(5) 위에 감광막을 도포하고 노광 및 현상하여 금속 배선영역(미도시)을 노출시키는 감광막 패턴(21)을 형성한다. 이때, 광원으로서 DUV(Deep Ultra Violet)를 이용한다. 상기 DUV 리쏘그라피(lithography)공정에서는 종래에 사용하였던 TiN막이 반사방지막으로서의 구실을 하지 못하므로, 본 발명에서는 상기 TiN막 대신 Al2O3막을 이용한다.Subsequently, as illustrated in FIG. 1B, a photoresist film is coated on the first Al 2 O 3 film 5, exposed, and developed to form a photoresist pattern 21 exposing a metal wiring region (not shown). At this time, DUV (Deep Ultra Violet) is used as a light source. In the DUV lithography process, the conventionally used TiN film does not serve as an antireflection film. Thus, the present invention uses an Al 2 O 3 film instead of the TiN film.
또한, 상기 감광막 패턴(21)을 형성하기 전에, 상기 제 1Al2O3막(5) 위에 유기 반사방지막(7)을 형성하여 리쏘그라피 디파인을 양호하게 할 수도 있다.In addition, before forming the photoresist pattern 21, an organic antireflection film 7 may be formed on the first Al 2 O 3 film 5 to improve lithography fine.
그런 다음, 도 1c에 도시된 바와 같이, 상기 감광막 패턴(21)을 마스크로 하고 상기 제 1Al2O3막 및 Al막을 동시에 플라즈마 건식 식각하여 금속 배선(9)을 형성한다.Then, as shown in FIG. 1C, the metal wiring 9 is formed by plasma dry etching the first Al 2 O 3 film and the Al film simultaneously with the photoresist pattern 21 as a mask.
이때, 상기 제 1Al2O3막을 식각하는 조건은, 식각 챔버(미도시) 내부의 소오스 파워(source power)를 800∼1400와트(Watt)로, 바이어스 파워(bias power)를 150∼200와트로, 압력(pressure)을 5∼10mTorr로 각각 셋팅시킨 후, 상기 셋팅된 식각 챔버 내로 BCl3가스를 100∼120sccm 유량으로, Cl2가스를 40∼60sccm 유량으로 각각 공급한다.In this case, the etching conditions of the first Al 2 O 3 film may include a source power of 800 to 1400 watts, a bias power of 150 to 200 watts, and a pressure ( pressure) is set at 5 to 10 mTorr, and then, BCl 3 gas is supplied at a flow rate of 100 to 120 sccm, and Cl 2 gas is supplied at a flow rate of 40 to 60 sccm, respectively, into the set etching chamber.
한편, 상기 제 1Al2O3막 제거 공정과 Al막 제거 공정은 인-시튜(in-situ)로 진행한다.On the other hand, the first Al2O3 film removal process and the Al film removal process proceed in-situ.
이 후, 상기 감광막 패턴을 제거한 다음, 도 1d에 도시된 바와 같이, 상기 금속 배선(9) 측면을 산화하여 제 2Al2O3막(11)을 형성한다. 이때, 상기 제 2Al2O3막(11)형성 공정은 O3 타입 애셔를 사용하여 진행한다.Thereafter, after removing the photoresist pattern, as shown in FIG. 1D, the side surface of the metal wiring 9 is oxidized to form a second Al 2 O 3 film 11. In this case, the process of forming the second Al 2 O 3 film 11 is performed using an O 3 type asher.
본 발명에 따르면, Al 금속 배선을 형성하는 데 있어서, Al막 상에 반사방지막으로서 Al2O3막을 형성함으로써, 이 후의 금속 배선 형성을 위한 플라즈마 건식 식각공정 시 상기 Al2O3막에 의해 상기 금속 배선의 상부가 드러날 우려가 없으므로 플라즈마 식각 데미지로부터 디바이스를 보호할 수 있다.According to the present invention, in forming an Al metal wiring, by forming an Al2O3 film on the Al film as an anti-reflection film, the upper portion of the metal wiring is exposed by the Al2O3 film during the plasma dry etching process for subsequent metal wiring formation. There is no concern to protect the device from plasma etch damage.
이상에서와 같이, 본 발명은 Al 금속 배선 상부에 Al막을 산화시켜 안정한 Al2O3막을 형성함으로써, 이 후의 금속 배선 형성을 위한 플라즈마 건식 식각공정 시, 상기 금속 배선의 상부가 드러날 우려가 없으므로 플라즈마 식각 데미지로부터 디바이스를 보호할 수 있다.As described above, the present invention forms a stable Al2O3 film by oxidizing the Al film on the Al metal wiring, so that during the plasma dry etching process for the subsequent metal wiring formation, the upper part of the metal wiring is not exposed, thereby preventing plasma from being etched. The device can be protected.
또한, 상기 구조의 금속 배선 위에 채움특성을 양호하게 하는 HDP 방식의 층간절연막 증착 시, 플라즈마 데미지로 인한 디바이스 손상을 방지할 수 있다.In addition, it is possible to prevent device damage due to plasma damage when the HDP type interlayer insulating film is deposited on the metal wiring having the above structure.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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