CN112271257A - Preparation method of stretchable semiconductor device - Google Patents

Preparation method of stretchable semiconductor device Download PDF

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Publication number
CN112271257A
CN112271257A CN202010991589.1A CN202010991589A CN112271257A CN 112271257 A CN112271257 A CN 112271257A CN 202010991589 A CN202010991589 A CN 202010991589A CN 112271257 A CN112271257 A CN 112271257A
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electrode
sacrificial layer
substrate
layer
forming
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CN112271257B (en
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张敏
黄巍宏
焦浩轩
黄秋月
张娇娜
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/491—Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes

Abstract

The invention relates to a preparation method of a stretchable semiconductor device, which comprises the following steps: forming a substrate sacrificial layer on a substrate; forming a substrate on the base plate sacrificial layer; forming a first electrode sacrificial layer on a substrate; forming a first electrode on the first electrode sacrificial layer; removing the first electrode sacrificial layer; forming a dielectric layer on the first electrode; forming a second electrode sacrificial layer on the dielectric layer; forming a second electrode and a third electrode on the second electrode sacrificial layer; forming a channel layer between the second electrodes; and removing the second electrode sacrificial layer. The invention further includes another method of making a stretchable semiconductor device.

Description

Preparation method of stretchable semiconductor device
Technical Field
The present invention relates to a method of manufacturing, and in particular to a method of manufacturing a stretchable semiconductor device.
Background
Stretchable semiconductor devices can be broadly classified into both intrinsic stretchable and extrinsic stretchable. Extrinsic stretchable semiconductor devices can be made with a special structure from conventional hard materials or using special methods to achieve a certain stretchability. However, these treatments are affected and limited in terms of large-area patterning, working stability, stretchability, etc. The preparation material of the intrinsic stretchable semiconductor device comprises a substrate, a dielectric layer, electrodes, a semiconductor layer and interconnecting wires which are all stretchable structures. Intrinsically stretchable semiconductors can have advantages in large area integration, tensile stability.
The fabrication of intrinsically stretchable semiconductor devices requires the use of stretchable materials, but most of these materials are solution-based, stretchable semiconductor devices are structurally stacked, and when the next layer of material is deposited based on a solution process, damage may be caused to the already prepared underlying material, causing problems including dissolution, intermixing or wrinkling. Thus, each layer structure is typically fabricated separately and the multiple layers are transferred to the same substrate by a multi-step transfer process to complete the fabrication of the intrinsically stretchable semiconductor device. However, the process requires a complicated alignment operation during the transfer process, which results in a large device size and thus affects the integration density of the device, and the device yield is low.
In recent years, ink jet printing has provided a solution for non-destructive device integration, and this approach has made significant progress in the preparation of stretchable semiconductors by selecting appropriate orthogonal inks to avoid material miscibility. However, limited by current ink jet printing technology, stretchable semiconductor devices prepared by printing tend to exhibit relatively low pattern resolution, thus limiting further device feature size reduction. At the same time, there are still certain difficulties in achieving printing ink stability, and there are also few challenges, especially in ink preparation for new materials, which limit the achievement of high integration by printing processes.
Therefore, finding a way to fabricate intrinsically stretchable semiconductor devices that combine high stretchability, high electrical performance, small feature size and mass producibility is crucial to the development of stretchable semiconductor devices.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a preparation method of a stretchable semiconductor device, which comprises the following steps: forming a substrate sacrificial layer on a substrate; forming a substrate on the base plate sacrificial layer; forming a first electrode sacrificial layer on a substrate; forming a first electrode layer on the first electrode sacrificial layer and patterning the first electrode layer to form a first electrode; removing the first electrode sacrificial layer; forming a dielectric layer on the first electrode; forming a second electrode sacrificial layer on the dielectric layer; forming a second electrode layer on the second electrode sacrificial layer, and patterning the second electrode layer to form a second electrode and a third electrode; forming a channel layer between the second electrode and the third electrode, and patterning the channel layer to form a channel; and removing the second electrode sacrificial layer.
Specifically, after the first electrode sacrificial layer and/or the second electrode sacrificial layer are/is formed, the method further includes: and (5) pre-baking treatment.
In particular, the substrate material comprises a silicon wafer or glass.
In particular, the substrate sacrificial layer material comprises dextran or PVA.
In particular, the substrate material comprises PDMS, Ecoflex, or PUU.
Particularly, the material of the first electrode sacrificial layer and/or the second electrode sacrificial layer comprises IGZO or Al2O3。
In particular, the first electrode, the second electrode material and/or the third electrode comprise metallic carbon nanotubes or conductive nanowires.
In particular, wherein the dielectric layer material comprises PUU, PDMS or SEBS.
In particular, wherein the channel layer material comprises semiconducting carbon nanotubes.
Particularly, the substrate sacrificial layer and/or dielectric layer forming process further comprises a curing process, wherein the curing temperature is 20 ℃ to 100 ℃, and the curing time is 1 hour to 12 hours, wherein the curing temperature is inversely proportional to the curing time.
Specifically, before forming the substrate sacrificial layer, the method further includes: and carrying out hydrophilic treatment on the substrate.
Specifically, after removing the second electrode sacrificial layer, the method further includes: and removing the substrate sacrificial layer.
The present invention further includes a method of making a stretchable semiconductor device, comprising: forming a substrate sacrificial layer on a substrate; forming a substrate on the base plate sacrificial layer; forming a first electrode sacrificial layer on a substrate; forming a first electrode layer on the first electrode sacrificial layer and patterning the first electrode layer to form a second electrode and a third electrode; forming a channel layer between the second electrode and the third electrode, and patterning the channel layer to form a channel; removing the first electrode sacrificial layer; forming a dielectric layer on the second electrode, the third electrode and the channel; forming a second electrode sacrificial layer on the dielectric layer; forming a second electrode layer on the second electrode sacrificial layer and patterning the second electrode layer to form a first electrode; and removing the second electrode sacrificial layer.
Specifically, after the first electrode sacrificial layer and/or the second electrode sacrificial layer are/is formed, the method further includes: and (5) pre-baking treatment.
In particular, the substrate material comprises a silicon wafer or glass.
In particular, the substrate sacrificial layer material comprises dextran or PVA.
In particular, the substrate material comprises PDMS, Ecoflex, or PUU.
Particularly, the material of the first electrode sacrificial layer and/or the second electrode sacrificial layer comprises IGZO or Al2O3。
In particular, the first electrode, the second electrode and/or the third electrode material comprises metallic carbon nanotubes or conductive nanowires.
In particular, wherein the dielectric layer material comprises PUU, PDMS or SEBS.
In particular, wherein the channel layer material comprises semiconducting carbon nanotubes.
Particularly, the substrate sacrificial layer and/or dielectric layer forming process further comprises a curing process, wherein the curing temperature is 20 ℃ to 100 ℃, and the curing time is 1 hour to 12 hours, wherein the curing temperature is inversely proportional to the curing time.
Specifically, before forming the substrate sacrificial layer, the method further includes: and carrying out hydrophilic treatment on the substrate.
Specifically, after removing the second electrode sacrificial layer, the method further includes: and removing the substrate sacrificial layer.
Drawings
Preferred embodiments of the present invention will now be described in further detail with reference to the accompanying drawings, in which:
FIGS. 1A-1L are schematic device structures illustrating a method of fabricating a stretchable semiconductor device according to one embodiment of the present invention;
FIGS. 2A-2L are perspective views of device structures fabricated by a method of fabricating a stretchable semiconductor device according to an embodiment of the present invention;
FIG. 3 is a schematic flow chart of a method of fabricating a stretchable semiconductor device according to one embodiment of the present invention;
fig. 4A is a diagram illustrating a tensile state of a tensile semiconductor fabricated by a method of fabricating a tensile semiconductor device according to an embodiment of the present invention;
FIG. 4B shows the tensile semiconductor prepared by the method of manufacturing a tensile semiconductor device according to an embodiment of the present invention under different stretching conditions IDS-VGSA relationship graph;
figure 4C is a graph of tensile semiconductor elongation, mobility, and sub-threshold swing relationship for a method of making a tensile semiconductor device according to one embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof and in which is shown by way of illustration specific embodiments of the application. In the drawings, like numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized and structural, logical or electrical changes may be made to the embodiments of the present application.
Conventional processes of photolithography and plasma etching have many advantages in terms of process compatibility, equipment maturity, and low cost in order to fabricate intrinsically stretchable semiconductor devices with high stretchability, high electrical performance, small feature size, and mass producibility. However, most stretchable organic elastomers are not resistant to plasma etching and it is difficult to deposit other materials directly thereon by solution methods, so that the introduction of a protective layer suitable for the chosen material system is particularly important in the manufacture of stretchable semiconductor devices based on photolithographic processes. However, the introduction of the inorganic protective layer can cause the electrical performance of the transistor to be obviously degraded after stretching. Therefore, the development of fabricating stretchable semiconductor devices on photolithographic platforms is slow.
The present application provides a method of fabricating an intrinsically stretchable semiconductor device, which avoids the previous problems while utilizing the advantages of photolithography and plasma etching, such as alignment effects, etc., and achieves fabrication of a stretchable semiconductor device of high stretchability, high electrical stability, and small size.
Preferred embodiments of the present invention will now be described in further detail with reference to the accompanying drawings, in which:
fig. 1A to 1L are schematic views illustrating a device structure prepared by a method for preparing a stretchable semiconductor device according to an embodiment of the present invention, fig. 2A to 2L are perspective views illustrating a device structure prepared by a method for preparing a stretchable semiconductor device according to an embodiment of the present invention, and fig. 3 is a schematic flow chart illustrating a method for preparing a stretchable semiconductor device according to an embodiment of the present invention. Fig. 2A to 2L correspond to the structures in fig. 1A to 1L one by one, and fig. 3 corresponds to the steps in fig. 1A to 1L one by one. The present application is described in detail below with reference to the attached drawings. The method steps involved are merely exemplary, and only one bottom-gate transistor is shown, as known to those skilled in the art, and the disclosed method is equally applicable to other types of semiconductor devices, such as diodes, etc.
In the methods of the present application, the polymer curing process is not described in detail in the steps without specific descriptions. In some embodiments, the curing temperature is 20 ℃ to 100 ℃, the curing time is 1 hour to 12 hours, and the curing time and curing temperature are inversely proportional. Without specific mention, the curing process is not embodied in the step.
Step 1001: and (5) carrying out hydrophilic treatment on the surface of the substrate. According to one embodiment, the substrate may comprise a silicon wafer and the hydrophilic treatment may comprise an oxygen plasma treatment.
In some embodiments, as shown in fig. 1A and 2A, a silicon wafer is used as the substrate 101 for the manufacturing process, and the substrate 101 is first surface-treated with oxygen plasma for 5 minutes at a power of, for example, 100W. The hydrophilicity of the substrate 101 after the treatment is improved. In some embodiments, the substrate 101 may be a silicon wafer, or may be replaced by other hard materials, such as glass. Of course, the substrate 101 may be hydrophilically treated by other methods.
Step 1002: a substrate sacrificial layer is formed on a substrate. According to one embodiment, the substrate sacrificial layer may comprise dextran.
In some embodiments, as shown in fig. 1B and 2B, dextran is dissolved in deionized water at a 1:10 ratio and agitated for 1 hour at 40 ℃ to form a dextran solution. The dextran solution was spin coated on the surface of the substrate 101 at 2000rpm for a period of 50s to obtain a 550 nm thick substrate sacrificial layer 102. Then baking at 120 deg.C for 5 min. Of course, other methods may be used to form the substrate sacrificial layer 102. In some embodiments, other materials, such as PVA, may be used for the substrate sacrificial layer 102, as long as the material is water-soluble and has no effect on other structures of the device.
Although inherently stretchable devices, stretchable semiconductor devices are referred to herein, a rigid structure (e.g., a substrate) is still required as a support structure for the semiconductor device during fabrication. And after fabrication, the stretchable semiconductor device needs to be separated from the rigid support structure. The substrate sacrificial layer can exist as a transition layer between the substrate sacrificial layer and the stretchable semiconductor device, the substrate sacrificial layer is filled between the substrate and the stretchable semiconductor device in the preparation process, and the substrate sacrificial layer can be easily removed after the preparation process is completed so as to realize the separation of the substrate and the stretchable semiconductor.
Step 1003: a substrate is formed on the base plate sacrificial layer. According to one embodiment, the substrate may comprise a PDMS material.
In some embodiments, as shown in fig. 1C and 2C, the prepolymer and curing agent are mixed in a mass ratio of 10:1 to form a PDMS solution. The PDMS containing solution was spin coated on the substrate sacrificial layer 102 surface at 800rpm for 60 s. Then, the semiconductor device was processed at a constant temperature of 70 ℃ for 15 min. Thereafter, the PDMS solution was again spin coated at 1500rpm and 3000rpm, respectively. A dielectric film is formed to a thickness of about 1.25 μm, which is the substrate 103. Then, the semiconductor device was left for an additional 2 hours at a constant temperature of 70 ℃. Of course, other methods may be used to form the PDMS layer. In some embodiments, other elastic materials may be used for the substrate 103, such as Ecoflex, PUU, and the like.
Step 1004: a first electrode sacrificial layer is formed on a substrate. According to one embodiment, the first electrode sacrificial layer may include IGZO.
In some embodiments, as shown in FIGS. 1D and 2D, IGZO was magnetron sputtered at 100w power for a time period of 85s in an argon atmosphere at an oxygen concentration of 6% and a gas pressure of 0.43 Pa. A first electrode sacrificial layer 104 was formed on the substrate 103 to a thickness of 12 nm. In some embodiments, the first electrode sacrificial layer 104 mayIncluding other inorganic materials having acid-etchability, e.g. Al2O3And the like. Of course, the first electrode sacrificial layer 104 may be formed by other methods.
The first electrode sacrificial layer 104 may protect the substrate 103 from oxygen plasma during patterning of the counter electrode. At the same time, the wettability of the substrate 103 is improved to improve the tube density of the carbon nanotubes spin-coated thereon.
In some embodiments, in order to relieve thermal stress, a device pre-bake process is further included after forming first electrode sacrificial layer 104.
Step 1005: and forming a first electrode layer on the first electrode sacrificial layer, and patterning the first electrode layer to form a first electrode. According to one embodiment, the first electrode layer material may comprise metallic carbon nanotubes.
In some embodiments, as shown in FIGS. 1E and 2E, an aqueous dispersion (0.9 wt%) of metallic carbon nanotubes (M-CNTs) is spin coated at 4000rpm onto the first electrode sacrificial layer 104 for 40 s. After the spin coating is finished, the semiconductor device is annealed at 120 ℃ for 10min to form a first electrode layer. Thereafter, it is patterned into the first electrode 105 by photolithography and oxygen plasma etching. Wherein the etching parameter of the oxygen plasma is 3 l.min-1Nitrogen gas at 5sccm, power 100w, for 45 minutes. Of course, other methods may be used to form the first electrode 105. According to one embodiment, the first electrode layer 105 may be patterned using plasma etching, thereby forming a first electrode.
In some embodiments, the first electrode 105 is configured as a gate electrode of a transistor.
Step 1006: and removing the first electrode sacrificial layer.
In some embodiments, as shown in fig. 1F and 2F, the present semiconductor device is immersed in a hydrochloric acid solution (1: 50 dilution in deionized water) to remove the first electrode sacrificial layer 104. The first electrode 105 is attached to the substrate 103. The semiconductor device was then taken out and dried at 120 ℃ for 5 min. Of course, other methods may be used to remove the first electrode sacrificial layer.
The first electrode sacrificial layer protects the substrate 103 from oxygen plasma during patterning during formation of the first electrode 105. At the same time, the wettability of the substrate 103 is improved to improve the tube density of the carbon nanotubes spin-coated thereon. In the etching process, because gaps exist among the carbon nanotubes, hydrochloric acid can penetrate through the gaps to etch the electrode sacrificial layer. The etching speed of the first electrode sacrificial layer in the longitudinal direction is higher than that in the transverse direction. After the first electrode sacrificial layer is etched away, the electrode can be dropped in the vertical direction in situ, attaching to the substrate without drifting. After the first electrode 105 is formed, the electrode sacrificial layer is no longer a structure required by the device, and the electrode sacrificial layer is removed by hydrochloric acid, so that the influence on the electrical and mechanical properties of the stretchable semiconductor device in a tensile test can be avoided, residual dispersing agents in the carbon nano tubes can be removed, and other structures of the device are not influenced.
Step 1007: a dielectric layer is formed on the first electrode. According to one embodiment, the dielectric layer may comprise a PUU.
In some embodiments, as shown in FIGS. 1G and 2G, the PPG-TDI and APDS are first mixed in tetrahydrofuran at a ratio of 100:10.7 to form a concentration of 170 mg/ml-1Then stirred at 35 ℃ for 2 hours to form a PUU solution. The PUU solution was spin-coated on the first electrode 105 at 5000rpm for 50s to form a dielectric layer 106 of 1 μm. Then annealed at 100 ℃ for 5 hours to remove the THF solvent. Of course, other methods may be used to form the dielectric layer 106. In some embodiments, the dielectric layer 106 may comprise other corrosion resistant organic elastomeric dielectric materials, such as PDMS, SEBS, and the like.
Step 1008: and forming a second electrode sacrificial layer on the dielectric layer.
In some embodiments, as shown in fig. 1H, the second electrode sacrificial layer 107 is formed on the dielectric layer 106 to a thickness of 12nm by sputtering IGZO (parameter reference step 1004). Of course, the second electrode sacrificial layer 107 may be formed by other methods.
In some embodiments, in order to release the thermal stress, a device pre-bake process is further included after forming the second electrode sacrificial layer 107.
The second electrode sacrificial layer 107 may protect the dielectric layer 106 from oxygen plasma during the patterning process. At the same time, the wettability of the dielectric layer 106 is improved to improve the tube density of the carbon nanotubes spin-coated thereon.
Step 1009: and forming a second electrode layer on the second electrode sacrificial layer, and patterning the second electrode layer to form a second electrode and a third electrode.
In some embodiments, as shown in FIG. 1I, a prepared aqueous dispersion of M-CNTs (0.3 wt%) was spin coated on the second electrode sacrificial layer 107 at 3000rpm for 40 s. And annealing for 10min at 100 ℃ to form a second electrode layer. And then patterned into the second electrode 108 and the third electrode 109 by photolithography and oxygen plasma etching. Wherein the oxygen plasma etching parameter is that oxygen is 3 l.min-1The nitrogen is 5sccm, the power is 100W, and the time duration is 40 min. In some embodiments, the second electrode is configured as a source electrode and a drain electrode of the transistor. Of course, the second electrode 108 and the third electrode 109 may be formed by other methods.
Step 1010: a channel layer is formed between the second electrode and the third electrode and patterned to form a channel.
In some embodiments, CNTs (1.0-1.4 nm in diameter, 1-2 μm in length) are administered at 0.01mg mL, as shown in FIG. 1J-1Is dispersed in a DCE (1,2 dichloroethane) solution containing a dispersant. The solution was sonicated for 30 minutes and then spin coated at 1500rpm for 40 seconds on the second sacrificial layer 108. Thereafter, annealing was performed at 100 ℃ for 15min to form a channel layer. The channel layer is patterned by photolithography and oxygen plasma etching to form a channel 110 between the second electrode 108 and the third electrode 109 over the gate electrode 105. Wherein the oxygen plasma etching parameter is that oxygen is 3 l.min-1The nitrogen is 5sccm, the power is 100W, and the time duration is 25 min. In some embodiments, the channel 110 has a width of 20 μm and a length of 5-100 μm. Of course, other methods may be used to form the channel 110.
Step 1011: and removing the second electrode sacrificial layer.
In some embodiments, as shown in fig. 1K, the semiconductor device is immersed in a hydrochloric acid solution (concentration as above) for a period of 100s to remove the second electrode sacrificial layer 107. The upper structure of the second electrode sacrificial layer 107 is attached to the lower structure thereof. Then, the newly obtained semiconductor device was heated to 70 ℃ and maintained for 2 hours to improve the adhesion. Of course, other methods may be used to remove the second electrode sacrificial layer.
The second electrode sacrificial layer 107 protects the dielectric layer 106 from oxygen plasma during patterning in the process of forming the second electrode 108, the third electrode 109 and the channel layer 110. At the same time, the wettability of the substrate 103 is improved to improve the tube density of the carbon nanotubes spin-coated thereon. In the etching process, because gaps exist among the carbon nanotubes, hydrochloric acid can penetrate through the gaps to etch the electrode sacrificial layer. The etching speed of the second electrode sacrificial layer in the longitudinal direction is higher than that in the transverse direction. After the second electrode sacrificial layer is etched away, the electrode and the channel layer may be dropped in a vertical direction in situ, attaching to the substrate without drifting. After the second electrode 108, the third electrode 109 and the channel layer 110 are formed, the second electrode sacrificial layer 107 itself is no longer a structure required by the device, and the electrode sacrificial layer is removed by hydrochloric acid, so that not only can the electrical and mechanical properties of the stretchable semiconductor device be prevented from being influenced in a tensile test, but also the dispersant remained in the carbon nanotubes can be removed, and meanwhile, other structures of the device are not influenced.
Step 1012: and removing the substrate sacrificial layer.
In some embodiments, as shown in fig. 1L, a corner of the semiconductor device is selected, the substrate 103 is partially peeled from the base plate 101, and then the entire semiconductor device is immersed in deionized water. Since the substrate sacrificial layer 102 is dissolved in water, the substrate sacrificial layer 102 disappears after a certain time, and the stretchable semiconductor device is separated from the substrate 101. And drying the stretchable semiconductor device by nitrogen, and baking for 10min at the temperature of 70 ℃ to obtain the final stretchable semiconductor device. Of course, other methods may be used to remove the substrate sacrificial layer.
Formed in the above method is a bottom gate stretchable semiconductor device. Of course, in some embodiments, a similar method may also be utilized to form a top-gate stretchable semiconductor device. The methods of processing the substrate, forming the substrate sacrificial layer and the stretchable substrate are the same as those described above, a first electrode sacrificial layer may be formed on the stretchable substrate, and then the second electrode and the third electrode (e.g., source and drain) and the conductive channel are formed on the first electrode sacrificial layer, and then the first electrode sacrificial layer is removed. Then, a dielectric layer is formed on the second third electrode and the conductive channel, a second electrode sacrificial layer is formed on the dielectric layer, a first electrode (for example, a gate electrode) is formed on the second electrode sacrificial layer, then the second electrode sacrificial layer is removed, and finally the stretchable semiconductor device is peeled off from the substrate by removing the substrate sacrificial layer.
The semiconductor device prepared by the method has the characteristics of excellent stretchability and stable electrical characteristics after stretching. Fig. 4A is a diagram illustrating a tensile state of a tensile semiconductor fabricated by a method of fabricating a tensile semiconductor device according to an embodiment of the present invention. The prepared semiconductor device is stretched as shown in the figure, and even after being stretched for many times, the stretchability and the electrical characteristics of the semiconductor device are still stable.
FIG. 4B shows the tensile semiconductor prepared by the method of manufacturing a tensile semiconductor device according to an embodiment of the present invention under different stretching conditions IDS-VGSAnd (5) a relational graph. Wherein the experimental results shown in the figure are at VDSIn the case of-1V, IDS-VGSAnd (5) a relational graph. In the figure, curve 401 is I for the semiconductor device produced at a degree of stretching of 0% (unstretched)DS-VGSThe relationship of (1). Curve 402 is I after the semiconductor device prepared has been subjected to a tensile deformation with a degree of elongation of 10%DS-VGSThe relationship of (1). Curve 403 shows I after subjecting the semiconductor device to a tensile deformation with a degree of elongation of 20%DS-VGSThe relationship of (1). Curve 404 is I after subjecting the semiconductor device prepared to a tensile deformation with a degree of elongation of 30%DS-VGSThe relationship of (1). Curve 405 shows the tensile deformation of the semiconductor device produced when it is subjected to a degree of stretching of 40%Then, IDS-VGSThe relationship of (1). Curve 406 is I after subjecting the semiconductor device prepared to a tensile deformation with a degree of elongation of 50%DS-VGSThe relationship of (1). It is clear from the curves in the figure that the variation range between the curves is small in the case of different stretching degrees.
Figure 4C is a graph of tensile semiconductor elongation, mobility, and sub-threshold swing relationship for a method of making a tensile semiconductor device according to one embodiment of the present invention. Where curve 410 is the carrier mobility versus the degree of stretching and curve 411 is the device sub-threshold swing versus the degree of stretching. As is clear from the curves in the figure, the rate of change of both curves as a whole is very small in the case of different degrees of stretching.
Fig. 4B and 4C clearly show that the electrical characteristics of the semiconductor device manufactured by the method of the present application are very stable when the degree of stretching is changed.
The method described herein uses a network of carbon nanotubes (or conductive nanowires) as the source/drain/gate/channel layer to achieve a high performance intrinsically stretchable semiconductor. Creatively provides that an electrode sacrificial layer is added in the preparation process to improve the wettability of the substrate and the dielectric layer and simultaneously protect the substrate and the dielectric layer from being damaged by oxygen plasma in the patterning process. Furthermore, the electrode sacrificial layer can be removed at the end of device fabrication, improving the stability of the stretchable semiconductor device during stretching. Compared with the existing stretchable semiconductor, the stretchable semiconductor device prepared by the method has smaller size, higher driving current density and higher field effect mobility. The stretchable semiconductor devices prepared by the methods described herein retain their excellent electrical properties after 2000 stretching cycles at 50% tensile strain.
The above embodiments are provided only for illustrating the present invention and not for limiting the present invention, and those skilled in the art can make various changes and modifications without departing from the scope of the present invention, and therefore, all equivalent technical solutions should fall within the scope of the present invention.

Claims (24)

1. A method of making a stretchable semiconductor device, comprising:
forming a substrate sacrificial layer on a substrate;
forming a substrate on the base plate sacrificial layer;
forming a first electrode sacrificial layer on a substrate;
forming a first electrode layer on the first electrode sacrificial layer and patterning the first electrode layer to form a first electrode;
removing the first electrode sacrificial layer;
forming a dielectric layer on the first electrode;
forming a second electrode sacrificial layer on the dielectric layer;
forming a second electrode layer on the second electrode sacrificial layer, and patterning the second electrode layer to form a second electrode and a third electrode;
forming a channel layer between the second electrode and the third electrode, and patterning the channel layer to form a channel; and
removing the second electrode sacrificial layer;
wherein the substrate, the first electrode, the second electrode, the third electrode, the channel, and the dielectric layer have stretchability.
2. The method of claim 1, further comprising, after forming the first and/or second electrode sacrificial layers: and (5) pre-baking treatment.
3. The method of claim 1, the substrate material comprising silicon wafer or glass.
4. The method of claim 1, the substrate sacrificial layer material comprising dextran or PVA.
5. The method of claim 1, the substrate material comprising PDMS, Ecoflex, or PUU.
6. The method of claim 1, the first electrodeThe sacrificial layer and/or the second electrode sacrificial layer material comprises IGZO or Al2O3。
7. The method of claim 1, the first electrode, second electrode material, and/or third electrode comprising metallic carbon nanotubes or conductive nanowires.
8. The method of claim 1, wherein the dielectric layer material comprises PUU, PDMS, or SEBS.
9. The method of claim 1, wherein the channel layer material comprises semiconducting carbon nanotubes.
10. The method of claim 1, wherein the substrate sacrificial layer and/or dielectric layer forming process further comprises a curing process, wherein the curing temperature is 20 ℃ to 100 ℃ and the curing time is 1 hour to 12 hours, and wherein the curing temperature is inversely proportional to the curing time.
11. The method of claim 1, further comprising, prior to forming the substrate sacrificial layer: and carrying out hydrophilic treatment on the substrate.
12. The method of claim 1, further comprising, after removing the second electrode sacrificial layer: and removing the substrate sacrificial layer.
13. A device fabrication method of a stretchable semiconductor device, comprising:
forming a substrate sacrificial layer on a substrate;
forming a substrate on the base plate sacrificial layer;
forming a first electrode sacrificial layer on a substrate;
forming a first electrode layer on the first electrode sacrificial layer and patterning the first electrode layer to form a second electrode and a third electrode;
forming a channel layer between the second electrode and the third electrode, and patterning the channel layer to form a channel;
removing the first electrode sacrificial layer;
forming a dielectric layer on the second electrode, the third electrode and the channel;
forming a second electrode sacrificial layer on the dielectric layer;
forming a second electrode layer on the second electrode sacrificial layer and patterning the second electrode layer to form a first electrode;
removing the second electrode sacrificial layer;
wherein the substrate, the first electrode, the second electrode, the third electrode, the channel, and the dielectric layer have stretchability.
14. The method of claim 13, further comprising, after forming the first and/or second electrode sacrificial layers: and (5) pre-baking treatment.
15. The method of claim 13, the substrate material comprising silicon wafer or glass.
16. The method of claim 13, the substrate sacrificial layer material comprising dextran or PVA.
17. The method of claim 13, the substrate material comprising PDMS, Ecoflex, or PUU.
18. The method of claim 13, the first and/or second electrode sacrificial layer material comprising IGZO or Al2O3。
19. The method of claim 13, the first, second and/or third electrode material comprising metallic carbon nanotubes or conductive nanowires.
20. The method of claim 13, wherein the dielectric layer material comprises PUU, PDMS, or SEBS.
21. The method of claim 13, wherein the channel layer material comprises semiconducting carbon nanotubes.
22. The method of claim 13, wherein the substrate sacrificial layer and/or dielectric layer forming process further comprises a curing process, wherein the curing temperature is 20 ℃ to 100 ℃ and the curing time is 1 hour to 12 hours, and wherein the curing temperature is inversely proportional to the curing time.
23. The method of claim 13, further comprising, prior to forming the substrate sacrificial layer: and carrying out hydrophilic treatment on the substrate.
24. The method of claim 13, further comprising, after removing the second electrode sacrificial layer: and removing the substrate sacrificial layer.
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