CN110943168A - Stretchable synapse based on organic thin film transistor and preparation method thereof - Google Patents
Stretchable synapse based on organic thin film transistor and preparation method thereof Download PDFInfo
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- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
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- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
Abstract
The invention relates to a stretchable synapse based on an organic thin film transistor and a preparation method thereof. The stretchable composite coplanar gate substrate is composed of a Polydimethylsiloxane (PDMS) film and a patterned coplanar electrode arranged on the PDMS film. The invention can effectively promote the development of flexible stretchable electronics in the aspects of biological implantation, man-machine interaction interface, wearing and the like.
Description
Technical Field
The invention relates to the field of organic photoelectric materials, in particular to a stretchable synapse based on an organic thin film transistor and a preparation method thereof.
Background
The human brain is composed of a large number of synapses and neurons, is a powerful information processor, and has the outstanding characteristics of parallel processing, high density, fault tolerance and the like. Synapses, which are the basic building blocks of biological brains, connect presynaptic neurons and postsynaptic neurons and are responsible for the learning and memory of the human brain. Therefore, there is a high demand for future development of neuromorphic computing to develop electronic synapses capable of simulating synaptic function.
The traditional electronic synapse based on the CMOS structure has the problems of complex process, high cost, large power consumption and the like. The two-end synapse device developed in recent years simplifies the structure of the device and improves the integration level, but an additional training circuit is needed to realize the simultaneous learning and processing functions of synapses. In contrast, a three-terminal device, i.e., a synapse based on an organic thin film transistor, can simultaneously implement processing and memory functions due to the regulation and control effect of gate voltage on source-drain voltage, which effectively simplifies the learning scheme and eliminates complex synchronization algorithms. Therefore, the successful preparation of three-terminal electronic synapses based on transistor structures is of great significance.
It is worth noting that with the development of flexible stretchable electronics, the applications of the flexible stretchable electronics in bio-implantability, man-machine interaction interface and the like are increasing, which requires the devices to have good mechanical compatibility and to withstand large mechanical deformation. Therefore, the preparation of high performance stretchable devices is crucial to drive the development of flexible stretchable electronics.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a stretchable synapse based on an organic thin film transistor and a method for fabricating the same, which can effectively promote the development of flexible stretchable electronics in bio-implantability, human-computer interaction interface, and wearable aspects.
The invention is realized by adopting the following scheme: a stretchable synapse based on an organic thin film transistor sequentially comprises a stretchable composite coplanar gate substrate, a wrinkled organic semiconductor layer and an ion gel insulating layer from bottom to top.
Further, the stretchable composite coplanar gate substrate is composed of a Polydimethylsiloxane (PDMS) film and a patterned coplanar electrode arranged on the PDMS film.
Wherein the coplanar electrode comprises a source, a drain, and a gate.
When the stretchable synapsis device is prepared, the organic semiconductor layer is arranged on the surface of the ionic gel insulating layer, the ionic gel insulating layer is stripped from the surface of the substrate, the substrate is overturned and laminated on the prestretched stretchable composite coplanar gate substrate, then the substrate is released, the stretchable synapsis of the organic thin film transistor with the coplanar gate structure can be obtained, the ionic gel insulating layer is required to be in contact with a gate electrode when the stretchable synapsis device is laminated, and the synapsis function can be simulated by the stretchable synapsis device according to the long-range polarization effect of ionic gel and the regulation.
Further, the patterned coplanar electrode is prepared by spraying Carbon Nanotubes (CNTs) with a thickness of 30 nm to 100 nm in combination with a mask plate.
Alternatively, the patterned coplanar electrode is prepared by spraying silver nanowires (AgNW) in a thickness of 30 nm to 100 nm in conjunction with a mask plate.
Further, the corrugated (wave-shaped) organic semiconductor layer is obtained by transferring the semiconductor layer to a pre-stretched stretchable composite coplanar gate substrate and then releasing. The wrinkle-shaped (wave-shaped) nanofiber organic semiconductor layer can absorb external force, relieve mechanical damage of the external force to the film and improve the mechanical stability of the film, so that the stretching capacity of the device is improved.
Further, the organic semiconductor layer is a nanofiber film, and the thickness of the organic semiconductor layer is 30 nm-50 nm.
Further, the ionic gel insulation layer has a thickness of 1 μm to 3 μm, and is prepared by spin coating or blade coating. The ionic gel insulating layer has a long-range polarization characteristic, so that non-alignment regulation of grid voltage to channel current carriers can be realized in a coplanar grid structure, and the limitation of alignment of a grid electrode and a source drain electrode in the traditional organic thin film transistor structure is eliminated.
Further, the organic semiconductor layer is subjected to patterning treatment when being transferred to the stretchable composite coplanar gate substrate, so that the ion gel insulating layer is in contact with the gate electrode on the stretchable composite coplanar gate substrate.
The invention also provides a preparation method of the stretchable synapse of the organic thin film transistor, which comprises the following steps:
preparing a stretchable composite coplanar gate substrate;
preparing an ion gel insulating layer and an organic semiconductor layer;
transferring and laminating the ionic gel insulating layer and the organic semiconductor layer onto a pre-stretched stretchable composite coplanar gate substrate;
releasing the pre-stretched stretchable composite coplanar gate substrate.
Further, the organic semiconductor layer is subjected to patterning processing when the ion gel insulating layer and the organic semiconductor layer are transfer-laminated on the stretchable composite coplanar gate substrate, so that the ion gel insulating layer is in contact with the gate electrode on the stretchable composite coplanar gate substrate when the ion gel insulating layer and the organic semiconductor layer are laminated.
The preparation method specifically comprises the following steps:
step S11: cleaning a substrate and carrying out appropriate surface treatment, wherein the substrate is made of glass or a silicon wafer;
step S12: preparing a patterned coplanar electrode on the substrate by adopting a spraying process and combining a mask plate, wherein the thickness of the electrode is 30 nm to 100 nm, and the length and the width of a channel between a source electrode and a drain electrode are respectively 1 mm and 30 micrometers;
step S13: preparing a PDMS film on the coplanar electrode by adopting a spin coating or blade coating process;
step S14: peeling the PDMS film from the substrate to obtain a stretchable composite coplanar gate substrate;
step S15: preparing an ion gel insulating layer on the substrate in the step S11 by adopting a spin coating or blade coating process;
step S16: preparing an organic semiconductor layer on the surface of the ionic gel insulating layer by adopting a spin coating or blade coating process;
step S17: peeling the ion gel insulating layer from the substrate, overturning the ion gel insulating layer, transferring and laminating the ion gel insulating layer onto the stretchable composite coplanar gate substrate prepared in the pre-stretching step S14, and ensuring the ion gel insulating layer to be in contact with the gate electrode during lamination;
step S18: slowly releasing the pre-stretched stretchable composite co-planar gate substrate in step S17.
Specifically, in step S11, the method for cleaning the substrate includes: ultrasonic cleaning in acetone, isopropanol and deionized water for 5-10 min, and blowing with nitrogen for use, wherein the surface treatment method comprises the following steps: plasma treatment for 5-10 min or octadecyl Octyl Trichlorosilane (OTS) treatment for about 20 min; OTS treatment process: mixing OTS and toluene in a certain volume ratio in a clean culture dish, putting the mixture into a substrate to be treated, heating and fumigating for about 20 min, taking out a treated sample, washing the treated sample with toluene and isopropanol respectively, and drying the sample with nitrogen for later use;
in step S12, a specific method of preparing the patterned coplanar electrode is: adjusting the distance between a thimble and a nozzle of the spray gun, placing the substrate on a heating table at 120 ℃ for preheating, fixing a mask plate on the surface of the sample, spraying, and annealing the prepared electrode at 150 ℃ at 120 ℃ after spraying to improve the conductivity of the electrode; the selected carbon nano tube spraying solution is prepared by uniformly mixing a carbon nano tube stock solution and deionized water according to a certain volume ratio and then standing for later use; the selected silver nanowire spraying solution is prepared by diluting a silver nanowire stock solution with isopropanol and standing for later use;
in step S13, the method for preparing the PDMS film includes: uniformly mixing PDMS stock solution and a cross-linking agent according to a certain mass ratio, vacuumizing to remove bubbles in the mixed solution, and standing for later use; spin-coating or blade-coating a PDMS film on the substrate with the electrode prepared in the step S12, and then annealing at 60-80 ℃ in a vacuum box for at least 24 h;
in step S15, the method for preparing the ionic gel film includes: spin-coating an ion gel insulating layer on the substrate in the step S11 at a certain rotation speed for about 60S, and after the spin-coating is finished, placing the obtained film in a vacuum box for annealing at 80-110 ℃ for at least 12 h;
in step S16, the specific method for preparing the organic semiconductor layer is: spin-coating an organic polymer semiconductor layer P3HT-NF on the insulating layer at the rotating speed of 800-1000 rpm for about 60 s, and annealing in a vacuum box at about 150 ℃ for 10-15 min after the spin-coating is finished; preparation of organic semiconductor solution: selecting trichloromethane as a solvent, preparing a P3HT solution with a certain concentration, then placing the solution on a heating table for heating to accelerate the dissolution of P3HT, mixing the completely dissolved P3HT solution and tetrahydrofuran according to a certain volume ratio, stirring the mixed solution at a high speed and by magnetic force for at least 12 hours, and standing for later use.
Compared with the prior art, the invention has the following beneficial effects: the stretchable synapse based on the organic thin film transistor and the preparation method thereof not only improve the mechanical stability of a stretchable device, but also reduce the process difficulty due to the long-range polarization effect of the ionic gel, and get rid of the problem that a grid electrode in the organic thin film transistor needs to be aligned with a source-drain electrode channel. The device can simulate synapse function, has important significance for the development of human-computer interaction, biological medical treatment, nerve morphology calculation and the like, and has wide application prospect.
Drawings
FIG. 1 is a schematic diagram of a stretchable synapse structure of an organic thin film transistor based device fabricated in accordance with an embodiment of the present invention;
FIG. 2 is a stretchable composite coplanar gate substrate prepared according to one embodiment of the present invention;
FIG. 3 is a schematic diagram of a stretchable synapse structure based on an organic thin film transistor fabricated in accordance with a second embodiment of the present invention;
FIG. 4 is a stretchable composite coplanar gate substrate prepared in accordance with example two of the present invention;
in the figure: 100 is PDMS film; 110 is a coplanar electrode made of carbon nanotubes; 111 is a coplanar electrode prepared by silver nanowires; 120 is an organic semiconductor layer; 130 is an ion gel insulating layer; 140 is a stretchable composite coplanar gate substrate; 150 is a gate; 160 is a source electrode; and 170 is a drain.
Detailed Description
The invention is further explained below with reference to the drawings and the embodiments.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
The embodiment provides a stretchable synapse based on an organic thin film transistor, which sequentially comprises a stretchable composite coplanar gate substrate, a corrugated organic semiconductor layer and an ionic gel insulating layer from bottom to top.
In this embodiment, the stretchable composite coplanar gate substrate is composed of a Polydimethylsiloxane (PDMS) thin film and a patterned coplanar electrode disposed thereon.
Wherein the coplanar electrode comprises a source, a drain, and a gate.
When the stretchable synapsis device is prepared, the organic semiconductor layer is arranged on the surface of the ionic gel insulating layer, the ionic gel insulating layer is stripped from the surface of the substrate, the substrate is overturned and laminated on the prestretched stretchable composite coplanar gate substrate, then the substrate is released, the stretchable synapsis of the organic thin film transistor with the coplanar gate structure can be obtained, the ionic gel insulating layer is required to be in contact with a gate electrode when the stretchable synapsis device is laminated, and the synapsis function can be simulated by the stretchable synapsis device according to the long-range polarization effect of ionic gel and the regulation.
In this embodiment, the patterned coplanar electrodes are fabricated by spraying Carbon Nanotubes (CNTs) with a thickness of 30 nm to 100 nm in conjunction with a mask.
Alternatively, the patterned coplanar electrode is prepared by spraying silver nanowires (AgNW) in a thickness of 30 nm to 100 nm in conjunction with a mask plate.
In this embodiment, the corrugated (wave-shaped) organic semiconductor layer is obtained by transferring the semiconductor layer to a pre-stretched stretchable composite coplanar gate substrate and then releasing it. The wrinkle-shaped (wave-shaped) nanofiber organic semiconductor layer can absorb external force, relieve mechanical damage of the external force to the film and improve the mechanical stability of the film, so that the stretching capacity of the device is improved.
In the embodiment, the organic semiconductor layer is a nanofiber film with a thickness of 30 nm-50 nm.
In this embodiment, the ionic gel insulation layer has a thickness of 1 μm to 3 μm, and is prepared by spin coating or blade coating. The ionic gel insulating layer has a long-range polarization characteristic, so that non-alignment regulation of grid voltage to channel current carriers can be realized in a coplanar grid structure, and the limitation of alignment of a grid electrode and a source drain electrode in the traditional organic thin film transistor structure is eliminated.
In this embodiment, the organic semiconductor layer is patterned during transfer to the stretchable composite coplanar gate substrate such that the ionic gel insulating layer is in contact with the gate electrode on the stretchable composite coplanar gate substrate.
The embodiment also provides a preparation method of the stretchable synapse of the organic thin film transistor, comprising the following steps:
preparing a stretchable composite coplanar gate substrate;
preparing an ion gel insulating layer and an organic semiconductor layer;
transferring and laminating the ionic gel insulating layer and the organic semiconductor layer onto a pre-stretched stretchable composite coplanar gate substrate;
releasing the pre-stretched stretchable composite coplanar gate substrate.
In this embodiment, the organic semiconductor layer is patterned while the ion gel insulating layer and the organic semiconductor layer are transfer laminated onto the stretchable composite coplanar gate substrate such that the ion gel insulating layer is in contact with the gate electrode on the stretchable composite coplanar gate substrate during lamination.
The preparation method specifically comprises the following steps:
step S11: cleaning a substrate and carrying out appropriate surface treatment, wherein the substrate is made of glass or a silicon wafer;
step S12: preparing a patterned coplanar electrode on the substrate by adopting a spraying process and combining a mask plate, wherein the thickness of the electrode is 30 nm to 100 nm, and the length and the width of a channel between a source electrode and a drain electrode are respectively 1 mm and 30 micrometers;
step S13: preparing a PDMS film on the coplanar electrode by adopting a spin coating or blade coating process;
step S14: peeling the PDMS film from the substrate to obtain a stretchable composite coplanar gate substrate;
step S15: preparing an ion gel insulating layer on the substrate in the step S11 by adopting a spin coating or blade coating process;
step S16: preparing an organic semiconductor layer on the surface of the ionic gel insulating layer by adopting a spin coating or blade coating process;
step S17: peeling the ion gel insulating layer from the substrate, overturning the ion gel insulating layer, transferring and laminating the ion gel insulating layer onto the stretchable composite coplanar gate substrate prepared in the pre-stretching step S14, and ensuring the ion gel insulating layer to be in contact with the gate electrode during lamination;
step S18: slowly releasing the pre-stretched stretchable composite co-planar gate substrate in step S17.
Specifically, in step S11, the method for cleaning the substrate includes: ultrasonic cleaning in acetone, isopropanol and deionized water for 5-10 min, and blowing with nitrogen for use, wherein the surface treatment method comprises the following steps: plasma treatment for 5-10 min or octadecyl Octyl Trichlorosilane (OTS) treatment for about 20 min; OTS treatment process: mixing OTS and toluene in a certain volume ratio in a clean culture dish, putting the mixture into a substrate to be treated, heating and fumigating for about 20 min, taking out a treated sample, washing the treated sample with toluene and isopropanol respectively, and drying the sample with nitrogen for later use;
in step S12, a specific method of preparing the patterned coplanar electrode is: adjusting the distance between a thimble and a nozzle of the spray gun, placing the substrate on a heating table at 120 ℃ for preheating, fixing a mask plate on the surface of the sample, spraying, and annealing the prepared electrode at 150 ℃ at 120 ℃ after spraying to improve the conductivity of the electrode; the selected carbon nano tube spraying solution is prepared by uniformly mixing a carbon nano tube stock solution and deionized water according to a certain volume ratio and then standing for later use; the selected silver nanowire spraying solution is prepared by diluting a silver nanowire stock solution with isopropanol and standing for later use;
in step S13, the method for preparing the PDMS film includes: uniformly mixing PDMS stock solution and a cross-linking agent according to a certain mass ratio, vacuumizing to remove bubbles in the mixed solution, and standing for later use; spin-coating or blade-coating a PDMS film on the substrate with the electrode prepared in the step S12, and then annealing at 60-80 ℃ in a vacuum box for at least 24 h;
in step S15, the method for preparing the ionic gel film includes: spin-coating an ion gel insulating layer on the substrate in the step S11 at a certain rotation speed for about 60S, and after the spin-coating is finished, placing the obtained film in a vacuum box for annealing at 80-110 ℃ for at least 12 h;
in step S16, the specific method for preparing the organic semiconductor layer is: spin-coating an organic polymer semiconductor layer P3HT-NF on the insulating layer at the rotating speed of 800-1000 rpm for about 60 s, and annealing in a vacuum box at about 150 ℃ for 10-15 min after the spin-coating is finished; preparation of organic semiconductor solution: selecting trichloromethane as a solvent, preparing a P3HT solution with a certain concentration, then placing the solution on a heating table for heating to accelerate the dissolution of P3HT, mixing the completely dissolved P3HT solution and tetrahydrofuran according to a certain volume ratio, stirring the mixed solution at a high speed and by magnetic force for at least 12 hours, and standing for later use.
In particular, two specific embodiments are provided in the following description and the accompanying drawings.
The first embodiment.
As shown in fig. 1, the present embodiment provides a stretchable synapse structure based on an organic thin film transistor, the device includes, from bottom to top, a stretchable composite coplanar gate substrate 140, an ion gel insulating layer 130, and an organic semiconductor layer 120; wherein, the stretchable composite coplanar gate substrate is composed of a PDMS film 100 and a patterned coplanar electrode 110; the organic semiconductor layer is arranged on the surface of the ionic gel insulating layer, the ionic gel film is laminated on the surface of the prestretched stretchable composite coplanar gate substrate after being stripped from the surface of the substrate, and then the stretchable synapse with the transistor structure is obtained through slow release, wherein the ionic gel is ensured to be in contact with the gate 150 during lamination; the corrugated fiber semiconductor layer obtained after slow release can absorb external force, and the tensile stability of the film is improved. The ion gel insulating layer has the characteristic of long-range polarization in the structure, so that the regulation and control effect of grid voltage on channel current carriers can be realized through the coplanar grid structure, and the limitation that a grid electrode in the traditional structure needs to be aligned with a source electrode and a drain electrode is eliminated. Meanwhile, the grid voltage can regulate and control the migration of ions in the ionic gel film, so that the migration of the ions in the ionic gel film can be controlled and the number of channel carriers can be regulated and controlled by regulating and controlling the grid voltage, and the magnitude of source-drain current is finally influenced and used for simulating the performance of synapse.
As shown in fig. 2, the stretchable composite coplanar gate substrate 140 provided in this embodiment is composed of a coplanar electrode 110 and a PDMS film 100.
The organic semiconductor layer selected in this embodiment is a nanofiber film prepared by blending a P3HT solution and tetrahydrofuran.
As a preferred solution of this embodiment, the patterned coplanar electrode 110 is prepared by spraying Carbon Nanotubes (CNTs) with a thickness of 30 nm to 100 nm in combination with a mask plate, wherein the length and width of a channel between the patterned source and drain electrodes are 1 mm and 30 μm, respectively; the PDMS film 100 is prepared by spin coating or doctor blading and has a thickness of 3 mm to 5 mm.
The material of the insulating layer 130 is ionic gel, and is prepared by spin coating or blade coating, and the thickness is 1 μm to 3 μm.
The ionic gel insulating layer 130 has a long-range polarization characteristic, so that non-alignment regulation of a channel carrier by gate voltage can be realized in a coplanar gate structure, and the limitation of alignment of a gate electrode and a source drain electrode in the traditional organic thin film transistor structure is eliminated.
The ion-gel insulating layer 130 is transferred and laminated in contact with the gate electrode 150 in the coplanar gate structure.
The organic semiconductor layer 120 is a wavy nanofiber film having a thickness of 30 nm to 50 nm.
The undulating nanofiber organic semiconductor layer is prepared by transferring the semiconductor layer 120 to a pre-stretched stretchable substrate 140 and then releasing it.
The wavy nanofiber organic semiconductor layer can absorb external force, relieve mechanical damage of the external force to the film and improve the mechanical stability of the film, so that the stretching capacity of the device is improved.
The preparation scheme of this example is as follows:
step S11: cleaning a substrate and carrying out appropriate surface treatment, wherein the substrate is made of glass or a silicon wafer;
step S12: preparing a patterned carbon nano tube coplanar electrode 110 on the substrate by adopting a spraying process and combining a mask plate, wherein the thickness of the electrode is 30 nm to 100 nm, and the length and the width of a channel between a source electrode and a drain electrode are respectively 1 mm and 30 micrometers;
step S13: preparing a PDMS film 100 on the coplanar electrode 110 by adopting a spin coating or blade coating process;
step S14: peeling the PDMS film from the substrate to obtain a stretchable composite coplanar gate substrate 140;
step S15: preparing an ion gel insulating layer 130 on the substrate in the step S11 by adopting a spin coating or blade coating process;
step S16: preparing an organic semiconductor layer 120 on the surface of the ionic gel insulating layer by adopting a spin coating or blade coating process;
step S17: peeling the ionic gel insulating layer from the substrate and transfer-laminating the ionic gel insulating layer onto the stretchable composite coplanar gate substrate 140 prepared in the pre-stretching step S14, wherein the ionic gel insulating layer and the gate electrode are in contact with each other when the ionic gel insulating layer and the gate electrode are laminated;
step S18: the pre-stretched stretchable composite coplanar gate substrate 140 in the slow release step S17.
More preferably, in step S11, the substrate has a size of 1.5 cm × 2 cm, and the cleaning method is as follows: respectively ultrasonically cleaning in acetone, isopropanol and deionized water for ten minutes, and then blowing the mixture by using nitrogen for standby, wherein the surface treatment method comprises the following steps: plasma treatment for 10 min or OTS treatment for 20 min; OTS treatment process: octadecyloctyltrichlorosilane (OTS) and toluene were added to a clean petri dish in 23 μ l: 10 ml of the mixture is put into a substrate to be processed, heated at 60 ℃ for 20 min, taken out and processed, and respectively washed by toluene and isopropanol and dried by nitrogen for standby;
in step S12, a specific method of preparing the patterned coplanar electrode 110 is: adjusting the distance between a thimble and a nozzle of a spray gun, placing the substrate on a 120 ℃ heating table for preheating, fixing a mask plate on the surface of a sample, spraying, and annealing the prepared electrode at 150 ℃ after spraying is finished so as to improve the conductivity of the electrode; the selected carbon nano tube spraying solution is prepared from the following components in percentage by weight: stock solution carbon nanotube: deionized water =1 ml: 20 ml, mixing evenly and standing for standby;
in step S13, the method for preparing the PDMS film 100 includes: PDMS stock solution and a cross-linking agent were mixed according to a ratio of 1: 10, vacuumizing to remove bubbles in the mixed solution, and standing for later use; spin-coating or blade-coating a PDMS film on the substrate with the electrode prepared in the step S12, and then annealing for 24 h at 80 ℃ in a vacuum box;
in step S15, the method for preparing the ion gel insulation layer 130 thin film includes: spin-coating the ion gel insulating layer 130 on the substrate in the step S11 at 500 rpm for 60S, and after the spin-coating is finished, placing the obtained film in a vacuum box for annealing at 110 ℃ for 12 h;
in step S16, the specific preparation method of the organic semiconductor layer 120 is: spin-coating an organic polymer semiconductor layer P3HT-NF on the insulating layer 130 at 1000 rpm for 60 s, and annealing in a vacuum box at 150 ℃ for 10 min after the spin-coating is finished; preparation of organic semiconductor solution: selecting trichloromethane as a solvent, preparing a 10 mg/ml P3HT solution, then placing the solution on a heating table, heating at 45 ℃ for 8 hours, and mixing the completely dissolved P3HT solution with tetrahydrofuran according to a volume ratio of 1: 5, mixing, magnetically stirring the blended solution at the rotating speed of 700 rpm for 12 hours, and standing for later use.
Example two.
As shown in fig. 3 and 4, the present embodiment differs from the first embodiment only in that the carbon nanotubes 110 are replaced with silver nanowires 111 in the coplanar electrode in terms of the device structure. Since the silver nanowires 111 have good spraying characteristics and good conductive ability and other functional layers are the same, the principle of the present embodiment is the same as that of the first embodiment.
In this example, the following preparation protocol is provided:
step S21: cleaning a substrate and carrying out appropriate surface treatment, wherein the substrate is made of glass or a silicon wafer;
step S22: preparing a patterned silver nanowire coplanar electrode 111 on the substrate by adopting a spraying process and combining a mask plate, wherein the thickness of the electrode is 30 nm to 100 nm, and the length and the width of a channel between a source electrode and a drain electrode are respectively 1 mm and 30 micrometers;
step S23: preparing a PDMS film 100 on the coplanar electrode 111 by adopting a spin coating or blade coating process;
step S24: peeling the PDMS film from the substrate to obtain a stretchable composite coplanar gate substrate 140;
step S25: preparing an ion gel insulating layer 130 on the substrate in the step S21 by adopting a spin coating or blade coating process;
step S26: preparing an organic semiconductor layer 120 on the surface of the ionic gel insulating layer by adopting a spin coating or blade coating process;
step S27: peeling the ionic gel insulating layer from the substrate and transfer-laminating the ionic gel insulating layer onto the stretchable composite coplanar gate substrate 140 prepared in the pre-stretching step S24, wherein the ionic gel insulating layer and the gate electrode are in contact with each other when the ionic gel insulating layer and the gate electrode are laminated;
step S28: the pre-stretched stretchable composite coplanar gate substrate 140 in the slow release step S27.
More preferably, in step S21, the substrate has a size of 1.5 cm × 2 cm, and the cleaning method is as follows: respectively ultrasonically cleaning in acetone, isopropanol and deionized water for ten minutes, and then blowing the mixture by using nitrogen for standby, wherein the surface treatment method comprises the following steps: plasma treatment for 10 min or OTS treatment for 20 min; OTS treatment process: octadecyloctyltrichlorosilane (OTS) and toluene were added to a clean petri dish in 23 μ l: 10 ml of the mixture is put into a substrate to be processed, heated at 60 ℃ for 20 min, taken out and processed, and respectively washed by toluene and isopropanol and dried by nitrogen for standby;
in step S22, a specific method of preparing the patterned coplanar electrode 111 is: adjusting the distance between a thimble and a nozzle of a spray gun, placing the substrate on a 120 ℃ heating table for preheating, fixing a mask plate on the surface of a sample, spraying, and annealing the prepared electrode at 150 ℃ after spraying is finished so as to improve the conductivity of the electrode; spraying a solution on the selected silver nanowires, diluting 5 mg/ml stock solution to 0.5 mg/ml by using a solvent isopropanol, and standing for later use;
in step S23, the method for preparing the PDMS film 100 includes: PDMS stock solution and a cross-linking agent were mixed according to a ratio of 1: 10, vacuumizing to remove bubbles in the mixed solution, and standing for later use; spin-coating or blade-coating a PDMS film on the substrate with the electrode prepared in the step S22, and then annealing for 24 h at 80 ℃ in a vacuum box;
in step S25, the method for preparing the ion gel insulation layer 130 thin film includes: spin-coating the ion gel insulating layer 130 on the substrate in the step S21 at 500 rpm for 60S, and after the spin-coating is finished, placing the obtained film in a vacuum box for annealing at 110 ℃ for 12 h;
in step S26, the specific preparation method of the organic semiconductor layer 120 is: spin-coating an organic polymer semiconductor layer P3HT-NF on the insulating layer 130 at 1000 rpm for 60 s, and annealing in a vacuum box at 150 ℃ for 10 min after the spin-coating is finished; preparation of organic semiconductor solution: selecting trichloromethane as a solvent, preparing a 10 mg/ml P3HT solution, then placing the solution on a heating table, heating at 45 ℃ for 8 hours, and mixing the completely dissolved P3HT solution with tetrahydrofuran according to a volume ratio of 1: 5, mixing, magnetically stirring the blended solution at the rotating speed of 700 rpm for 12 hours, and standing for later use.
The foregoing is directed to preferred embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. However, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the present invention are within the protection scope of the technical solution of the present invention.
Claims (10)
1. The stretchable synapse based on the organic thin film transistor is characterized by sequentially comprising a stretchable composite coplanar gate substrate, a wrinkled organic semiconductor layer and an ionic gel insulating layer from bottom to top.
2. The stretchable synapse of claim 1, wherein the stretchable composite coplanar gate substrate is comprised of a polydimethylsiloxane film with patterned coplanar electrodes disposed thereon.
3. The stretchable synapse of claim 2, wherein the patterned coplanar electrodes are fabricated by carbon nanotube sputtering in conjunction with a mask plate, and have a thickness of 30 nm to 100 nm.
4. The stretchable synapse of claim 2, wherein the patterned coplanar electrodes are fabricated by spraying silver nanowires with a thickness of 30 nm to 100 nm in combination with a mask.
5. The stretchable synapse of claim 1, wherein the corrugated organic semiconductor layer is formed by transferring a semiconductor layer to a pre-stretched stretchable composite coplanar gate substrate and then releasing.
6. The stretchable synapse of claim 1, wherein said organic semiconductor layer is a nanofiber film having a thickness of 30 nm-50 nm.
7. The stretchable synapse of claim 1, wherein said ionic gel insulating layer has a thickness of 1 μm to 3 μm.
8. The stretchable synapse of claim 1, wherein the organic semiconductor layer is patterned during transfer onto a stretchable composite coplanar gate substrate such that the ionic gel insulating layer contacts a gate electrode on the stretchable composite coplanar gate substrate.
9. A method for preparing a stretchable synapse of an organic thin film transistor, comprising:
preparing a stretchable composite coplanar gate substrate;
preparing an ion gel insulating layer and an organic semiconductor layer;
transferring and laminating the ionic gel insulating layer and the organic semiconductor layer onto a pre-stretched stretchable composite coplanar gate substrate;
releasing the pre-stretched stretchable composite coplanar gate substrate.
10. The method of claim 9, wherein the organic semiconductor layer is patterned during the step of transferring and laminating the ionic gel insulating layer and the organic semiconductor layer onto the stretchable composite coplanar gate substrate, such that the ionic gel insulating layer is in contact with the gate electrode on the stretchable composite coplanar gate substrate during the step of laminating.
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