KR20040038143A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of preventing bridge between gate electrodes and short between gate electrodes and contact plug. CONSTITUTION: Gate electrodes(210) with a hard mask(209) are formed on a semiconductor substrate(201). An interlayer dielectric(213) is formed on the resultant structure. Contact holes are formed to expose simultaneously the gate electrodes and the substrate. The contact hole is filled with a polysilicon layer. The polysilicon layer is firstly polished to expose the interlayer dielectric. A photoresist pattern is formed to expose the polysilicon layer between the gate electrodes. Dopants are implanted into the exposed polysilicon layer to enhance the polishing selectivity with the hard mask. The polysilicon layer and the interlayer dielectric are secondly polished to expose the gate electrode.

Description

Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing a short circuit between the gate electrode, the bit line contact plug, and the storage contact plug while achieving complete separation between the LPPs. will be.

As the integration of semiconductor devices proceeds, not only the cell area but also the size of the contact hole decreases. As a result, it has been difficult to form contact holes for electrically connecting the silicon substrate and the bit line and between the silicon substrate and the capacitor. Thus, in order to solve the above-mentioned difficulties, self-aligned contacts have recently been developed. Contact: Hereinafter, the SAC) process is proposed / applied.

The SAC process forms a contacting plug (LPC) that simultaneously exposes a portion of a cell region where a bit line and a capacitor are to be formed, and then plugs a bitline and a capacitor plug (LPP) into the contact hole. Is embedded in the process to facilitate electrical connection between the bit line and capacitor to be formed subsequently and the silicon substrate.

1A to 1D are cross-sectional views of respective processes for describing a method of manufacturing a semiconductor device according to the related art using a SAC process, which will be described below.

Referring to FIG. 1A, a gate insulating film 5, a gate conductive film 7, and a hard mask film 9 are sequentially formed on a semiconductor substrate 1 having device isolation layers 3 defining an active region. The gate films 10 are patterned to form several gate electrodes 10.

Then, for example, nitride film spacers 11 are formed on both side walls of the gate electrode 10 according to a known process, and then predetermined impurities are ion implanted into the exposed semiconductor substrate 1 to form a junction region ( Not shown). Next, an interlayer insulating film 13 is deposited on the substrate resultant.

Referring to FIG. 1B, a contact hole (LPC) 15 for simultaneously exposing a portion of a cell region where a bit line and a capacitor are to be formed is formed. Then, a plugging polysilicon layer (LPP) 17 is deposited on the interlayer insulating layer 13 to fill the LPC 15. At this time, the interlayer insulating layer 13 and the LPP 17 have a step due to the gate electrodes 10.

Referring to FIG. 1C, the LPP 17 is primarily chemical mechanical polishing (CMP) using a basic slurry so that the surface of the interlayer insulating layer 13 is exposed, and thus the step between the LPP 17 and the interlayer insulating layer 13 is increased. Remove it.

Referring to FIG. 1D, the LPP and the interlayer insulating layer 13 are secondly CMPed using an acid slurry to expose the surfaces of the gate electrodes 10 to form a contact plug 19 while completely separating the LPP. do.

In the above, when the LPP 17 is completely separated from the gate electrode 10 only by using a CMP process using a basic slurry, since the polishing rate of the interlayer insulating layer 13 is high, the gate electrode 10 and the gate electrode ( Dishes are generated in the interlayer insulating film 13 between the layers 10, and thus, a phenomenon in which an oxide slurry remains in the portion where the dishing occurs is generated. At this time, since the oxidizing slurry is metallic, it is not removed even in a subsequent cleaning process, and as shown in FIG. 2, a bridge between the gate electrodes is generated.

Therefore, the step removal of the LPP 17 and the interlayer insulating film 13 is preferably divided into CMP using a basic slurry and CMP using an acidic slurry.

Subsequently, although not shown, a known subsequent process is performed to form bit lines and storage nodes that are each electrically connected to the junction regions by contact plugs, thereby completing the fabrication of unit cells in DRAM devices, for example. do.

However, in the conventional manufacturing method as described above, when CMP of the LPP and the interlayer insulating film using an acidic slurry to expose the surfaces of the gate electrodes, dishing of the interlayer insulating film between the gate electrode and the gate electrode is performed using a basic slurry. Although less than that of CMP, the difference in the polishing selectivity between the LPP and the gate electrode is reduced so that the bridge phenomenon occurs between the gate electrodes due to the LPP.

In addition, if the polishing amount is increased for complete separation between the LPPs, the thickness of the hard mask film, that is, the nitride film, of the gate electrode may be reduced, and may be removed in severe cases. Short between the bit line contact plug and the gate electrode and the storage contact plug occurs.

Accordingly, the present invention has been made to solve the above problems, and provides a method of manufacturing a semiconductor device capable of preventing the occurrence of a short between the gate electrode, the bit line contact plug and the storage contact plug while achieving complete separation between the LPPs. Has its purpose.

1A to 1D are cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor device according to the prior art.

2 is a photograph showing a bridge phenomenon between gate electrodes.

3A to 3E are cross-sectional views of respective processes for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on main parts of drawing

201: semiconductor substrate 203: device isolation film

205 gate insulating film 207 gate conductive film

209: hard mask film 210: gate electrode

211: spacer 213: interlayer insulating film

215: LPC 217: LPP

219: Contact Plug

The method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of: forming a gate electrode having a nitride film on the surface on a semiconductor substrate; Depositing an interlayer insulating film on the substrate to cover the gate electrodes; Etching the interlayer insulating film to form contact holes for simultaneously exposing predetermined gate electrodes and a substrate; Depositing a polysilicon film on the interlayer insulating film to fill the contact hole; Firstly CMPing the polysilicon film to expose the interlayer insulating film; Forming a photoresist pattern that exposes portions of the polysilicon layer between the gate electrodes; Implanting impurity ions into the polysilicon film portion exposed by the photosensitive film pattern such that the polishing selectivity with the nitride film is increased; Removing the photoresist pattern; And secondly CMPing the polysilicon film and the interlayer insulating film until the gate electrode surface is exposed.

Here, the primary CMP of the polysilicon film to expose the interlayer insulating film is to maintain the rotational speed of the platen and the head of the CMP device at 30 to 150 RPM, while maintaining the membrane and retaining. ) And an inner tube with a basic slurry having a pH of 6 or more under a condition of 2 to 8 PSI, and the second CMP is performed with an acid slurry having a pH of 1 to 5 under the above conditions.

In addition, the ion implantation process injects a pentavalent element including phosphorus or arsenic into the polysilicon film portion between the gate electrodes at an injection energy of 3 to 10 KeV up to 500 to 1000 kW above the gate electrode.

According to the present invention, since an ion is implanted into the polysilicon film portion between the gate electrodes to increase the polishing selectivity with the nitride film, the polysilicon film and the interlayer insulating film are secondly CMPed to form a gap between the gate electrodes caused by the polysilicon film. The bridge phenomenon can be prevented, and the short circuit between the gate electrode, the capacitor contact plug, and the bit line contact plug can be prevented.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3D are cross-sectional views of respective processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3A, after the gate insulating layer 205, the gate conductive layer 207, and the hard mask layer 209 are sequentially formed on the semiconductor substrate 201 having the device isolation layers 203 defining the active region. The gate layers 210 are formed by patterning the layers.

Then, for example, nitride film spacers 211 are formed on both side walls of the gate electrode 210 according to a known process, and then ion implantation of predetermined impurities into the exposed semiconductor substrate 201 to form a junction region ( Not shown). Next, an interlayer insulating film 213 is deposited on the substrate resultant.

Referring to FIG. 3B, an LPC 215 is formed to simultaneously expose portions of the cell region where bit lines and capacitors are to be formed. Then, a plug-in polysilicon film, that is, an LPP 217, is deposited on the interlayer insulating film 213 to fill the LPC 215. At this time, the interlayer insulating film 213 and the LPP 217 have a step due to the gate electrodes 210.

Referring to FIG. 3C, the LPP 217 is primarily CMP by using a basic slurry so that the surface of the interlayer insulating layer 213 is exposed to remove the step between the LPP 217 and the interlayer insulating layer 213.

Here, the primary CMP is a rotational speed of the platen and the head of the CMP equipment at 30 to 150 RPM, while maintaining the pressure of the membrane, retaining and inner tube. Under conditions of 2 to 8 PSI, a basic slurry having a pH of 6 or more, and preferably 6 to 12 is used.

Referring to FIG. 3D, a photoresist pattern 218 is formed on the interlayer insulating layer 213 and the LPP 217 to expose a portion of the LPP 217 between the gate electrodes 210, and then, on the substrate resultant. An ion implantation process is performed to implant a Group 5 element such as phosphorus or arsenic into the LPP 217 exposed by the photoresist pattern 218 with energy of 3 to 10 KeV. In addition, the ion implantation process allows impurities to be implanted from a surface of the gate electrode 210 to a predetermined height, preferably 500 to 1000 mW, in consideration of an attack to the gate electrode 210.

Here, the ion implantation process breaks the lattice of the portion of the LPP 217 exposed by the photoresist pattern 218, so that the LPP 217 is compared to the hard mask layer 209 of the gate electrode 210, that is, the nitride layer. Increase the polishing selectivity of the part.

Referring to FIG. 3E, the LPP and the interlayer dielectric layer 213 are secondly CMPed using an acid slurry to expose the surfaces of the gate electrodes 210 so that the LPP is completely separated from the gate electrode. 219).

Here, the secondary CMP is a rotational speed of the platen and the head of the CMP equipment at 30 to 150 RPM, while maintaining the pressure of the membrane, retaining and inner tube. It is performed with an acidic slurry having a pH of 1 to 5 under conditions of 2 to 8 PSI.

In this case, since the LPP 219 has a higher polishing selectivity than the hard mask film 213 of the gate electrode 210 due to the ion implantation process, the hard mask film 213 on the surface of the gate electrode 210 using CMP using an acid slurry. The LPP 219 can be completely separated about the gate electrode 210 while reducing the decrease in thickness.

In addition, the present invention can significantly reduce the reduction of the thickness of the hard mask film 213 on the surface of the gate electrode 210 due to CMP using an acidic slurry, so that the gate electrode 210 is subsequently used. Short circuits with the bitline contact plugs and the storage node contact plugs can be prevented.

Subsequently, although not shown, a known subsequent process is performed to form bit lines and storage nodes that are each electrically connected to the junction regions by contact plugs, thereby completing the fabrication of unit cells in DRAM devices, for example. do.

As described above, the manufacturing method of the semiconductor device of the present invention can prevent the bridge phenomenon between the gate electrodes due to the LPP, and at the same time, it is possible to prevent the short between the gate electrode and the bit line contact plug and the storage node contact plug. The reliability and manufacturing yield of the device can be improved.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (4)

Forming gate electrodes having a nitride film on a surface of the semiconductor substrate; Depositing an interlayer insulating film on the substrate to cover the gate electrodes; Etching the interlayer insulating film to form contact holes for simultaneously exposing predetermined gate electrodes and a substrate; Depositing a polysilicon film on the interlayer insulating film to fill the contact hole; Firstly CMPing the polysilicon film to expose the interlayer insulating film; Forming a photoresist pattern that exposes portions of the polysilicon layer between the gate electrodes; Implanting impurity ions into the polysilicon film portion exposed by the photosensitive film pattern such that the polishing selectivity with the nitride film is increased; Removing the photoresist pattern; And And secondly CMPing the polysilicon film and the interlayer insulating film until the gate electrode surface is exposed. The method of claim 1, wherein the CMP of the polysilicon film is primarily performed so that the interlayer insulating film is exposed. The condition that the rotation speed of platen and head of CMP equipment is 30-150 RPM, and the pressure of membrane, retaining and inner tube is 2-8 PSI. Method for producing a semiconductor device, characterized in that performed using a basic slurry having a pH of 6 or more. The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation step implants phosphorus or arsenic with an energy of implantation energy of 3 to 10 KeV to an depth of 500 to 1000 Pa from the top of the gate electrode. The method of claim 1, wherein the second CMP of the polysilicon film and the interlayer insulating film The condition that the rotation speed of platen and head of CMP equipment is 30-150 RPM, and the pressure of membrane, retaining and inner tube is 2-8 PSI. Method for producing a semiconductor device, characterized in that carried out using an acid slurry of pH 1 to 5.