KR100714268B1 - Method for fabricating semiconductor device - Google Patents

Abstract

In the present invention, an island plate-poly pattern is introduced into a core region of a highly integrated DRAM device having a difference in level difference between a memory cell region and a core region of 1.0 μm or more, Align Contact) method, it is possible to reduce the step between the memory cell region and the core region, to prevent photo-induced sick-open fail in MC formation, to minimize the occurrence of voids in MC, And a method of manufacturing a semiconductor device.

To this end, according to the present invention, in a method for manufacturing a DRAM device having a COB structure, a first interlayer insulating film is formed on a substrate, an island P-poly pattern is formed on the insulating film to define an MC- , A second interlayer insulating film is formed thereon, and the second interlayer insulating film is etched so that the surface of the P-poly pattern is exposed using a photoresist pattern having a largely defined MC forming portion as a mask, Etching the first interlayer insulating film at the lower end of the P-poly pattern to form an MC having a structure in which the upper end is wider than the lower end, then removing the photoresist pattern and forming a W- Method is provided. At this time, since the P-poly pattern is a film quality formed together with the plate electrode of the memory cell capacitor, a separate film deposition process or an etching process is not required in forming the pattern.

Description

[0001] The present invention relates to a method for fabricating a semiconductor device,             

FIGS. 1A to 1D are a process flow chart showing a conventional method for manufacturing a DRAM device,

FIGS. 2A to 2D are process flow charts showing a method of manufacturing a semiconductor device according to the present invention,

Figures 3a and 3b are top plan views of the island P-poly pattern shown in Figure 2a from above.

The present invention relates to a method of manufacturing a semiconductor device, in particular, by introducing an island plate-poly pattern into a core area of a highly integrated DRAM device, (Self Align Contact) method, it is possible to reduce a step between a memory cell area and a core area and prevent a photo-sickness-not-open fail during MC formation And more particularly, to a method of manufacturing a semiconductor device.                         

As semiconductor devices become more highly integrated, the chip size is reduced and the area occupied by the capacitor within the same occupied area is reduced while designing the DRAM device to realize a large memory, while increasing the height of the capacitor to maximize the capacitance Technology is being developed.

However, when the device is designed as described above, the step height between the memory cell region and the core region becomes large due to the height of the capacitor formed in the memory cell region, so that when MC is formed at a slope portion between the cell region and the core region, (Under Depth Of Focus) margins become weak, causing problems such as photo sickness - open fail.

Hereinafter, a conventional semiconductor device manufacturing method shown in FIGS. 1A to 1D will be described with reference to a process flow diagram. Here, as an example, a case where a memory cell has a COB structure will be described. In the figure, a portion denoted by A represents a memory cell region of a DRAM device, and a portion denoted by B represents a peripheral circuit portion of the DRAM device, that is, a core region.

1A, a field oxide film 12 is formed in a device isolation region on a semiconductor substrate 10 to define an active region in which an active device is to be formed. Then, an active region is formed on the substrate 10 and a field oxide film 12 A gate electrode 14 made of polycide (or polysilicon) having a gate insulating film (not shown) is formed at a predetermined portion. Next, a low concentration impurity is ion-implanted onto the substrate 10, spacers 16 made of an insulating film are formed on both sidewalls of the gate electrode 14, and ions of a high concentration are implanted into the substrate 10 A source / drain region (not shown) having a lightly doped drain (LDD) structure is formed in the substrate 10 on both edge sides of the gate electrode 14. As a result, the transistor of the illustrated type is completed.

A buffer oxide film 18 is formed on the gate electrode 14 of the memory cell region A, the field oxide film 12 and the substrate 10 and a first interlayer insulating film (for example, BPSG) After forming the insulating film 20, it is reflowed at a predetermined temperature. The reason why the buffer oxide film 18 is further processed in this manner is that the boron B or phosphorus (B) implantation into the gate electrode 14, which may occur when the first interlayer insulating film 20 is formed of a high- P) ions in the memory cell region A and a plasma damage caused by the film quality deposition.

A DC (Direct Contact) 21 is formed by selectively etching a predetermined portion of the first interlayer insulating film 20 so that the surface of the substrate 10 in the bit line forming portion is exposed and the first interlayer insulating film 20 A bit line 22 is formed in the memory cell region A by selectively etching the first interlayer insulating film 20 so that the surface of the first interlayer insulating film 20 is partially exposed.

A second interlayer insulating film 24 made of a high-temperature oxide film (for example, BPSG) is formed on the first interlayer insulating film 20 including the bit line 22, reflowed at a predetermined temperature, The buried contact 25 is formed by selectively etching the second and first interlayer insulating films 24 and 20 so that the surface of the first interlayer insulating film 24 and the second interlayer insulating film 24 may be exposed to predetermined portions, A conductive film of a polysilicon material doped with a high concentration impurity is formed on the insulating film 24, and then the conductive film is selectively etched to form the storage electrode 26 in the memory cell region A. A dielectric film 28 is formed on the top and side surfaces of the storage electrode 26 and a polysilicon conductive film doped with a high concentration of impurities is formed on the second interlayer insulating film 24 including the dielectric film 28 And the plate electrode 30 is formed by selective etching.

As a result, a stacked capacitor 32 made up of the storage electrode 26, the dielectric film 28, and the plate electrode 30 is formed in the memory cell region A. At this time, the storage electrode 26 constituting the capacitor 32 should be formed to have a height of at least 7000 angstroms in order to secure the capacitance of the capacitor to at least 30 fF / cell because of the product characteristics of the DRAM cell.

A third interlayer insulating film 34 made of a high-temperature oxide film (for example, BPSG) is formed on the second interlayer insulating film 24 including the capacitor 32. The third interlayer insulating film 34 is reflowed at a predetermined temperature, A photoresist pattern 36 is formed on the third interlayer insulating film 34 to define an MC forming portion.

As a second step, a third interlayer insulating film (not shown) is formed so as to expose a predetermined portion of the surface of the active region between the gate electrodes 14 formed in the core region B using the photoresist pattern 36 as a mask, 34, the second interlayer insulating film 24, and the first interlayer insulating film 20 are sequentially etched to form the MC 38.

As a third step, the photoresist pattern 36 is removed as shown in FIG.

As a fourth step, a W-plug 40 is formed in the MC contact 38 as shown in FIG. 1D, and on the third interlayer insulating film 34 including the W- A metal film made of an Al alloy is formed and then a metal wiring 42 is formed in each of the memory cell area A and the core area B by selective etching to complete the process. At this time, the metal wiring 42 of the core region B is formed to be electrically connected to the W-plug 40.

That is, in the conventional DRAM device, a global step between the memory cell region A and the core region B is opened by at least 1.0 μm due to the capacitor, and the etching process using the photoresist pattern as a mask It can be seen that the process progresses so that the MC 38 is formed.

Therefore, when the DRAM is manufactured by applying the above process as it is, the following problems arise in manufacturing the device.

In general, since the DRAM region has a step value lower than 1.0 占 퐉 in the core region B as compared with the memory cell region A in which the stacked capacitor is formed, It is impossible to find a photo margin that can satisfy both the low step portion and the high step portion in the photo etching process.

As a result, when forming the photoresist pattern 36 that defines the MC forming portion in the inclined portion between the memory cell region A and the core region B, the UDOF margin becomes weak, and the sectional profile thereof can be reproduced in a desired shape There is a defect that the photoresist pattern is formed so that the MC formation is opened smaller than the set value.

When the defect is generated, the difference in level difference between the memory cell region A and the core region B is large, so that the photoresist pattern 36 can not act as a mask when etching the interlayer insulating film for MC formation, There is a problem that a photoresistive sick-open fail may be caused due to insufficient etching in some cases, and a void may be generated in the MC when the W plug is formed in some cases. Therefore, there is an urgent need for an improvement thereto.

It is an object of the present invention to provide an island P-poly pattern for defining an MC forming portion in a core region by utilizing a node resistance or a polysilicon film used as a plate electrode of a capacitor in the manufacture of a DRAM device, (SAC) method by a P-poly pattern, thereby reducing a step between the memory cell and the core region, preventing the photo-induced sick-open fail caused by the UDOF margin weakness during MC formation, Thereby preventing voids from being formed during W-plug formation.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a first interlayer insulating film on a semiconductor substrate having a field oxide film and a transistor; Forming a DC by selectively etching the first interlayer insulating film so that the surface of the substrate of the bit line forming unit is exposed at a predetermined portion; Forming a conductive film on the first interlayer insulating film including the DC, and selectively etching the conductive film to form bit lines; Forming a second interlayer insulating film on the first interlayer insulating film including the bit line; Forming BC by sequentially etching the second and first interlayer insulating films so that the surface of the substrate of the capacitor forming unit is exposed; Forming a storage capacitor for a cell capacitor and a dielectric film on a predetermined portion of the second interlayer insulating film including the BC; A conductive polysilicon conductive film doped with a high concentration impurity is formed on the resultant, and then a plate electrode for a cell capacitor is formed in the memory cell region by selective etching, and an island P-poly pattern is formed in the core region. ; Forming a third interlayer insulating film on the resultant product; Forming a photoresist pattern having an open area larger in size than MC to be formed on the third interlayer insulating film; The third interlayer insulating film is etched so that the surface of the P-poly pattern is exposed using the photoresist pattern as a mask, and then the second and first interlayer insulating films at the lower end of the P-poly pattern are sequentially etched, Forming a MC having a wider structure than the lower end; Removing the photoresist pattern; And forming a W-plug in the MC.

At this time, the P-poly pattern is formed into a bar structure in which two thin film patterns are arranged side-by-side with a quadrangular structure having a hollow hole having the same size as the MC or an open region having the same size as the MC .

When the DRAM is manufactured by applying the above process, since the P-poly pattern is formed in the core region when the plate electrode of the memory cell capacitor is formed, and MC is manufactured by the SAC method using the P-poly pattern, It is possible to reduce the step between the cell region and the core region and to prevent the photo sickle-open fail caused by the UDOF margin vulnerability because the open portion of the photoresist pattern can be largely taken when the MC is formed. In addition, since the cross-sectional profile of the finished MC is wider at the upper end than at the lower end, the possibility of occurrence of voids in gap filling of the conductive film gap of the W material in the MC is reduced.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIGS. 2A to 2D are process flow charts showing a method of manufacturing a DRAM device proposed in the present invention. The manufacturing method will be described in the fourth step with reference to the above process flow chart. Here, as an example, a case where a memory cell of a DRAM device has a COB structure will be described. In the figure, a portion denoted by A represents a memory cell region of a DRAM device, and a portion denoted by B represents a peripheral circuit portion of the DRAM device, that is, a core region.

2A, a field oxide film 12 is formed in a device isolation region on the semiconductor substrate 10 to define an active region in which an active device is to be formed. Then, an active region is formed on the substrate 10 and the field oxide film 12 A gate electrode 14 made of polycide (or polysilicon) having a gate insulating film (not shown) is formed at a predetermined portion. Next, a low concentration impurity is ion-implanted into the substrate 10, spacers 16 made of insulating material are formed on both side walls of the gate electrode 14, and then high-concentration impurities are implanted into the substrate 10 A source / drain region (not shown) having a lightly doped drain (LDD) structure is formed in the substrate 10 on both edge sides of the gate electrode 14. As a result, the transistor of the illustrated type is completed.

A buffer oxide film 18 is formed on the gate electrode 14 of the memory cell region A, the field oxide film 12 and the substrate 10 and a first interlayer insulating film (for example, BPSG) After the insulating film 20 is formed, it is reflowed at a predetermined temperature. As described above, the buffer oxide film 18 is further fabricated by forming boron (B) or phosphorus (B) into the gate electrode 14, which may be generated when the first interlayer insulating film 20 is formed of a high- To protect the transistor of the memory cell region A from the doping of P ions and the plasma damage caused by the film quality deposition.

A DC 21 is formed by selectively etching a predetermined portion of the first interlayer insulating film 20 so that the surface of the substrate 10 in the bit line forming portion is exposed to form a conductive layer 20 on the first interlayer insulating film 20 including the DC 21, A bit line 22 is formed in the memory cell region A by selectively etching the first interlayer insulating film 20 so that the surface of the first interlayer insulating film 20 is partially exposed.

A second interlayer insulating film 24 made of a high-temperature oxide film (for example, BPSG) is formed on the first interlayer insulating film 20 including the bit line 22, reflowed at a predetermined temperature, The second and first interlayer insulating films 24 and 20 are partially selectively etched to form a BC 25 and the second interlayer insulating film 24 including the BC 25, A conductive film of a polysilicon material doped with a high concentration impurity is formed on the polysilicon layer and is selectively etched to form the storage electrode 26 in the memory cell region A. A dielectric film 28 is formed on the top and side surfaces of the storage electrode 26 and a polysilicon conductive film doped with a high concentration of impurities is formed on the second interlayer insulating film 24 including the dielectric film 28 A plate electrode is formed in the memory cell region A, and an island P-poly pattern 30a is formed in the core region B.

3A and 3B, the P-poly pattern 30a may have a rectangular shape (FIG. 3A) having a hollow hole h of the same size (L) as the predetermined MC (FIG. 3B) in which two thin film patterns are arranged side-by-side with an open region h 'of the same size (l) as that of the MC. The P-poly pattern 30a of FIG. 2A shows the X-X cross-sectional structure of FIGS. 3A and 3B.

As a result, a capacitor 32 having a stack structure composed of the storage electrode 26, the dielectric film 28, and the plate electrode 30 is formed in the memory cell region A, and the MC region B is defined in the core region B An Ir P-poly pattern 30a is formed. In this case, the storage electrode 26 constituting the capacitor 32 must be formed to have a height of at least 7000 ANGSTROM or higher, because the capacitance of the capacitor must be maintained at least 30 fF / cell due to the product characteristics of the DRAM cell.

A third interlayer insulating film 34 made of a high-temperature oxide film (for example, BPSG) is formed on the second interlayer insulating film 24 including the capacitor 32 and the P-poly pattern 30a, Then, a photoresist pattern 36 is formed on the third interlayer insulating film 34 by using a photolithography process so as to have an open region having a size (? +?) Larger than the predetermined MC. Since the P-poly pattern 30a is formed at the lower end of the open region of the photoresist pattern 36 compared to the conventional structure, the MC is manufactured by the SAC method in the subsequent process, Even if the area is somewhat larger than the conventional one, there is no problem in forming the MC, and it is also advantageous in terms of eliminating defects caused by the weakness of the UDOF margin.

As a second step, the third interlayer insulating film 34 is etched so that the surface of the P-poly pattern 30a is exposed using the photoresist pattern 36 as a mask as shown in FIG. 2B, The second interlayer insulating film 24 and the first interlayer insulating film 20 at the lower end of the P-poly pattern 30a are sequentially etched so that the upper surface of the MC layer 38 has a wider structure than the lower end do.

As a third step, the photoresist pattern 36 is removed as shown in FIG. 2C.

As a fourth step, a W-plug 40 is formed in the MC contact 38 as shown in FIG. 2D, and a metal material of an Al alloy material is formed on the third interlayer insulating film 34 including the W- The metal wiring 42 is formed in the memory cell area A and the core area B, respectively, thereby completing the present process. At this time, the metal wiring 42 of the core region B is formed to be electrically connected to the W-plug 40.

In this way, when the DRAM cell 30 is formed, the P-poly pattern 30a is left intact in the core region B having a low step difference, The step between the memory cell region A and the core region B can be reduced as well as the photoresist pattern 36 can be formed since the process is performed to form the MC 38 by the SAC method using the poly pattern 30a. It is possible to manufacture the MC 38 without short-circuiting with the lower gate electrode 14. As a result, the photo-induced sickle- Thereby preventing open failures.

In addition, in this case, since the cross-sectional profile of the final completed MC 38 has a structure in which the upper end portion is wider than the lower end portion, the effect of widening the entrance of the MC in the conductive film gap of the W material can be obtained, It is advantageous.

As described above, according to the present invention, when a plate electrode of a memory cell capacitor is formed, a P-poly pattern is formed together with an MC forming portion of a core region so that MC is manufactured by the P- It is possible to reduce steps between 1) a memory cell region and a core region, 2) a large opening portion of the photoresist pattern can be achieved without a short circuit with the gate electrode, and thus, 3) The cross-sectional profile of the MC has a wider upper end than the lower end, so that voids can be minimized during W-plug formation.

Claims (3)

Forming a first interlayer insulating film on a semiconductor substrate having a field oxide film and a transistor; Forming a DC by selectively etching the first interlayer insulating film so that the surface of the substrate of the bit line forming unit is exposed at a predetermined portion; Forming a conductive film on the first interlayer insulating film including the DC, and selectively etching the conductive film to form bit lines; Forming a second interlayer insulating film on the first interlayer insulating film including the bit line; Forming BC by sequentially etching the second and first interlayer insulating films so that the surface of the substrate of the capacitor forming unit is exposed; Forming a storage capacitor for a cell capacitor and a dielectric film on a predetermined portion of the second interlayer insulating film including the BC; A conductive polysilicon conductive film doped with a high concentration impurity is formed on the resultant, and then a plate electrode for a cell capacitor is formed in the memory cell region by selective etching, and an island P-poly pattern is formed in the core region. ; Forming a third interlayer insulating film on the resultant product; Forming a photoresist pattern having an open area larger in size than MC to be formed on the third interlayer insulating film; The third interlayer insulating film is etched so that the surface of the P-poly pattern is exposed using the photoresist pattern as a mask, and then the second and first interlayer insulating films at the lower end of the P-poly pattern are sequentially etched, Forming a MC having a wider structure than the lower end; Removing the photoresist pattern; And And forming a W-plug in the MC, wherein DC is a direct contact, BC is a buried contact, and MC is a metal conductor. 2. The method of claim 1, wherein the P-poly pattern is formed in a rectangular structure having hollow holes of the same size as the MC. The method of claim 1, wherein the P-poly pattern is formed in a bar structure in which two thin film patterns are arranged side-by-side with an open region of the same size as the MC.

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