KR20040014183A - Etchant for patterning a wiring and method for manufacturing a thin film transistor array panel using the etchant - Google Patents

Abstract

PURPOSE: An etchant for interconnect and a method for fabricating a thin film display using the same are provided to minimize fabrication costs as well as simplify a fabrication process. CONSTITUTION: According to the method, a gate line(121) having a gate electrode(123) is formed on a substrate. A gate insulation film is formed on the above substrate. A semiconductor layer is formed on an upper part of the gate insulation film. A drain electrode and a data line having a source electrode are formed. And a pixel electrode(190) connected with the above drain electrode is formed. The gate line, the data line, the drain electrode, and the pixel electrode are patterned using the same etchant.

Description

Etching for wiring and method for manufacturing thin film transistor array panel using same {Etchant for patterning a wiring and method for manufacturing a thin film transistor array panel using the etchant}

The present invention relates to a wiring etchant and a method of manufacturing a thin film transistor array panel using the same. More particularly, the present invention relates to a wiring etchant for patterning a conductive film and a method of manufacturing a thin film transistor array panel used as a substrate of a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

In the liquid crystal display, in order to prevent signal delay, a gate wire or a data wire that transmits an image signal generally uses a low resistance material such as aluminum (Al) or an aluminum alloy (Al alloy) having a low resistance. Since silver contacts silicon, chrome etc. which are excellent in fire resistance are added and used. In addition, the pixel electrode is formed using indium tin oxide (ITO) or the like, which is a transparent conductive material.

The thin film transistor array panel is typically laminated with a conductive material and patterned by a photolithography process using a mask to complete a gate wiring, a data wiring, and a pixel electrode. Korean Patent Application No. 2000-2886 describes an etchant for patterning a gate electrode into a double layer of Al or Al-Nd alloy / Mo, and Korean Patent Application No. 2000-13867 describes Mo / Al or Al-. An etchant for patterning triple layers of Nd alloy / Mo is described, and Korean Patent Application No. 2001-18351 describes an etchant for patterning indium tin oxide (ITO).

However, each conductive material for wiring is patterned by applying different etching solutions or etching conditions because the characteristics of the film are different, and thus, the manufacturing process is complicated and the manufacturing cost increases because several etching conditions are applied.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for manufacturing a thin film transistor array panel using an etching solution and a wiring which can minimize manufacturing costs while simplifying a manufacturing process.

1 to 3 are photographs of the structure of the wiring after patterning various wirings using the same etchant according to the experimental example of the present invention,

4 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along the line VV ′ of FIG. 4;

6A, 7A, 8A, and 9A are layout views of a thin film transistor array panel in an intermediate process of manufacturing a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A;

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ in FIG. 7A and illustrating the next step in FIG. 6B;

FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb ′ in FIG. 8A and is a cross-sectional view showing the next step in FIG. 7B;

FIG. 9B is a cross-sectional view taken along the line IXb-IXb 'of FIG. 9A and illustrates the next step of FIG. 8B;

10 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

11 and 12 are cross-sectional views of the thin film transistor array panel illustrated in FIG. 10 taken along lines XI-XI ′ and XII-XII ′,

13A is a layout view of a thin film transistor array panel at a first stage of manufacture according to a second embodiment of the present invention;

13B and 13C are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' of FIG. 13A, respectively.

14A and 14B are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' in FIG. 13A, respectively, and are cross-sectional views in the next steps of FIGS. 13B and 13C;

FIG. 15A is a layout view of a TFT panel next to FIGS. 14A and 14B;

15B and 15C are cross-sectional views taken along the XVb-XVb 'line and the XVc-XVc' line in FIG. 15A, respectively.

16A, 17A, 18A and 16B, 17B, and 18B are cross-sectional views taken along the XVb-XVb 'line and the XVc-XVc' line in FIG. 15A, respectively, illustrating the following steps in the order of the process. ,

19A is a layout view of a thin film transistor array panel in the next step of FIGS. 18A and 18B.

19B and 19C are cross-sectional views taken along the lines XIXb-XIXb 'and XIXc-XIXc', respectively, in FIG. 19A;

20 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 21 is a cross-sectional view taken along the line XXI-XXI ′ of FIG. 20;

22A, 23, 24A, and 25A are layout views of a thin film transistor array panel in an intermediate process of manufacturing a thin film transistor array panel for a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 22B is a cross-sectional view taken along the line XXIIb-XXIIb 'of FIG. 22A;

FIG. 23B is a cross-sectional view taken along the line XXIIIb-XXIIIb 'of FIG. 23A, and is a cross-sectional view showing the next step of FIG. 22B;

FIG. 24B is a cross-sectional view taken along the line XXIVb-XXIVb 'of FIG. 24A, and is a cross-sectional view showing the next step of FIG. 23B;

FIG. 25B is a cross-sectional view taken along the line XXVb-XXVb 'of FIG. 25A and illustrates the next step of FIG. 24B.

In the method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention, the gate line, the data line, and the pixel electrode may include 50-60% phosphoric acid, 6-10% nitric acid, 15-25% acetic acid, and 2-5. Patterned with an etchant containing% stabilizer and the remaining ultrapure water.

More specifically, a gate line including a gate electrode is formed on a substrate, and a gate insulating film covering the gate line is laminated. Next, a semiconductor layer is formed over the gate insulating film, and a data line and a drain electrode having a source electrode are formed. Next, a pixel electrode connected to the drain electrode is formed. In this case, the gate line, the data line, and the pixel electrode are patterned using the same etchant.

In this case, the gate line is formed of a lower layer made of aluminum or an aluminum alloy and an upper layer of molybdenum or molybdenum alloy, the data line and the drain electrode are formed including a conductive film of molybdenum or molybdenum alloy, and the pixel electrode is formed of IZO. It is preferable.

Here, the lower layer and the upper layer are each formed to have a thickness in the range of 300-600 mW and 1,500-3,000 mW, respectively, and the data lines are formed in the thickness range of 1,500-3,000 mW, and the pixel electrode is formed at a thickness in the range of 800-1,000 mW. It is desirable to.

At this time, the etchant comprises 50-60% of phosphoric acid, 6-10% of nitric acid, 15-25% of acetic acid, and 2-5% of stabilizer and the remaining ultrapure water, and the stabilizer of oxyhydroide inorganic acid Formula is represented by M (OH) _X L _Y , M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, X is 2 or 3, L is H ₂ O, NH ₃ , CN, NH ₂ R, Y is 0, 1, 2 or 3, R is an alkyl group.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only being "on top of" another part but also having another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

In the method of manufacturing a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, the gate line, the data line, and the pixel electrode are patterned by wet etching, which is an etching condition. At this time, the etchant used includes phosphoric acid in the range of 50-60%, nitric acid in the range of 6-10%, acetic acid in the range of 15-25%, and stabilizer of 2-5% and the remaining ultrapure water. Lloyd inorganic acid is represented by the formula M (OH) _X L _Y , M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, X is 2 or 3, L is H ₂ O, NH ₃ , CN, NH ₂ R, Y is 0,1,2 or 3, and R is an alkyl group. In addition, the gate line and the data line may include a single film of molybdenum or molybdenum alloy or the like, and may include a conductive film of aluminum or aluminum alloy. In this case, in the case of forming a single film of molybdenum or molybdenum alloy, the single film is preferably formed in the range of about 1,500-3,000 kPa, and in the case of including an aluminum or aluminum alloy conductive film, the conductive film is in the range of about 300-600 kPa. It is preferable. In addition, the pixel electrode is formed of indium zinc oxide (IZO), and the thickness thereof is preferably in the range of about 800-1,000 GPa. This makes it possible to form a wiring having a profile having a good taper angle under the same etching conditions. This will be described in detail through experimental examples.

1 to 3 are photographs showing the structure of wirings after patterning various wirings using the same etchant according to the experimental example of the present invention. FIG. 1 is a pattern obtained by sequentially stacking a lower film of an Al-Nd alloy and an upper film of a MoW alloy at a thickness of about 500 kPa and 2,500 kPa, respectively. FIG. 2 is a layer of a conductive film of MoW alloy having a thickness of about 2000 kPa. 3 is a patterned photograph, and FIG. 3 is a patterned pattern after IZO is laminated to a thickness of about 900 mW. Here, the etchant was used that contains about 55% phosphoric acid, about 8% nitric acid, about 19% acetic acid, and 3% stabilizer (stabilizer), in the case of Figure 1 wet etching by the method of immersion in the etchant 2 and 3, the wet etching was performed by spraying the etchant.

As shown in FIG. 1 to FIG. 3, when the lower layer of the Al-Nd alloy and the upper layer of the MoW alloy are patterned together using one etching solution, the conductive layer of the MoW alloy is patterned, and the IZO layer is patterned. Wiring with a 50 ° taper angle could be formed.

The method of manufacturing the wiring using the etchant can be similarly applied to the method of manufacturing the thin film transistor array panel, which will be described in detail with reference to the accompanying drawings.

First, the structure of the thin film transistor array panel for a liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 4 and 5.

4 is a layout view of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 4 taken along a line V-V ′.

A gate line 121 including a lower layer 201 made of molybdenum or molybdenum alloy and an upper layer 202 made of aluminum or an aluminum alloy having low resistance is formed on the insulating substrate 110 in a tapered structure. A portion of each gate line 121 extends to form a gate electrode 123 of the thin film transistor. At this time, the gate line 121 is inclined side, the inclination angle is in the range of 20-80 ° from the horizontal plane. A portion of the gate line 121 overlaps the conductive capacitor conductor 177 connected to the pixel electrode 190 to be formed later to form a storage capacitor that improves the charge storage capability of the pixel.

According to another embodiment of the present invention, a plurality of storage electrodes (not shown) forming one electrode of the storage capacitor, which improves the charge storage capability of the liquid crystal capacitor, are formed on the substrate 110. The sustain electrode receives a predetermined voltage from the outside, such as the common electrode voltage (also referred to as "common voltage" for short). The common voltage is also applied to a common electrode (not shown) of another display panel (not shown).

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121 and the storage electrode.

On the gate insulating layer 140, a plurality of linear islands 150 formed of hydrogenated amorphous silicon are formed. A plurality of branches of each linear semiconductor 150 extends over the corresponding gate electrode 123 to form a channel of the thin film transistor. A plurality of sets of linear and island ohmic contacts 163 and 165 made of n + hydrogenated amorphous silicon doped with high concentration of silicide or n-type impurities are formed on the semiconductor 150. . Each of the islands of ohmic contact 165 is located on the opposite side of the linear ohmic contact 163 with respect to the gate electrode 123 and is separated therefrom. Sides of the semiconductor 150 and the ohmic contacts 163 and 165 have a tapered structure, and the inclination angle is in the range of 30-80 °.

On the ohmic contacts 163 and 165 and the gate insulating layer 140, a plurality of data lines 171, a plurality of drain electrodes 175 of the thin film transistor, and a plurality of conductive capacitors 177. ) Is formed. The data line 171 and the drain electrode 175 may include a conductive film made of molybdenum or molybdenum alloy, and may include a conductive film made of aluminum or an aluminum alloy like the gate line 121. The data line 171 mainly extends in the vertical direction to intersect the gate line 121 and forms a source electrode 173 having a plurality of branches extending from each data line 171. The pair of source and drain electrodes 173 and 175 are at least partially positioned on the upper portions of the ohmic contacts 163 and 165, respectively, and are separated from each other and disposed opposite to the gate electrode 123.

The storage capacitor conductor 177 overlaps the protrusion of the gate line 121.

Sides of the data line 171, the drain electrode 175, and the conductor 177 for the storage capacitor may have a tapered structure having an inclination angle in the range of 30 to 80 °.

In this case, the data line 171 and the drain electrode 175 may include a three-layer film including a conductive film of aluminum or aluminum alloy.

The ohmic contacts 163 and 165 positioned between the semiconductor 150 and the data line 171 and the drain electrode 175 lower the contact resistance therebetween.

Acrylic organic insulation having low planarity and low dielectric constant on the data line 171, the drain electrode 173, and the conductor 177 for the storage capacitor, and the semiconductor 150 and the gate insulating film 1150 that are not covered by them. A protective film 180 made of a material or a low dielectric constant insulating material having a low dielectric constant of 4.0 or less and formed by chemical vapor deposition such as SiOC or SiOF is formed. The passivation layer 180 has contact holes 185 and 187 exposing the drain electrode 175 and the conductor 177 for the storage capacitor. The passivation layer 180 also has a plurality of contact holes 189 exposing the end portion 179 of the data line 171, and together with the gate insulating layer 140, exposing the end portion 125 of the gate line 121. It has a plurality of contact holes 182. The contact holes 182 and 189 are for electrical connection between the gate line 121 and the data line 171 and a driving circuit (not shown).

At this time, the sidewalls of the contact holes 187, 182, 185, and 189 of the passivation layer 180 are preferably inclined.

Here, the passivation layer 180 may further include an insulating layer made of silicon nitride, and in this case, the insulating layer may be disposed under the organic insulating layer to directly cover the semiconductor layer 150. In addition, it is preferable to completely remove the organic insulating material from the pad portion in which the gate pad 125 and the data pad 179 are located. This structure is formed on the pad portion of the gate pad 125 and the data pad 179. The present invention is particularly advantageous when applied to a COG (chip on glass) type liquid crystal display device in which a gate driving integrated circuit and a data driving integrated circuit are directly mounted on the thin film transistor array panel to transmit scan signals and image signals, respectively.

A pixel electrode 190 made of a transparent conductive material such as indium zinc oxide (IZO) is formed on the passivation layer 180. The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact hole 185, and is also connected to the conductor 177 for the storage capacitor through the contact hole 187. The protrusion of the gate line 121 and the conductor 177 for the storage capacitor form a storage capacitor.

The pixel electrode 190 receives the data voltage from the thin film transistor and generates an electric field together with the common electrode of another display panel. When the applied voltage is changed, the molecular arrangement of the liquid crystal layer between the two field generating electrodes changes. From the point of view of the electrical circuit, the pixel electrode 190 and the common electrode form a liquid crystal dielectric capacitor that stores charge.

The pixel electrode 190 overlaps the gate line 121 and the data line 171 to increase the aperture ratio, and form a plurality of storage capacitors connected in parallel with the liquid crystal capacitor to enhance the charge storage capability.

On the other hand, a plurality of contact assistants 192 and 199 are formed on the passivation layer 180. The contact auxiliary members 192 and 199 are connected to the exposed end portions 125 and 179 of the gate line 121 and the data line 171 through the contact holes 182 and 189, respectively. The contact auxiliary members 192 and 199 protect the exposed ends 125 and 179 of the gate line 121 and the data line 171 and supplement the adhesion between the thin film transistor array panel and the driving circuit. . The contact auxiliary members 192 and 199 are formed of the same layer as the pixel electrode 190.

According to another embodiment of the present invention, a metal piece isolated in the same layer as the gate line 121 or the data line 171 adjacent to the end portions 125 and 179 of the gate line 121 and / or the data line 171. a metal island is formed, and a contact hole is formed in the gate insulating layer 140 and / or the lower insulating layer 180 thereon, and then connected to the contact auxiliary members 192 and 199.

Next, a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 6A to 9B and FIGS. 4 and 5.

6A, 7A, 8A, and 9A are layout views of a thin film transistor array panel in an intermediate process of manufacturing a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 6B is along a line VIb-VIb ′ in FIG. 6A. FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb 'in FIG. 7A and is a cross-sectional view showing the next step in FIG. 6B, and FIG. 8B is cut along the line VIIIb-VIIIb' in FIG. 8A. 7B is a cross-sectional view illustrating the next step of FIG. 7B, and FIG. 9B is a cross-sectional view of the next step of FIG. 8B taken along the line IXb-IXb ′ in FIG. 9A.

First, as shown in FIGS. 6A and 6B, the lower film 201 of molybdenum tungsten and the upper film 202 of aluminum neodymium alloy, which is a low-resistance conductive material, are disposed on the glass substrate 110 at about 500 kPa and 2,500 kPa. The upper layer 202 and the lower layer 201 were wet-etched together in a photolithography process using an etchant including an etchant (HNO ₃ : H ₃ PO ₄ : CH ₃ COOH: stabilizer and ultrapure water) in order. By patterning, the gate line 121 is formed in a tapered structure.

At this time, the etchant used includes phosphoric acid in the range of 50-60%, nitric acid in the range of 6-10%, acetic acid in the range of 15-25%, and stabilizer of 2-5% and the remaining ultrapure water. Lloyd inorganic acid is represented by the formula M (OH) _X L _Y , M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, X is 2 or 3, L is H ₂ O, NH ₃ , CN, NH ₂ R, Y is 0,1,2 or 3, and R is an alkyl group.

Next, as illustrated in FIGS. 7A and 7B, three layers of the gate insulating layer 140, the amorphous silicon layer, and the doped amorphous silicon layer are successively stacked, and the two layers are photographed to etch the upper portion of the gate insulating layer 140. A plurality of linear semiconductors 150 and a plurality of linearly doped amorphous silicon islands 160 are formed in a tapered structure.

Next, as illustrated in FIGS. 8A to 8B, a plurality of source electrodes 173 may be formed by stacking a molybdenum tungsten alloy conductive film with a thickness of about 2,000 kPa and patterning the gate line 121 by a photolithography process using an etchant patterned. A plurality of data lines 171, a plurality of drain electrodes 175, and a plurality of storage capacitor conductors 177 are formed in a tapered structure. Subsequently, portions of the doped amorphous silicon 160 that are not covered by the data line 171 and the drain electrode 175 are removed to transfer each of the doped amorphous silicon 160 to the linear and island resistive contact members 163 and 165. While separating, exposing the portion of semiconductor 150 between the two. Subsequently, in order to stabilize the surface of the exposed semiconductor 150, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 9A and 9B, silicon nitride is deposited or an organic material having excellent planarization characteristics and a photosensitive property is coated on the substrate 110 or a plasma enhanced chemical vapor deposition (PECVD) method. The protective film 180 is formed by depositing a low dielectric constant CVD film such as an a-Si: C: O film or an a-Si: O: F film. Subsequently, the gate portion 140 is patterned together with the gate insulating layer 140 by a photolithography process using a mask to form the gate portion 125, the drain electrode 175, the data portion 179, and the storage capacitor conductor 177. Form exposed contact holes 182, 185, 189, 187. In this case, in the portions exposed through the contact holes 182, 185, 189, and 187, it is preferable to remove the conductive material including aluminum in consideration of the contact characteristics of the IZO to be formed later with the pixel electrode 190.

Next, as shown in FIGS. 4 and 5, a contact hole is formed by depositing a transparent conductive material of IZO to a thickness of about 900 하고 and patterning the photolithography process using an etchant in which the gate line 121 and the data line 121 are patterned. Through the contact holes 182 and 189 and the pixel electrode 190 connected to the drain electrode 175 and the storage capacitor conductor pattern 177 through 187 and 185. An auxiliary gate contact member 92 and an auxiliary data contact member 97 respectively connected to the end portion 179 are formed.

In the method of manufacturing a thin film transistor array panel for a liquid crystal display device according to an exemplary embodiment of the present invention, the gate line, the data line, and the pixel electrode are patterned by using the same etching solution, thereby simplifying the manufacturing process and reducing manufacturing facilities. The cost can be minimized.

In addition, although the embodiment of the present invention has been described above in the manufacturing method for forming the semiconductor layer and the data line by a photolithography process using different masks, the manufacturing method according to the present invention is used to minimize the manufacturing cost. The same applies to the method of manufacturing a thin film transistor array panel for a liquid crystal display device, in which the photo data line is formed by a photolithography process using one photosensitive film pattern. This will be described in detail with reference to the drawings.

First, the unit pixel structure of the thin film transistor array panel for a liquid crystal display according to the second exemplary embodiment of the present invention will be described in detail with reference to FIGS. 10 to 12.

10 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 11 and 12 are lines XI-XI ′ and XII-XII ′, respectively, of the thin film transistor array panel illustrated in FIG. 10. A cross-sectional view taken along the line.

The thin film transistor array panel 100 according to the second exemplary embodiment of the present invention includes a plurality of storage electrode lines 131 formed on the lower insulating substrate 110, and the extension portion does not exist in the plurality of gate lines 121. Is one of its characteristics. The storage electrode line 131 is made of the same layer as the gate line 121, is substantially parallel to the gate line 121, and is electrically separated from the gate line 121. The storage electrode line 131 receives a voltage such as a common voltage together with the storage electrode 133, which is a part of the storage electrode line 131, and the plurality of drain electrodes 175 and the gate insulating layer 140 connected to the plurality of pixel electrodes 190, respectively. It faces and forms plural maintenance capacitors. When the storage capacitor generated due to the overlap of the pixel electrode 190 and the gate line 121 is sufficient, the storage electrode line 131 may be omitted or may be disposed at the edge of the pixel region in consideration of the aperture ratio of the pixel region.

In addition, a plurality of linear semiconductors 152 and a plurality of ohmic contacts 163 and 165 are provided.

The linear semiconductor 152 is substantially planar with the plurality of data lines 171 and the plurality of drain electrodes 175 except for the channel region C of the thin film transistor. That is, although the data line 171 and the drain electrode 175 are separated from each other in the channel region C, the linear semiconductor 152 is connected without disconnecting to form a channel of the thin film transistor. The ohmic contacts 163 and 165 have the same shape as the data line 171 and the drain electrode 175, respectively.

The gate line 121, the storage electrode line 131, the semiconductor layer 152, and the ohmic contacts 163 and 165 have a tapered structure.

Next, a method of manufacturing the thin film transistor array panel for the liquid crystal display device having the structure of FIGS. 10 to 12 will be described with reference to FIGS. 10 to 12 and 13A to 19C.

First, as shown in FIGS. 13A to 13C, the lower layer of molybdenum or molybdenum alloy and the upper layer of aluminum or aluminum alloy are sequentially stacked and patterned by a photolithography process using a mask to form the gate line 121 and the storage electrode line 131. ) And the sustain wiring including the sustain electrode 133 are formed in a tapered structure. At this time, the photolithography process is patterned by wet etching, and the etchant used during wet etching is 50-60% phosphoric acid, 6-10% nitric acid, 15-25% acetic acid and 2-5% stabilizer ( stabilizer) and the remaining ultrapure water, and the stabilizer is an oxyhydride inorganic acid represented by the formula M (OH) _X L _Y , where M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si, or B, X is 2 or 3, L is H ₂ O, NH ₃ , CN, NH ₂ R, Y is 0,1,2 or 3, and R is an alkyl group.

Next, as shown in FIGS. 14A and 14B, the gate insulating layer 140 made of silicon nitride, the semiconductor layer 150 of undoped amorphous silicon, and the intermediate layer 160 of doped amorphous silicon are formed by chemical vapor deposition. Continuous deposition is carried out at a thickness of 1,500 kPa to 5,000 kPa, 500 kPa to 2,000 kPa, and 1400 kPa to 600 kPa, respectively. Subsequently, a conductor layer 170 made of molybdenum or molybdenum alloy is deposited to a thickness of 1,500 kPa to 3,000 kPa by sputtering or the like, and then a photosensitive film 210 is applied thereon to a thickness of 1 μm to 2 μm.

Thereafter, the photoresist film 210 is irradiated with light through a photomask and then developed. As shown in FIGS. 15B and 15C, the photoresist film includes first and second portions 212 and 214 having different thicknesses. Patterns 212 and 214 are formed. In this case, the second portion 214 positioned in the channel region C of the thin film transistor is smaller than the first portion 212 positioned in the data region A, and the photoresist 210 portion of the other region B is thinner. Remove all or have a very small thickness. At this time, the ratio of the thickness of the second portion 214 remaining in the channel region C and the thickness of the first portion 212 remaining in the data region A depends on the etching conditions in the etching step described later. The thickness of the second portion 214 is preferably 1/2 or less of the thickness of the first portion 212, for example, 4,000 kPa or less.

As such, there may be various methods of varying the thickness of the photoresist pattern according to the position. For example, a translucent area may be added to the photomask in addition to the transparent area and the light blocking area. There is a way to put it. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal mask having only a transparent region and a light shielding region and then reflowing so that the photoresist film flows into an area where no photoresist remains.

First, as shown in FIGS. 16A and 16B, the exposed portion of the conductor layer 170 in the other region B is removed to expose the lower doped amorphous silicon layer 160. For the conductor layer 170 including aluminum or an aluminum alloy, both dry etching and wet etching methods may be used. In the case of containing chromium, wet etching using etchant such as CeNHO 3 is preferable for chromium. In the case of dry etching, the photoresist patterns 212 and 214 may also be etched to reduce the thickness. Reference numeral 178 denotes a remaining portion of the conductor layer 170. In addition, in the case of including molybdenum or molybdenum alloy or aluminum or aluminum alloy, patterning is performed by wet etching using an etchant obtained by patterning a gate line.

17A and 17B, the exposed doped amorphous silicon layer 170 portion of the other region B and the portion of the semiconductor layer 160 underneath are removed by dry etching to remove the conductive material below. 178). The second portion 214 of the photoresist pattern is removed at the same time or separately from the exposed doped amorphous silicon layer 170 portion and the semiconductor layer 160 portion. Residue of the second portion 214 remaining in the channel region C is removed by ashing. Reference numeral 152 denotes a remaining portion of the semiconductor layer 150, and reference numeral 168 denotes a remaining portion of the doped amorphous silicon layer 160.

Next, as shown in FIGS. 18A and 18B, portions of the exposed conductor 178 of the channel region C and portions of the doped amorphous silicon 168 thereunder are removed. In this case, as shown in FIG. 17B, a portion of the upper portion of the semiconductor layer 152 of the channel region C may be removed to reduce the thickness, and the first portion 212 of the photoresist pattern may also be etched to a certain thickness at this time.

In this way, each of the conductors 178 of the channel region C is completed by separating the data line 171 and the plurality of drain electrodes 175, and each of the doped amorphous silicon 168 of the channel region C is formed. A linear resistive contact member 163 and a plurality of island resistive contact members 165 are completed.

The first portion 212 of the photoresist pattern remaining in the data region A is removed after removing the exposed conductor 178 portion of the channel region C or after removing the doped amorphous silicon 168 thereunder. do.

After forming the data line 171 and the drain electrode 175 in this manner, as shown in FIGS. 19A to 19C, the same insulating material as that of the first embodiment is stacked to form the passivation layer 180, and a mask is used. The protective layer 180 is etched together with the gate insulating layer 140 to form contact holes 185, 182, and 189 that expose the drain electrode 175, the end portion 125 of the gate line, and the end portion 179 of the data line, respectively. do.

Next, as shown in FIGS. 10 to 12, the pixel electrode 190 and the end portion 125 of the gate line connected to the drain electrode 175 are deposited by depositing IZO having a thickness of 500 to 1,000 Å and wet etching using a mask. ) And a data auxiliary contact member 97 connected to the gate auxiliary contact member 92 connected to the end of the data line. In this case, as described above, patterning is performed under an etching condition using the same etching solution as that of the gate line and the data line.

In the second exemplary embodiment of the present invention, the data line 171 and the drain electrode 175, the contact members 163 and 165 and the semiconductor 152 below the data line 171 and the drain electrode 175, as well as the effect according to the first embodiment, In this process, the source electrode 173 and the drain electrode 175 may be separated to simplify the manufacturing process.

Meanwhile, in the first and second embodiments of the present invention, a manufacturing method of patterning a signal line and a pixel electrode of a single layer or a double layer including aluminum or molybdenum with a single etchant has been described. However, by adjusting the component ratio of the etchant, The signal line and the pixel electrode may be patterned by the same etchant, which will be described in detail with reference to the accompanying drawings.

20 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a third exemplary embodiment of the present invention, and FIG. 21 is a cross-sectional view taken along the line XXI-XXI ′ of FIG. 20.

20 and 21, the structure of the thin film transistor array panel according to the third exemplary embodiment of the present invention is similar to that of FIGS. 4 and 5.

However, the data line 171 and the drain electrode 175 have a tapered structure, and the first conductive film 701 made of molybdenum or molybdenum alloy, the second conductive film 702 made of aluminum or aluminum alloy, molybdenum or A third conductive film 703 made of molybdenum alloy is included.

A method of manufacturing the thin film transistor array panel according to the third exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

22A, 23, 24A, and 25A are layout views of a thin film transistor array panel in an intermediate process of manufacturing a thin film transistor array panel for a liquid crystal display according to a third exemplary embodiment of the present invention, and FIG. 22B is a line XXIIb-XXIIb 'in FIG. 22A. FIG. 23B is a cross-sectional view taken along the line XXIIIb-XXIIIb 'in FIG. 23A, and is a cross-sectional view showing the next step in FIG. 22B, and FIG. 24B is taken along the line XXIVb-XXIVb' in FIG. 24A. 23B is a cross-sectional view illustrating the next step of FIG. 23B, and FIG. 25B is a cross-sectional view of the next step of FIG. 24B taken along the line XXVb-XXVb ′ in FIG. 25A.

First, as shown in FIGS. 22A and 22B, the lower layer 201 made of molybdenum and the upper layer 202 of aluminum neodymium alloy, which is a low-resistance conductive material, are formed on the glass substrate 110. In the photo-etching process using an etchant containing an etchant (HNO ₃ : H ₃ PO ₄ : CH ₃ COOH: stabilizer and ultrapure water), the upper layer 202 and the lower layer 201 were wet-etched together. By patterning, the gate line 121 is formed in a tapered structure.

At this time, the etchant used includes phosphoric acid in the range of 65-75%, nitric acid in the range of 0.5-4%, acetic acid in the range of 9-13%, stabilizer of 2-5% and the remaining ultrapure water, and the stabilizer is oxyhydr Lloyd inorganic acid is represented by the formula M (OH) _X L _Y , M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, X is 2 or 3, L is H ₂ O, NH ₃ , CN, NH ₂ R, Y is 0,1,2 or 3, and R is an alkyl group.

At this time, the gate line 121 includes the lower layer 201 of pure molybdenum different from the first embodiment, and the same ratio of the components of the etchant but the mixing ratio is different from that of the first embodiment.

Next, as shown in FIGS. 23A and 23B, three-layer films of the gate insulating layer 140, the amorphous silicon layer, and the doped amorphous silicon layer are successively stacked in the same manner as in the first embodiment, and the above two layers are photo-etched. A plurality of linear semiconductors 150 and a plurality of linearly doped amorphous silicon islands 160 are tapered on the gate insulating layer 140.

Next, as shown in FIGS. 24A to 24B, a first conductive film 701 made of pure molybdenum, a second conductive film 702 made of aluminum neodymium alloy (Al-Nd alloy), and a third made of pure molybdenum The conductive film 703 was sequentially stacked, and an etchant containing phosphoric acid in the range of 65-75%, nitric acid in the range of 0.5-4%, acetic acid in the range of 9-13%, and stabilizer of 2-5% and the remaining ultrapure water was prepared. Patterned by the photolithography process used, a plurality of data lines 171 including a plurality of source electrodes 173, a plurality of drain electrodes 175, and a plurality of conductive capacitor conductors 177 are formed in a tapered structure.

Subsequently, portions of the doped amorphous silicon 160 that are not covered by the data line 171 and the drain electrode 175 are removed to transfer each of the doped amorphous silicon 160 to the linear and island resistive contact members 163 and 165. While separating, exposing the portion of semiconductor 150 between the two. Subsequently, in order to stabilize the surface of the exposed semiconductor 150, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 24A and 24B, the passivation layer 180 is formed as in the first and second embodiments, and then patterned together with the gate insulating layer 140 in a photolithography process using a mask, thereby ending the gate line. Contact holes 182, 185, 189, and 187 are formed to expose the portion 125, the drain electrode 175, the end portion 179 of the data line, and the conductor 177 for the storage capacitor. In this case, in the portions exposed through the contact holes 182, 185, 189, and 187, it is preferable to remove the conductive material including aluminum in consideration of the contact characteristics of the IZO to be formed later with the pixel electrode 190.

Next, as shown in FIGS. 20 and 21, a transparent conductive material of IZO is deposited to a thickness of about 900 kPa, phosphoric acid in the range of 65-75%, nitric acid in the range of 0.5-4%, acetic acid in the range of 9-13%, and 2 The pixel electrode 190 and the auxiliary electrode by patterning the gate electrode 121 and the data line 121 by a photolithography process using an etchant patterned to include the stabilizer and the remaining ultrapure water of -5%. The gate contact member 92 and the auxiliary data contact member 97 are formed, respectively.

In the method of manufacturing a thin film transistor array panel for a liquid crystal display according to the third exemplary embodiment of the present invention, the manufacturing process can be simplified by changing the component ratio of the etching solution and patterning the signal line of the multilayer film and the pixel electrode of the IZO using the same etching solution. As a result, manufacturing costs can be minimized.

The manufacturing method according to the present invention may be similarly applied to the manufacturing method of a thin film transistor array panel having a color filter on array (COA) structure in which a color filter is formed on the thin film transistor array.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, in the present invention, the gate line, the data line, and the pixel electrode are patterned by etching conditions using the same etching solution, thereby simplifying the manufacturing process and minimizing the manufacturing equipment, thereby reducing manufacturing costs.

Claims (18)

Forming a gate line having a gate electrode on the substrate, Stacking a gate insulating film on the substrate; Forming a semiconductor layer on the gate insulating layer; Forming a data line and a drain electrode having a source electrode, A method of manufacturing a thin film transistor array panel including forming a pixel electrode connected to the drain electrode. The gate line, the data line, the drain electrode, and the pixel electrode are patterned using the same etchant. In claim 1, The etchant comprises 50-60% phosphoric acid, 6-10% nitric acid, 15-25% acetic acid and 2-5% and 2-5% stabilizer and the remaining ultrapure water, Is an oxyhydride inorganic acid represented by the formula M (OH) _X L _Y , where M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, X is 2 or 3, and L is H ₂ O, NH ₃ , CN, NH ₂ R, Y is 0,1,2 or 3, and R is an alkyl group. In claim 2, And the gate line is formed of a lower layer made of aluminum or an aluminum alloy and an upper layer made of molybdenum or molybdenum alloy. In claim 3, And the data line is formed of a conductive film of molybdenum or molybdenum alloy. In claim 4, The pixel electrode is formed of IZO. In claim 5, The lower layer and the upper layer are each formed to have a thickness in the range of 300-600 mW and 1,500-3,000 mW, respectively, and the data line is formed at a thickness in the range of 1,500-3,000 mW, and the pixel electrode has a thickness in the range of 800-1,000 mW. The manufacturing method of the thin-film transistor display panel formed with the. In claim 1, The etchant comprises 65-75% of phosphoric acid, 0.5-4% of nitric acid, 9-13% of acetic acid, and 2-5% of stabilizer and the remaining ultrapure water, and the stabilizer is an oxyhydroide inorganic acid. The formula is represented by M (OH) _X L _Y , where M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, X is 2 or 3, L is H ₂ O, NH ₃ , CN, NH ₂ R, Y is 0, 1, 2 or 3, R is an alkyl group manufacturing method of a thin film transistor array panel. In claim 7, And the gate line is formed of a lower film made of aluminum or an aluminum alloy and an upper film made of molybdenum. In claim 8, And the data line is formed of a first conductive film made of molybdenum, a second conductive film made of aluminum or an aluminum alloy, or a third conductive film made of molybdenum. In claim 9, The pixel electrode is formed of IZO. Phosphoric acid in the range of 50-60%, nitric acid in the range of 6-10%, acetic acid in the range of 15-25% and stabilizer of 2-5% and the remaining ultrapure water, the stabilizer being an oxyhydroide inorganic acid (OH) _X L _Y , M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, X is 2 or 3, L is H ₂ O, NH ₃ , CN, NH ₂ R, Y is 0, 1, 2 or 3, and R is an alkyl group wiring solution. In claim 11, The wiring etching solution is a wiring etching solution used for patterning a first conductive film made of aluminum or an aluminum alloy or a second conductive film made of molybdenum or molybdenum alloy, or a multilayer including the first and second conductive films. In claim 11, The wiring etching solution is a wiring etching solution used to pattern a transparent conductive film made of IZO. Phosphoric acid in the range of 65-75%, nitric acid in the range of 0.5-4%, acetic acid in the range of 9-13%, and stabilizer of 2-5% and the remaining ultrapure water, the stabilizer being an oxyhydroide inorganic acid (OH) _X L _Y , M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, X is 2 or 3, L is H ₂ O, NH ₃ , CN, NH ₂ R, Y is 0, 1, 2 or 3, and R is an alkyl group wiring solution. The method of claim 14, The wiring etching solution is a wiring etching solution used for patterning a first conductive film made of aluminum or an aluminum alloy or a second conductive film made of molybdenum or molybdenum alloy, or a multilayer including the first and second conductive films. The method of claim 14, The wiring etching solution is a wiring etching solution used to pattern a transparent conductive film made of IZO. The method of claim 14, The wiring etching solution is a wiring etching solution used for patterning a first conductive film made of aluminum or an aluminum alloy and a multilayer film made of a second conductive film made of molybdenum and a third conductive film made of IZO together. The method of claim 14, The wiring etchant is used for patterning a three-layer foil consisting of a first conductive film of molybdenum, a second conductive film of aluminum or aluminum alloy, or a third conductive film of molybdenum.