KR20040009085A - Multi chip package and manufacturing method the same - Google Patents
Multi chip package and manufacturing method the same Download PDFInfo
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- KR20040009085A KR20040009085A KR1020020042915A KR20020042915A KR20040009085A KR 20040009085 A KR20040009085 A KR 20040009085A KR 1020020042915 A KR1020020042915 A KR 1020020042915A KR 20020042915 A KR20020042915 A KR 20020042915A KR 20040009085 A KR20040009085 A KR 20040009085A
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- Prior art keywords
- chip
- lead frame
- exposed
- die pad
- light
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000011347 resin Substances 0.000 claims abstract description 16
- 229920005989 resin Polymers 0.000 claims abstract description 16
- 238000007789 sealing Methods 0.000 claims abstract description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 13
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 238000000465 moulding Methods 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 26
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
빛을 받아서 동작하는 반도체 칩을 포함하는 멀티칩 패키지 및 그 제조방법에 관해 개시한다. 이를 위해 본 발명은, 두 개의 수평형 다이패드(die pad)를 포함하는 리드프레임과, 상기 리드프레임의 다이패드에 탑재되어 봉합수지로 덮여지는 제1 칩과, 상기 리드프레임의 나머지 다이패드에 탑재되어 봉합수지에 의해 덮여지지 않고 외부로 노출되고 빛에 의해 동작하는 특징을 갖는 제2 칩과, 상기 제1 및 제2 칩과 상기 리드프레임의 리드를 연결하는 금선과, 상기 리드프레임의 일부 및 상기 제1 칩을 봉합하고, 상기 제2 칩은 외부로 노출시키는 봉합수지를 구비하는 것을 특징으로 하는 멀티칩 패키지 및 그 제조방법에 관해 개시한다.A multichip package including a semiconductor chip operating by receiving light and a method of manufacturing the same are disclosed. To this end, the present invention provides a lead frame including two horizontal die pads, a first chip mounted on a die pad of the lead frame and covered with a sealing resin, and a remaining die pad of the lead frame. A second chip mounted and not covered by the suture resin and exposed to the outside and operated by light, a gold wire connecting the first and second chips to the lead of the lead frame, and a part of the lead frame And a sealing resin for sealing the first chip and exposing the second chip to the outside.
Description
본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로, 더욱 상세하게는 빛에 의해 동작되는 특징을 갖는 반도체 칩을 포함하는 멀티칩 패키지 및 그 제조방법에 관한 것이다.The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a multi-chip package including a semiconductor chip having a feature that is operated by light and a method for manufacturing the same.
도 1 및 도 2는 종래 기술에 의한 멀티 칩 패키지를 설명하기 위한 단면도들이다.1 and 2 are cross-sectional views illustrating a multi-chip package according to the prior art.
도 1 및 도 2를 참조하면, 도 1은 두 개의 반도체 칩(16, 14)을 리드프레임(12) 위에서 수평방향으로 구성한 멀티칩 패키지(10)이고, 도 2는 두 개의 반도체 칩(34, 36)을 수직방향으로 구성한 칩온칩(COC: Chip On Chip) 구조의 멀티칩 패키지(30)이다. 도면의 12 및 32는 리드프레임을 가리키고, 20 및 40은 봉합수지(EMC)를 각각 가리킨다.1 and 2, FIG. 1 is a multichip package 10 in which two semiconductor chips 16 and 14 are configured in a horizontal direction on a lead frame 12, and FIG. 2 shows two semiconductor chips 34, 36 is a multi-chip package 30 having a chip on chip (COC) structure having a vertical direction. 12 and 32 in the drawings indicate a lead frame, and 20 and 40 indicate a suture resin (EMC), respectively.
그러나 반도체 칩 중에서는 빛을 받아 동작을 하거나, 빛에 의하여 특별한 특성 변화를 갖는 반도체 칩이 있다. 대개 이러한 빛을 받아 동작하는 반도체 칩은 패키징(packaging)하는 방법이 다르다. 반도체 칩 상부를 노출시키고 외부로부터 빛이 반도체 칩에 도달할 수 있는 특별한 구조를 갖도록 패키징(packaging)하여야 한다. 이러한 특징 때문에 2개의 반도체 칩 중에서, 하나가 상술한 바와 같이 빛에 의해 동작하는 반도체 칩인 경우에는, 도 1 및 도 2를 구조를 적용하기가 곤란한 문제점이 있다.However, among semiconductor chips, there are semiconductor chips that operate by receiving light or have special characteristic changes by light. In general, semiconductor chips that operate under such light have a different method of packaging. It must be packaged to have a special structure that exposes the top of the semiconductor chip and allows light from outside to reach the semiconductor chip. Because of this feature, when one of the two semiconductor chips is a semiconductor chip operated by light as described above, there is a problem that it is difficult to apply the structure of FIGS. 1 and 2.
현재까지는 대부분 경우, 빛에 의해 동작하는 특징을 갖는 반도체 칩은 멀티칩 패키지로 제작이 불가능하기 때문에, 두 개의 별도 반도체 패키지로 만들어 인쇄회로기판에 실장하기 때문에 실장면적이 커지고, 제조원가가 높아지고, 신뢰성이 저하되는 문제점이 있었다.Until now, in most cases, a semiconductor chip having a characteristic of being operated by light cannot be manufactured in a multi-chip package. Therefore, since the semiconductor chip is made into two separate semiconductor packages and mounted on a printed circuit board, the mounting area is increased, manufacturing cost is increased, and reliability is achieved. There was a problem of this deterioration.
본 발명이 이루고자 하는 기술적 과제는 빛에 의해 동작하는 특징을 갖는 반도체 칩을 포함하는 멀티칩 패키지를 제공하는데 있다.An object of the present invention is to provide a multi-chip package including a semiconductor chip having a feature that operates by light.
본 발명이 이루고자 하는 다른 기술적 과제는 상기 멀티칩 패키지의 제조방법을 제공하는데 있다.Another object of the present invention is to provide a method of manufacturing the multichip package.
도 1 및 도 2는 종래 기술에 의한 멀티 칩 패키지를 설명하기 위한 단면도들이다.1 and 2 are cross-sectional views illustrating a multi-chip package according to the prior art.
도 3은 본 발명에 의한 멀티 칩 패키지 제조에 사용되는 리드프레임을 설명하기 위한 평면도이다.3 is a plan view illustrating a lead frame used in manufacturing a multi-chip package according to the present invention.
도4 내지 도 7은 본 발명에 의한 멀티칩 패키지 제조방법을 설명하기 위한 단면도들이다.4 to 7 are cross-sectional views illustrating a method of manufacturing a multichip package according to the present invention.
도 8은 본 발명에 의한 멀티칩 패키지의 변형예를 설명하기 위해 도시한 단면도이다.8 is a cross-sectional view illustrating a modified example of the multichip package according to the present invention.
상기 기술적 과제를 달성하기 위하여 본 발명은, 두 개의 수평형 다이패드(die pad)를 포함하는 리드프레임과, 상기 리드프레임의 다이패드에 탑재되어 봉합수지로 덮여지는 제1 칩과, 상기 리드프레임의 나머지 다이패드에 탑재되어 봉합수지에 의해 덮여지지 않고 외부로 노출되고 빛에 의해 동작하는 특징을 갖는 제2 칩과, 상기 제1 및 제2 칩과 상기 리드프레임의 리드를 연결하는 금선과, 상기 리드프레임의 일부 및 상기 제1 칩을 봉합하고, 상기 제2 칩은 외부로 노출시키는 봉합수지를 구비하는 것을 특징으로 하는 멀티칩 패키지를 제공한다.In order to achieve the above technical problem, the present invention provides a lead frame including two horizontal die pads, a first chip mounted on a die pad of the lead frame and covered with a suture resin, and the lead frame. A second chip mounted on the remaining die pad and exposed to the outside without being covered by the suture resin and operated by light, a gold wire connecting the first and second chips to the lead of the lead frame; A portion of the lead frame and the first chip is sealed, and the second chip provides a multi-chip package, characterized in that it comprises a sealing resin for exposing to the outside.
본 발명의 바람직한 실시예에 의하면, 상기 멀티칩 패키지는 상기 제2 칩을 덮는 코팅막을 더 구비할 수 있으며, 상기 노출된 제2 칩을 봉합하는 캡(cap)을 더 구비할 수도 있다.According to a preferred embodiment of the present invention, the multichip package may further include a coating film covering the second chip, and may further include a cap for sealing the exposed second chip.
상기 다른 기술적 과제를 달성하기 위하여 본 발명은, 두 개의 수평형 다이패드가 구비된 리드프레임을 준비하는 단계와, 상기 두 개의 다이패드중 하나에 제1 칩을 탑재하고 와이어 본딩을 수행하는 단계와, 상기 제1 칩이 와이어 본딩된 리드프레임에 몰딩을 실시하되, 칩이 탑재되지 않은 다이패드가 노출되도록 몰딩을 수행하는 단계와, 상기 노출된 다이패드에 제2 칩을 탑재하고 와이어 본딩을 수행하는 단계를 구비하는 것을 특징으로 하는 멀티칩 패키지 제조방법을 제공한다.In order to achieve the above another technical problem, the present invention provides a method for manufacturing a lead frame including two horizontal die pads, mounting a first chip on one of the two die pads, and performing wire bonding; Performing molding on the lead frame in which the first chip is wire bonded, but performing molding to expose a die pad on which the chip is not mounted, and mounting a second chip on the exposed die pad and performing wire bonding. It provides a multi-chip package manufacturing method comprising the steps of.
본 발명의 바람직한 실시예에 의하면, 상기 노출된 제2 칩에 코팅막을 형성하는 단계를 더 진행할 수도 있고, 상기 노출된 제2 칩 위에 상기 제2 칩을 덮는 캡을 형성하는 단계를 더 진행할 수도 있다.According to a preferred embodiment of the present invention, the step of forming a coating film on the exposed second chip may be further performed, or the step of forming a cap covering the second chip on the exposed second chip may further proceed. .
상기 캡은 빛이 들어올 수 있는 구멍이 하나 이상 형성된 것이 바람직하다.The cap is preferably formed with one or more holes through which light can enter.
본 발명에 따르면, 빛에 의해 동작하는 반도체 칩을 포함하는 멀티칩 패키지를 실현하여 실장면적을 줄이고, 제조원가를 줄이고, 반도체 패키지의 신뢰성을 개선할 수 있다.According to the present invention, it is possible to realize a multi-chip package including a semiconductor chip operated by light, thereby reducing the mounting area, manufacturing cost, and improve the reliability of the semiconductor package.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명은 그 정신 및 필수의 특징을 이탈하지 않고 다른 방식으로 실시할 수 있다. 예를 들면, 아래의 바람직한 실시예에 있어서 캡은, 빛이 들어올 수 있는 구멍이 있는 것을 사용하였지만, 이는 투명한 재질을 갖고 구멍을 없는 것을 사용해도 무방하다. 또한, 가장 일반적인 DIP(Dual In-Line Package)를 중심으로 설명하였지만, 이는 다른 형태의 반도체 패키지, 예컨대 SOP(Small Out-line Package), QFP(Quad Flat Package) 및 BGA(Ball Grid Array) 등으로 치환할 수 있는 것이다. 따라서, 아래의 바람직한 실시예에서 기재한 내용은 예시적인 것이며 한정하는 의미가 아니다.The invention can be practiced in other ways without departing from its spirit and essential features. For example, in the following preferred embodiment, the cap is used having a hole to which light can enter, but it may be used having a transparent material and no hole. In addition, the most common DIP (Dual In-Line Package) has been described as a center, but this is another type of semiconductor package, such as Small Out-line Package (SOP), Quad Flat Package (QFP) and Ball Grid Array It can be substituted. Therefore, the content described in the following preferred embodiments is exemplary and not intended to be limiting.
도 3은 본 발명에 의한 멀티 칩 패키지 제조에 사용되는 리드프레임을 설명하기 위한 평면도이다.3 is a plan view illustrating a lead frame used in manufacturing a multi-chip package according to the present invention.
도 3을 참조하면, 본 발명의 의한 멀티칩 패키지에 사용되는 리드프레임(120)은, 두 개의 반도체 칩을 수평으로 탑재할 수 있는 다이패드(122,124)가 나란히 형성된 것을 사용한다. 도면의 참조부호 126은 내부리드(inner lead)를 가리킨다.Referring to FIG. 3, the lead frame 120 used in the multichip package according to the present invention uses die pads 122 and 124 formed side by side to mount two semiconductor chips horizontally. Reference numeral 126 in the drawing indicates an inner lead.
도4 내지 도 7은 본 발명에 의한 멀티칩 패키지 제조방법을 설명하기 위한 단면도들이다.4 to 7 are cross-sectional views illustrating a method of manufacturing a multichip package according to the present invention.
도 4를 참조하면, 먼저 두 개의 다이 패드가 수평으로 있는 리드프레임(120)에 제1 칩(130), 즉 후속공정에서 봉합수지(EMC: Epoxy Mold Compound)로 봉합되는 반도체 칩을 다이패드(die pad)에 다이접착제를 사용하여 접착하고, 상기 제1 칩(130)과 리드프레임(120)의 내부리드를 금선(130)으로 와이어 본딩(wire bonding)한다.Referring to FIG. 4, first, a die pad includes a first chip 130, that is, a semiconductor chip sealed with an epoxy mold compound (EMC) in a subsequent process, on a lead frame 120 having two die pads horizontally. The die pad is bonded to each other using a die adhesive, and wire bonding of the inner lead of the first chip 130 and the lead frame 120 to the gold wire 130 is performed.
도 5를 참조하면, 상기 제1 칩(130)이 와이어 본딩된 리드프레임(120)에 몰딩공정(molding process)을 진행한다. 이때 봉합수지(EMC, 140)는 상기 제1 칩(130)은 봉합하되, 제2 칩(도8의 160)이 탑재되는 리드프레임(120)의 나머지 다이패드 부분(200)은 외부로 노출되도록 한다. 이렇게 제2칩(160) 탑재를 위해 노출되는 부분은 사각형, 원형 등 다양한 형태로 만들어도 무방하다.Referring to FIG. 5, a molding process is performed on the lead frame 120 to which the first chip 130 is wire bonded. At this time, the suture resin (EMC) 140 seals the first chip 130, but the remaining die pad portion 200 of the lead frame 120 on which the second chip (160 of FIG. 8) is mounted is exposed to the outside. do. The portion exposed for mounting the second chip 160 may be made in various shapes such as a rectangle and a circle.
도 6을 참조하면, 상기 노출된 리드프레임(120)의 나머지 다이패드 부분(200)에, 제2 칩(160)인 빛에 의해 동작하는 특징을 갖는 반도체 칩을 다이접착제로 부착한다. 이어서 상기 제2 칩(160)과 리드프레임의 인너리드(inner lead)를 연결하는 금선(140)을 와이어 본딩 공정으로 형성한다. 계속해서 상기 제2 칩(160) 및 노출된 금선(140)을 외부 충격으로부터 보호하기 위한 코팅막(170)을 덮는다. 상기 코팅막(170)은 빛이 투과될 수 있는 투명한 막질이 것이 적합하다.Referring to FIG. 6, a semiconductor chip having a characteristic of being operated by light, which is the second chip 160, is attached to the remaining die pad portion 200 of the exposed lead frame 120 with a die adhesive. Subsequently, a gold wire 140 connecting the second chip 160 and the inner lead of the lead frame is formed by a wire bonding process. Subsequently, the coating film 170 for protecting the second chip 160 and the exposed gold wire 140 from external impact is covered. The coating film 170 is preferably a transparent film that can transmit light.
도 7을 참조하면, 상기 도 6의 결과물 상에 상기 봉합수지(150)에 의해 노출된 부분(도5의 200)을 봉인하는 캡(cap, 180)을 씌워 봉인공정(sealing proces)를 실시한다. 상기 캡(180)은 빛이 상기 제2칩(160)에 도달할 수 있도록 구멍이 형성되어 있는 것이 적합하다.Referring to FIG. 7, a sealing process is performed by covering a cap (180) to seal a portion (200 of FIG. 5) exposed by the sealing resin 150 on the resultant of FIG. 6. . The cap 180 is suitably formed with a hole so that light can reach the second chip 160.
이하, 도 7을 참조하여 본 발명에 의한 멀티칩 패키지의 구성에 대해 설명하기로 한다. 본 발명에 의한 멀티칩 패키지는, 두 개의 수평형 다이패드(die pad)를 포함하는 리드프레임(120)과, 상기 리드프레임의 다이패드에 탑재되어 봉합수지로 덮여지는 제1 칩(130)과, 상기 리드프레임의 나머지 다이패드에 탑재되어 봉합수지에 의해 덮여지지 않고 외부로 노출되고 빛에 의해 동작하는 특징을 갖는 제2 칩(160)과, 상기 제1 및 제2 칩과 상기 리드프레임의 리드를 연결하는 금선(140)과, 상기 리드프레임의 일부 및 상기 제1 칩을 봉합하고, 상기 제2 칩은 외부로 노출시키는 봉합수지(150)로 이루어진다. 또한 상기 봉합수지(150)에 의해 상기 제2칩(160)을 노출하는 부분을 덮는 코팅막(170) 혹은 캡(180)을 더 구비할 수 있다.Hereinafter, a configuration of a multichip package according to the present invention will be described with reference to FIG. 7. The multichip package according to the present invention includes a lead frame 120 including two horizontal die pads, a first chip 130 mounted on a die pad of the lead frame and covered with a suture resin; And a second chip 160 mounted on the remaining die pad of the lead frame and not covered by the suture resin and exposed to the outside and operated by light, and the first and second chips and the lead frame. A gold wire 140 connecting a lead and a portion of the lead frame and the first chip are sealed, and the second chip is made of a sealing resin 150 that is exposed to the outside. In addition, the sealant 150 may further include a coating layer 170 or a cap 180 covering the portion exposing the second chip 160.
도 8은 본 발명에 의한 멀티칩 패키지의 변형예를 설명하기 위해 도시한 단면도이다.8 is a cross-sectional view illustrating a modified example of the multichip package according to the present invention.
도 8을 참조하면, 상술한 실시예에서는 봉합수지(150)에 의해 노출된 부분에 1차로 코팅막(170)을 사용하고 그 위에 캡(180)을 봉인(sealing)하였으나, 상기 코팅막(170)을 사용하지 않고 곧바로 캡(180)으로 봉인하는 방식으로 변형하여 적용할 수도 있다. 또한, 도시되지는 않았으나, 상기 캡(180)을 사용하지 않고 코팅막(170)만을 사용하는 방식으로 변형이 가능함은 물론이다.Referring to FIG. 8, in the above-described embodiment, the coating film 170 is primarily used in the portion exposed by the suture resin 150, and the cap 180 is sealed thereon, but the coating film 170 is sealed. It can also be applied by deforming in a manner that is sealed directly to the cap 180 without using. In addition, although not shown, it is a matter of course that the deformation is possible by using only the coating film 170 without using the cap 180.
본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함이 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.
따라서, 상술한 본 발명에 따르면, 빛에 의해 동작하는 반도체 칩을 포함하는 멀티칩 패키지를 실현하여, 첫째 반도체 패키지를 인쇄회로기판에 실장할 때에 실장면적을 줄이고, 둘째 두 개의 반도체 패키지를 하나로 통합하기 때문에 제조원가를 줄이고, 셋째 반도체 패키지의 신뢰성을 개선할 수 있다.Therefore, according to the present invention described above, by realizing a multi-chip package including a semiconductor chip operated by light, to reduce the mounting area when the first semiconductor package is mounted on a printed circuit board, the second two semiconductor packages are integrated into one Therefore, the manufacturing cost can be reduced, and the reliability of the third semiconductor package can be improved.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020042915A KR20040009085A (en) | 2002-07-22 | 2002-07-22 | Multi chip package and manufacturing method the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020042915A KR20040009085A (en) | 2002-07-22 | 2002-07-22 | Multi chip package and manufacturing method the same |
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| KR20040009085A true KR20040009085A (en) | 2004-01-31 |
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| KR1020020042915A KR20040009085A (en) | 2002-07-22 | 2002-07-22 | Multi chip package and manufacturing method the same |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0685222A (en) * | 1992-09-01 | 1994-03-25 | Sharp Corp | Solid-state image sensing device |
| JPH08107167A (en) * | 1994-10-04 | 1996-04-23 | Sony Corp | Semiconductor device |
| JPH09266369A (en) * | 1996-03-27 | 1997-10-07 | Airex:Kk | Printed circuit board and its processing |
| KR20000001953U (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Multi-chip package |
-
2002
- 2002-07-22 KR KR1020020042915A patent/KR20040009085A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0685222A (en) * | 1992-09-01 | 1994-03-25 | Sharp Corp | Solid-state image sensing device |
| JPH08107167A (en) * | 1994-10-04 | 1996-04-23 | Sony Corp | Semiconductor device |
| JPH09266369A (en) * | 1996-03-27 | 1997-10-07 | Airex:Kk | Printed circuit board and its processing |
| KR20000001953U (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Multi-chip package |
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