KR200316720Y1 - Ball grid array package - Google Patents
Ball grid array package Download PDFInfo
- Publication number
- KR200316720Y1 KR200316720Y1 KR2019980011757U KR19980011757U KR200316720Y1 KR 200316720 Y1 KR200316720 Y1 KR 200316720Y1 KR 2019980011757 U KR2019980011757 U KR 2019980011757U KR 19980011757 U KR19980011757 U KR 19980011757U KR 200316720 Y1 KR200316720 Y1 KR 200316720Y1
- Authority
- KR
- South Korea
- Prior art keywords
- lead
- grid array
- lead frame
- ball grid
- array package
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 고안은 볼 그리드 어레이 패키지를 개시한다. 개시된 본 고안은, 밑면에 패드를 갖는 반도체 칩(10)의 상부면에 리드 프레임(20)의 인너 리드(21)가 부착되고, 금속 와이어(50)에 의해 패드와 리드 프레임(20)이 연결된다. 리드 프레임(20)의 아우터 리드(22) 밑면이 노출되도록, 봉지제(30)로 몰딩된다. 노출된 아우터 리드(22)에 솔더 볼(60)이 부착된 구조로 이루어져서, 기판 사용으로 인한 휘어짐과 박리 현상을 방지된다.The present invention discloses a ball grid array package. In the disclosed subject matter, the inner lead 21 of the lead frame 20 is attached to the upper surface of the semiconductor chip 10 having the pad on the bottom thereof, and the pad and the lead frame 20 are connected by the metal wire 50. do. The bottom surface of the outer lead 22 of the lead frame 20 is molded with an encapsulant 30 so as to be exposed. Since the solder ball 60 is attached to the exposed outer lead 22, the bending and peeling phenomenon due to the use of the substrate is prevented.
Description
본 고안은 볼 그리드 어레이 패키지에 관한 것으로서, 보다 구체적으로는 솔더 볼을 이용해서 실장되는 볼 그리드 어레이 패키지에 관한 것이다.The present invention relates to a ball grid array package, and more particularly, to a ball grid array package mounted using solder balls.
일반적인 플라스틱 반도체 패키지의 제조방법은 소잉공정, 다이 어태치 공정, 와이어 본딩 공정 및 몰딩 공정을 포함하고 있다. 여기서 몰딩 공정은 와이어 본딩된 칩과 리드 프레임의 인너리드를 포함하는 일정 면적을 에폭시 몰딩 컴파운드 등과 같은 봉지제로 밀봉함으로써 칩을 외부 환경으로부터 보호하기 위한 것으로, 통상 트랜스퍼 몰딩법으로 진행된다.A general method for manufacturing a plastic semiconductor package includes a sawing process, a die attach process, a wire bonding process, and a molding process. Here, the molding process is to protect the chip from the external environment by sealing a predetermined area including an inner lead of the wire bonded chip and the lead frame with an encapsulant such as an epoxy molding compound, and is generally performed by a transfer molding method.
이러한 패키지 중 경박화를 위해 제시된 볼 그리드 어레이 패키지는 도 1에 도시된 바와 같이, 기판(2)상에 반도체 칩(1)이 부착되어 있고, 반도체 칩(1)의 패드와 기판(2)의 리드가 금속 와이어(3)로 연결되어서, 전체가 봉지제(4)로 몰딩된 구조로 이루어져 있다. 한편, 기판(2)의 밑면에는 다수개의 랜드가 형성되어서, 각 랜드에 인쇄회로기판에 실장하기 위한 솔더 볼(5)이 부착되어 있다.Among these packages, the ball grid array package, which is presented for light and thinning, has a semiconductor chip 1 attached to the substrate 2 as shown in FIG. 1, and the pad of the semiconductor chip 1 and The lead is connected by the metal wire 3, and the whole is made into the structure molded by the sealing agent 4. As shown in FIG. On the other hand, a plurality of lands are formed on the bottom surface of the substrate 2, and solder balls 5 for mounting on the printed circuit board are attached to each land.
그런데, 종래의 볼 그리드 어레이 패키지는 기판(2)을 사용한다. 그러나, 다이 어태치 또는 몰딩 후에, 기판(2)이 휘어지는 현상이 발생되고, 또한 기판(2)과 봉지제(4)간에 박리 현상이 발생되는 문제점이 있었다.However, the conventional ball grid array package uses the substrate 2. However, after die attach or molding, there was a problem that the phenomenon in which the substrate 2 was bent and a peeling phenomenon occurred between the substrate 2 and the encapsulant 4.
따라서, 본 고안은 종래의 볼 그리드 어레이 패키지가 안고 있는 문제점을 해소하기 위해 안출된 것으로서, 기판 대신에 리드 프레임을 사용하여, 휘어지는 현상과 박리 현상을 방지할 수 있는 볼 그리드 어레이 패키지를 제공하는데 목적이 있다.Accordingly, the present invention has been made to solve the problems of the conventional ball grid array package, by using a lead frame in place of the substrate, to provide a ball grid array package that can prevent the bending and peeling phenomenon There is this.
도 1은 종래의 패키지를 나타낸 단면도1 is a cross-sectional view showing a conventional package
도 2는 본 고안의 실시예 1에 따른 패키지를 나타낸 단면도2 is a cross-sectional view showing a package according to Embodiment 1 of the present invention
도 3은 본 고안의 실시예 2에 따른 패키지를 나타낸 단면도3 is a cross-sectional view showing a package according to Embodiment 2 of the present invention
- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-
10 - 반도체 칩 20 - 리드 프레임10-semiconductor chip 20-lead frame
21 - 인너 리드 22 - 아우터 리드21-Inner Leads 22-Outer Leads
23,24 - 굴곡부 30 - 봉지제23,24-Bend 30-Encapsulant
40 - 접착제 50 - 금속 와이어40-adhesive 50-metal wire
60 - 솔더 볼60-solder balls
상기와 같은 목적을 달성하기 위한 본 고안에 따른 패키지는 다음과 같은 구성으로 이루어진다.Package according to the present invention for achieving the above object consists of the following configuration.
밑면에 패드가 형성된 반도체 칩의 상부면에 리드 프레임의 인너 리드가 부착되고, 패드가 금속 와이어로 리드 프레임에 연결된다. 봉지제에 의해 리드 프레임을 중심으로 상하부가 국부적으로 몰딩되고, 리드 프레임의 아우터 리드 밑면이 봉지제에서 노출된다. 노출된 아우터 리드 밑면에 솔더 볼이 부착된다.An inner lead of a lead frame is attached to an upper surface of a semiconductor chip having a pad formed on a bottom surface thereof, and the pad is connected to the lead frame with a metal wire. The upper and lower parts are locally molded around the lead frame by the encapsulant, and the bottom of the outer lead of the lead frame is exposed in the encapsulant. Solder balls are attached to the bottom of the exposed outer lead.
상기된 본 고안의 구성에 의하면, 기판 대신에 리드 프레임을 사용하고, 솔더 볼을 노출된 리드 프레임의 아우터 리드 밑면에 부착하므로써, 기판 사용으로 인한 휘어짐과 봉지제와의 박리 현상이 방지된다.According to the configuration of the present invention described above, by using a lead frame instead of a substrate, and by attaching a solder ball to the bottom surface of the outer lead of the exposed lead frame, the bending caused by the use of the substrate and peeling of the sealing agent is prevented.
이하, 본 고안의 바람직한 실시예를 첨부도면에 의거하여 설명한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
<실시예 1><Example 1>
도 2는 본 고안의 실시예 1에 따른 패키지를 나타낸 단면도이다.2 is a cross-sectional view showing a package according to Embodiment 1 of the present invention.
도시된 바와 같이, 반도체 칩(10)의 패드는 상부가 아니라 하부에 형성된다. 리드 프레임(20)의 인너 리드(21)가 반도체 칩(10)의 상부면에 접착제(40)로 부착되고, 금속 와이어(50)에 의해 패드와 리드 프레임(20)이 연결된다. 특히, 리드 프레임(20)의 중간부는 수평선을 중심으로 소정의 예각으로 절곡된 굴곡부(23)를 갖는다.As shown, the pads of the semiconductor chip 10 are formed at the bottom, not at the top. The inner lead 21 of the lead frame 20 is attached to the upper surface of the semiconductor chip 10 with an adhesive 40, and the pad and the lead frame 20 are connected by the metal wire 50. In particular, the middle portion of the lead frame 20 has a bent portion 23 bent at a predetermined acute angle about the horizontal line.
이러한 구조 전체가 봉지제(30)로 몰딩되는데, 리드 프레임(20)의 아우터 리드(22)가 봉지제(30)에서 노출되도록 몰딩된다. 즉, 일종의 저면 리드 노출형 패키지이다. 노출된 아우터 리드(22)의 밑면에 솔더 볼(60)이 부착된다. 특히, 아우터 리드(22)에는 도전체인 니켈/팔라듐(Ni/Pd) 합금 또는 금(Au)으로 도금 처리되고, 이 도금된 부분에 솔더 볼(60)이 부착된다. 또한, 부착력 강화를 위해, 아우터 리드(22)의 밑면에는 그루브가 형성되는 것도 바람직하다.The entire structure is molded with the encapsulant 30, and the outer lead 22 of the lead frame 20 is molded so as to be exposed from the encapsulant 30. That is, it is a kind of bottom lid exposed package. The solder ball 60 is attached to the bottom surface of the exposed outer lead 22. In particular, the outer lead 22 is plated with a nickel / palladium (Ni / Pd) alloy or gold (Au) as a conductor, and a solder ball 60 is attached to the plated portion. In addition, in order to strengthen the adhesion, it is also preferable that grooves are formed on the bottom surface of the outer lead 22.
<실시예 2><Example 2>
도 3은 본 고안의 실시예 2에 따른 패키지를 나타낸 것으로서, 다른 부분은 상기 실시예 1과 동일하고, 다만 리드 프레임과 봉지제의 구조만 약간 상이하다.Figure 3 shows a package according to Example 2 of the present invention, other parts are the same as in Example 1, except that only the structure of the lead frame and the encapsulant is slightly different.
즉, 리드 프레임(20)의 중간부에 2개의 굴곡부(23,24)가 형성되어서, 리드 프레임(20)의 아우터 리드(22)가 좀 더 하부에 위치되도록 한다. 따라서, 봉지제(70)로 몰딩하면, 실시예 1에서는 아우터 리드(22)가 봉지제(30)의 밑면보다 높은 위치에 있었으나, 본 실시예 2에서는 아우터 리드(22)와 봉지제(70)의 밑면이 동일 평면상에 위치하게 된다.That is, two bent portions 23 and 24 are formed in the middle portion of the lead frame 20 so that the outer lead 22 of the lead frame 20 is located at a lower portion. Therefore, when molded with the encapsulant 70, in the first embodiment, the outer lead 22 was higher than the bottom surface of the encapsulant 30, but in the second embodiment, the outer lead 22 and the encapsulant 70 The base of is on the same plane.
따라서, 패키지 실장 후, 패키지 저면이 인쇄회로기판과 이격되게 되므로써, 작동시에 발생되는 열이 보다 용이하게 발산될 수가 있다.Therefore, after package mounting, the bottom of the package is spaced apart from the printed circuit board, so that heat generated during operation can be more easily dissipated.
이상에서 설명한 바와 같이 본 고안에 의하면, 기판 대신에 리드 프레임(20)을 사용하고, 봉지제(30)로 몰딩시 아우터 리드(22)가 노출되도록 하며, 노출된 앙터 리드(22)에 솔더 볼(60)을 부착시키게 되므로써, 기판 사용으로 인한 휘어짐과 박리 현상을 방지할 수가 있게 된다.As described above, according to the present invention, the lead frame 20 is used instead of the substrate, and the outer lead 22 is exposed when molding with the encapsulant 30, and the solder ball is exposed to the exposed lead lead 22. By attaching the 60, it becomes possible to prevent the warpage and peeling phenomenon due to the use of the substrate.
또한, 리드 프레임(20)은 금속이므로, 패키지 내부에서 발생되는 열이 외부로 방출하는 작용이 보다 용이해진다.In addition, since the lead frame 20 is a metal, the action of dissipating heat generated inside the package to the outside becomes easier.
이상에서는 본 고안에 의한 패키지를 실시하기 위한 바람직한 실시예에 대하여 도시하고 또한 설명하였으나, 본 고안은 상기한 실시예에 한정되지 않고, 이하 청구범위에서 청구하는 본 고안의 요지를 벗어남이 없이 당해 고안이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변경 실시가 가능할 것이다.In the above has been shown and described with respect to a preferred embodiment for carrying out the package according to the present invention, the present invention is not limited to the above embodiment, the invention without departing from the spirit of the invention claimed in the claims below Anyone with ordinary knowledge in this field will be able to implement various changes.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019980011757U KR200316720Y1 (en) | 1998-06-30 | 1998-06-30 | Ball grid array package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019980011757U KR200316720Y1 (en) | 1998-06-30 | 1998-06-30 | Ball grid array package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000001950U KR20000001950U (en) | 2000-01-25 |
| KR200316720Y1 true KR200316720Y1 (en) | 2003-08-19 |
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ID=49408819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019980011757U KR200316720Y1 (en) | 1998-06-30 | 1998-06-30 | Ball grid array package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR200316720Y1 (en) |
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1998
- 1998-06-30 KR KR2019980011757U patent/KR200316720Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR20000001950U (en) | 2000-01-25 |
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