KR20030087294A - Test patterns of a semiconductor device - Google Patents

Test patterns of a semiconductor device Download PDF

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Publication number
KR20030087294A
KR20030087294A KR1020020025297A KR20020025297A KR20030087294A KR 20030087294 A KR20030087294 A KR 20030087294A KR 1020020025297 A KR1020020025297 A KR 1020020025297A KR 20020025297 A KR20020025297 A KR 20020025297A KR 20030087294 A KR20030087294 A KR 20030087294A
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South Korea
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test pattern
region
semiconductor device
active region
pattern
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KR1020020025297A
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Korean (ko)
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박현호
이철
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주식회사 하이닉스반도체
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Priority to KR1020020025297A priority Critical patent/KR20030087294A/en
Publication of KR20030087294A publication Critical patent/KR20030087294A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A test pattern of a semiconductor device is provided to be capable of reducing the resistance difference of active region between a test pattern region and a chip region for obtaining reliable measurement value by forming a test pattern region having a similar heat transmitting structure with the chip region using a dummy pattern. CONSTITUTION: A test pattern of a semiconductor device is used for measuring the resistance of an active region(43) of a semiconductor substrate by connecting a metal pad(41) at both edge portion of the active region. At this time, a dummy pattern having the same heat transmitting structure as a chip region, is formed at the active region. Preferably, the dummy pattern is made of a conductive line and an insulating layer. Preferably, the dummy pattern is grounded to a metal line located near the metal pad.

Description

반도체소자의 테스트 패턴{Test patterns of a semiconductor device}Test patterns of semiconductor devices

본 발명은 반도체소자의 테스트 패턴에 관한 것으로, 보다 상세하게 활성영역의 저항을 측정하는 테스트패턴 영역에 더미패턴을 형성하여 테스트패턴을 실제 칩과 유사하게 형성함으로써 소자의 특성을 보다 신뢰성 있게 테스트할 수 있는 반도체소자의 테스트 패턴에 관한 것이다.The present invention relates to a test pattern of a semiconductor device, and in more detail, a dummy pattern is formed in a test pattern region measuring resistance of an active region to form a test pattern similar to an actual chip, so that the characteristics of the device can be tested more reliably. The test pattern of the semiconductor device can be.

DRAM에서 테스트 패턴을 통해 소자의 전기적 특성을 측정하여 소자의 시뮬레이션에 큰 도움을 줄 수 있다.In DRAM, test patterns can be used to measure the electrical properties of the device, which can be a great help in device simulation.

상기 테스트 패턴을 통해 측정할 수 있는 항목 중 활성영역의 저항은 급속열처리(rapid thermal processing, RTP)에 민감하게 영향을 받게 된다.Among the items that can be measured through the test pattern, the resistance of the active region is sensitively affected by rapid thermal processing (RTP).

실제 칩영역은 활성영역 상에 층간절연막이 형성되고, 게이트라인, 비트라인 및 메탈 콘택 등 열전도도가 좋은 층들이 적층되어 형성되지만, 활성영역의 저항을 측정하는 테스트 패턴은 활성영역 형성된 후 다른 층들은 형성되지 않고, 산화막으로 형성되는 층간절연막 및 저항을 측정하기 위한 메탈 패드만이 형성된다.In the actual chip area, an interlayer insulating film is formed on the active area, and layers having good thermal conductivity such as gate lines, bit lines, and metal contacts are stacked. They are not formed, but only an interlayer insulating film formed of an oxide film and a metal pad for measuring resistance are formed.

이하, 첨부된 도면을 참고로 하여 종래기술에 따른 반도체소자의 테스트 패턴에 대하여 설명한다.Hereinafter, a test pattern of a semiconductor device according to the related art will be described with reference to the accompanying drawings.

도 1 및 도 2 는 종래기술에 따른 테스트 패턴을 구비하는 반도체소자를 도시한 도면으로서, 도 1은 메인 칩영역(13, 17)과 테스트 패턴 영역(11)이 인접해서 형성된 경우를 도시하고, 도 2 는 메인 칩영역(27)과 테스트패턴영역(25)이 패드영역(21)에 의해 분리되어 형성된 경우를 도시한다.1 and 2 illustrate a semiconductor device having a test pattern according to the related art, and FIG. 1 illustrates a case in which main chip regions 13 and 17 and test pattern regions 11 are formed adjacent to each other. 2 illustrates a case in which the main chip region 27 and the test pattern region 25 are formed by being separated by the pad region 21.

도 3 은 종래기술에 따른 반도체소자의 테스트 패턴을 도시한 평면도로서, 상기 테스트패턴영역(25)에서 활성영역의 저항을 측정하기 위한 테스트 패턴을 도시한다.3 is a plan view illustrating a test pattern of a semiconductor device according to the related art, and illustrates a test pattern for measuring resistance of an active region in the test pattern region 25.

상기 테스트패턴은 활성영역(33)과 메탈패드(31)로 구성되어 있으며, 상기 메탈패드(33)를 통하여 활성영역(33)의 저항을 측정할 수 있다.The test pattern is composed of an active region 33 and a metal pad 31, and the resistance of the active region 33 can be measured through the metal pad 33.

상기한 바와 같이 종래기술에 따른 반도체소자의 테스트 패턴은, 테스트패턴 영역에 활성영역과 메탈패드로만 이루어져 있고, 실제 칩영역에는 게이트라인, 비트라인 등이 구비되어 있다. 이로 인하여 후속 급속열처리에 의해 칩영역의 각종 배선 및 절연막 등이 영향을 받게 된다. 도 1 에 도시된 바와 같이 테스트패턴영역과 칩영역이 인접하여 있는 경우, 활성영역의 저항을 측정하는 경우 테스트패턴영역과 실제 칩영역이 받는 영향이 비슷하지만, 도 2에 도시된 바와 같이 테스트패턴영역과 실제 칩영역이 떨어져 형성되어 있는 경우에는 테스트패턴영역과 실제 칩영역이 받는 영향이 서로 다르기 때문에 테스트패턴영역에서 측정되는 활성영역의 저항치와 실제 칩영역에서 활성영역의 저항치가 서로 다르게 측정되어 실제 칩영역의 저항 특성을 정확하게 측정할 수 없다는 문제점이 있다.As described above, the test pattern of the semiconductor device according to the related art includes only the active region and the metal pad in the test pattern region, and the gate line and the bit line are provided in the actual chip region. As a result, various wirings, insulating films, and the like of the chip region are affected by subsequent rapid heat treatment. As shown in FIG. 1, when the test pattern region and the chip region are adjacent to each other, the effect of the test pattern region and the actual chip region is similar when measuring the resistance of the active region, but as shown in FIG. If the area is separated from the actual chip area, the test pattern area and the actual chip area have different influences. Therefore, the resistance value of the active area measured in the test pattern area is different from the resistance value of the active area in the actual chip area. There is a problem in that the resistance characteristics of the actual chip area cannot be accurately measured.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 활성영역의 저항을 측정하기 위한 테스트 패턴영역에 활성영역의 저항을 측정하기 위한 메탈패드와 활성영역 및 더미패턴을 형성하여 실제 칩영역과 비슷한 열전달 구조를 갖는 테스트패턴영역을 형성함으로써 후속 급속열처리에 의해 테스트패턴영역과 칩영역에서의 활성영역 저항치 차이를 감소시켜 신뢰성 있는 측정치를 얻을 수 있는 반도체소자의 테스트 패턴을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art, by forming a metal pad, an active region and a dummy pattern for measuring the resistance of the active region in the test pattern region for measuring the resistance of the active region similar to the actual chip region It is an object of the present invention to provide a test pattern of a semiconductor device in which a test pattern region having a heat transfer structure is formed to reduce the difference in resistance between the active region in the test pattern region and the chip region by subsequent rapid heat treatment to obtain reliable measurement values.

도 1 및 도 2 는 종래기술에 따른 테스트 패턴을 구비하는 반도체소자를 도시한 도면.1 and 2 illustrate a semiconductor device having a test pattern according to the prior art.

도 3 은 종래기술에 따른 반도체소자의 테스트 패턴을 도시한 평면도.3 is a plan view showing a test pattern of a semiconductor device according to the prior art.

도 4 는 본 발명에 따른 반도체소자의 테스트 패턴을 도시한 평면도.4 is a plan view showing a test pattern of a semiconductor device according to the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

11, 25 : 테스트패턴 영역 13, 17, 27 : 메인 칩영역(main chip region)11, 25: test pattern region 13, 17, 27: main chip region

15, 21 : 패드영역 31, 41 : 메탈 패드15, 21: pad area 31, 41: metal pad

33, 43 : 활성영역 45 : 더미게이트라인33, 43: active area 45: dummy gate line

47 : 더미비트라인 49 : 메탈 콘택47: dummy bit line 49: metal contact

51 : 메탈라인51: metal line

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 테스트 패턴은,In order to achieve the above object, the test pattern of the semiconductor device according to the present invention,

반도체기판의 활성영역 양쪽 가장자리에 메탈패드를 접속시켜 상기 활성영역의 저항을 측정하는 반도체소자의 테스트 패턴에 있어서,In the test pattern of the semiconductor device for measuring the resistance of the active region by connecting a metal pad to both edges of the active region of the semiconductor substrate,

상기 활성영역 상에 칩영역과 같은 열전달구조의 더미패턴을 구비하는 것과,Providing a dummy pattern of a heat transfer structure such as a chip region on the active region;

상기 더미패턴은 도전배선 및 절연막인 것과,The dummy pattern is a conductive wiring and an insulating film,

상기 더미패턴은 상기 메탈패드에 인접하는 메탈라인에 접지되어 구비되는 것을 특징으로 한다.The dummy pattern may be grounded to a metal line adjacent to the metal pad.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 4 는 본 발명에 따른 반도체소자의 테스트 패턴을 도시한 평면도로서, 실제 칩영역과 비슷한 구조로 형성된 것을 도시한다.4 is a plan view showing a test pattern of a semiconductor device according to the present invention, which is formed in a structure similar to an actual chip region.

먼저, 반도체기판의 테스트패턴영역에 활성영역(43)을 형성한다.First, an active region 43 is formed in a test pattern region of a semiconductor substrate.

다음, 상기 활성영역(43) 상에 더미게이트라인(45) 및 더미비트라인(47)을 형성한다.Next, a dummy gate line 45 and a dummy bit line 47 are formed on the active region 43.

이때, 상기 더미게이트라인(45) 및 더미비트라인(47)은 후속 급속열처리에 의한 열효과(thermal effect)만 일으켜 활성영역의 저항을 정확하게 측정하기 위해 형성된 것으로서 그 구조 및 형태는 결정되어 있지는 않다.At this time, the dummy gate line 45 and the dummy bit line 47 are formed to accurately measure the resistance of the active region due to only a thermal effect by subsequent rapid heat treatment, and the structure and shape thereof are not determined. .

여기서, 상기 더미게이트라인(45) 및 더미비트라인(47) 이외에 도시되어 있지는 않지만, 캐패시터가 형성될 수도 있다.Here, although not shown other than the dummy gate line 45 and the dummy bit line 47, a capacitor may be formed.

그리고, 소자 간의 층간절연을 위하여 절연막을 형성하여 구조를 변경함으로써 급속열처리에 의해 실제 칩영역이 받는 영향과 최대한 유사하게 받도록 한다.In addition, an insulating film is formed to change the structure for interlayer insulation between the devices, so that the thermal chip may be subjected to the heat treatment as closely as possible.

그 후, 상기 활성영역(43)의 양쪽 가장자리에 접속되어 상기 활성영역(43)의 저항을 측정하기 위한 메탈패드(41)를 형성하고, 상기 메탈패드(41)에 인접하여 상기 더미게이트라인(45) 및 더미비트라인(47)의 접지를 위한 메탈라인(51)을 형성한다.Thereafter, the metal pad 41 is connected to both edges of the active region 43 to form a metal pad 41 for measuring the resistance of the active region 43, and is adjacent to the metal pad 41. 45 and a metal line 51 for grounding the dummy bit line 47.

이때, 상기 더미 게이트라인(45) 및 더미 비트라인(47)은 상기 메탈라인(51)에 접지되어 메탈패드(41)로부터 측정되는 활성영역(43)의 저항치에 영향을 미치지 않는다.In this case, the dummy gate line 45 and the dummy bit line 47 are grounded to the metal line 51 so as not to affect the resistance value of the active region 43 measured from the metal pad 41.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 테스트 패턴은, 활성영역의 저항을 측정하기 위한 테스트 패턴영역에 실제 칩영역과 유사하게 게이트라인, 비트라인 등의 더미패턴을 형성하여 실제 칩영역과 테스트패턴영역의 열전달 구조를 유사하게 형성함으로써 급속열처리에 의해 저항치가 다르게 측정되는 것을 방지하여 반도체소자의 전기적 특성 및 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, the test pattern of the semiconductor device according to the present invention forms a dummy pattern such as a gate line and a bit line in the test pattern region for measuring the resistance of the active region, similarly to the actual chip region. By similarly forming the heat transfer structure of the test pattern region, it is possible to prevent the resistance value from being measured differently by rapid heat treatment, thereby improving electrical characteristics and reliability of the semiconductor device.

Claims (3)

반도체기판의 활성영역 양쪽 가장자리에 메탈패드를 접속시켜 상기 활성영역의 저항을 측정하는 반도체소자의 테스트 패턴에 있어서,In the test pattern of the semiconductor device for measuring the resistance of the active region by connecting a metal pad to both edges of the active region of the semiconductor substrate, 상기 활성영역 상에 칩영역과 같은 열전달구조의 더미패턴을 구비하는 반도체소자의 테스트 패턴.A test pattern of a semiconductor device having a dummy pattern of a heat transfer structure such as a chip region on the active region. 제 1 항에 있어서,The method of claim 1, 상기 더미패턴은 도전배선 및 절연막인 것을 특징으로 하는 반도체소자의 테스트 패턴.The dummy pattern is a test pattern of a semiconductor device, characterized in that the conductive wiring and the insulating film. 제 1 항에 있어서,The method of claim 1, 상기 더미패턴은 상기 메탈패드에 인접하는 메탈라인에 접지되어 구비되는 것을 특징으로 하는 반도체소자의 테스트 패턴.The dummy pattern is a test pattern of a semiconductor device, characterized in that the ground provided on the metal line adjacent to the metal pad.
KR1020020025297A 2002-05-08 2002-05-08 Test patterns of a semiconductor device KR20030087294A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101023072B1 (en) * 2008-09-05 2011-03-24 주식회사 동부하이텍 resist array of mismatch structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101023072B1 (en) * 2008-09-05 2011-03-24 주식회사 동부하이텍 resist array of mismatch structure

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