KR20040002273A - A test pattern of a semiconductor device and A method for measuring a overlay margin - Google Patents

Abstract

PURPOSE: A test pattern of a semiconductor device is provided to improve productivity of the semiconductor device by measuring total current while inserting the number of transistors necessary for a test pattern. CONSTITUTION: A common source/drain is formed in a side of a plurality of gates of the transistor. The first metal line(51) and the second metal line(53) are connected to a via contact plug(55) between the drain and the gate. A plurality of the first metal lines have a different size of an overlay margin at the side end of the first metal line to which the via contact plug is connected.

Description

A test pattern of a semiconductor device and A method for measuring a overlay margin}

The present invention relates to a method for measuring a test pattern and overlap margin of a semiconductor device, and in particular, a line during a contact process for interlayer connection of a line used as a circuit line, such as a gate, a bit line, a metal line, and the like, in a design rule. A test pattern formation technique for determining any overlap values between contacts.

In general, in the process of forming a semiconductor device, in order to implement an arbitrary semiconductor circuit on a wafer, the circuit is laid out in an actual shape to make a mask and the process is performed using the mask.

At this time, in order to layout, a design rule, which is a kind of layout rule for the minimum line width, interlayer spacing, or overlapping margin for each layer, is necessary, because current process capability must be considered.

For example, when forming a metal line to be used as an electrical line between circuits, it is necessary to design the layout beyond the line width that can be patterned by the current process.

In order to present an accurate value in the design rule, a method for verifying the current process capability and the electrical problem after the process is required.

The test pattern is evaluated to evaluate the design rule, and then the evaluation is performed to provide an accurate value.

1 to 4 are layout views, plan views, and cross-sectional views showing a test pattern and a method of measuring overlap margins of a semiconductor device according to the related art.

FIG. 1 illustrates a layout in the case of forming a contact for electrically connecting metal lines of different layers, and FIG. 2 illustrates a metal line on a mask and a metal line actually formed at part ⓐ of FIG. It shows the form.

1 and 2, when the contact 13 is formed on the metal line 11, it is common to form a large line width of the metal line 11 at the position where the contact is formed, which occurs in a photolithography process. This is because of the misalignment that occurs.

That is, even if misalignment occurs in the photo process as shown in FIG. 1, a margin is required to be electrically connected, which is classified into two side overlay sizes ⓧ and end side overlay size ⓨ. Can be.

In general, the margin between the line and the contact requires a larger value at the end side than both sides because of the effect of reducing the length of the line as shown in FIG.

Since the reduction of the line length is also affected by the line width, it is difficult to obtain the overlap margin value of the end side.

FIG. 2 illustrates a metal line 21 formed on a mask and a portion of the contact 23 overlapping the metal line 25 formed on the actual semiconductor substrate.

3 and 4 illustrate a general evaluation method for obtaining an end side overlap margin and a plan view and a cross-sectional view when a fail is induced.

3 and 4, the first metal line 33 is formed on the semiconductor substrate 31 on which the lower insulating layer including the device isolation layer, the gate electrode, the bit line, and the capacitor are formed.

In this case, the first metal line 33 is connected to an active region, a gate electrode, a bit line, and a capacitor of the semiconductor substrate 31.

Next, an interlayer insulating film 35 is formed to planarize the entire upper surface, and a via contact plug 37 is connected to the first metal line 33 and the second metal lines 39a and 39b.

In this case, the via contact plug 37 may etch the interlayer insulating layer 35 by a photolithography process using a via contact mask (not shown) to form a via contact contact hole exposing the first metal line 33. It is formed by filling it with a contact conductive layer for metal line.

Here, the second metal lines 39a and 39b are divided into two patterns and contacted with the first metal lines 33 through the via contact plugs 37.

In FIG. 3, ⓨ shows the end side overlap size.

Next, the via contact plug 37 and the first metal line 33 are electrically connected to each other at the predetermined end side overlap margin ⓨ by applying a voltage and measuring a current between the two second metal lines 39a and 39b. Determine more current flow.

However, when the overlap margin ⓨ is smaller than the misalignment of the photo process and the shortening of the line length, a via contact plug for forming the second metal line 39a on the first metal line 33 as shown in FIG. 4. 37 shows that the first metal line 33 is not electrically connected to each other by ⓐ.

By evaluating the end side overlap margin by the method described above, very many kinds of test patterns are needed to obtain an accurate value. That is, a test pattern according to the size of the side overlap margin is required, and the shortening of the length varies according to the line width, and thus the change according to each line width should be considered.

In order to electrically verify each test pattern, two pads are required that can be measured in electrical contact from the outside.

As described above, the test pattern and the overlapping margin measuring method of the semiconductor device according to the prior art,

When two pads are required for the electrical verification of each test pattern, the number of overlapping margins to be evaluated is 10. According to the prior art, 20 specific pads are required. . For this reason, the test pattern determined by the number of pads requires a large area, and thus the efficiency is inferior because the test pattern needs to be evaluated by multiple measurements.

In order to solve the problems of the prior art described above, by inserting as many transistors as necessary in the test pattern in order to reduce the area of the test pattern required to determine the design rule for the end side overlap margin and to efficiently measure It is an object of the present invention to provide a test pattern and overlapping margin measuring method of a semiconductor device that can improve productivity of the semiconductor device by using an encoding method of measuring a total current to obtain a design rule by only one measurement.

1 and 2 are layout diagrams showing problems in test patterns and misalignment of semiconductor devices in the prior art;

3 and 4 are layout views illustrating problems in test patterns and misalignment of semiconductor devices in the prior art;

5 is a circuit diagram illustrating the technical idea of the present invention.

6 is a graph showing the end side overlap margin size for the total current;

<Description of Symbols for Main Parts of Drawings>

11: first metal line

13,37,55: Contact, Via Contact, Via Contact Plug

21: first metal line shape designed on the mask

23: first metal line formed on the actual substrate

31: semiconductor substrate

3351: first metal line

35: interlayer insulating film

39a, 39b53: second metal line

Ⓑ: misaligned size

Ⓧ: Both sides overlap margin size

Ⓨ: end side nesting margin size

In order to achieve the above object, the test pattern of the semiconductor device according to the present invention,

Transistors each having a common source and drain formed on one side of a plurality of gates,

A via contact plug is connected between the drain and the gate to provide a first metal line and a second metal line.

A plurality of first metal lines having different end overlapping margin sizes of the first metal lines to which the via contact plugs are connected may be provided.

In addition, the overlap margin measuring method of the semiconductor device according to the present invention in order to achieve the above object,

A plurality of first metal lines and second metals having a common source and a drain are formed on one side of the gate, respectively, and the end side overlap margins of the first metal line having a via contact plug connected between the drain and the gate are different. Form a test pattern with lines,

The end side overlap margin is calculated by flowing a current from the drain to the source and measuring the sum of the currents flowing into the source.

5 is a circuit diagram showing the technical principle of the present invention,

According to the size of the overlap margin ⓨ between the first metal line 51 and the via contact plug 55, a plurality of second metal lines 53 are arranged, and transistors are connected to opposite sides of the second metal line 53, respectively. After that, the sum of the current flowing through the transistor can be measured.

The plurality of second metal lines 53 are connected to a common drain of the transistor, and are connected to a common source through gates of the transistors.

The gates and sources of all transistors are also connected, requiring three pads for external measurements.

If the connection between the first metal line 51 and the via contact plug 55 is cut below a certain size according to the size of the overlap margin ⓨ, current flows in the transistor only for the connected metal line, which is the magnitude of the total current. I (total) can be estimated in proportion to the number of connected contact plugs 55, thereby obtaining the size of the required overlap margin.

FIG. 6 is a graph showing the relationship between the measured total current amount and the size of the overlap margin ⓨ, which enables accurate extraction using the transistor characteristics of FIG. 5.

As described above, the test pattern and the overlap margin measuring method of the semiconductor device according to the present invention provide the following effects.

First, when the number of overlapping margins to be evaluated is 10, 20 specific pads are needed according to the prior art, and can be known through 10 measurements, whereas only 3 pads are required when using the present invention. The results can be seen with just one measurement. That is, the use of the present invention allows the reduction of layout area and efficient evaluation.

Claims (2)

Transistors each having a common source and drain formed on one side of a plurality of gates, A via contact plug is connected between the drain and the gate to provide a first metal line and a second metal line. And a plurality of first metal lines having different end overlapping margin sizes of the first metal lines to which the via contact plugs are connected. A plurality of first and second metals having a common source and a drain are formed on one side of the plurality of gates, respectively, and the end side overlap margins of the first metal line having a via contact plug connected between the drain and the gate are different. Form a test pattern with lines, The method of measuring overlapping margin of a semiconductor device, characterized in that the end side overlapping margin is calculated by measuring the sum of the current flowing from the drain to the source.