KR100370956B1 - Test pattern for measuring leakage current - Google Patents

Test pattern for measuring leakage current Download PDF

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Publication number
KR100370956B1
KR100370956B1 KR10-2000-0042208A KR20000042208A KR100370956B1 KR 100370956 B1 KR100370956 B1 KR 100370956B1 KR 20000042208 A KR20000042208 A KR 20000042208A KR 100370956 B1 KR100370956 B1 KR 100370956B1
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leakage current
main chip
region
bit line
measuring
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KR10-2000-0042208A
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Korean (ko)
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KR20020008346A (en
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옥승한
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only

Abstract

본 발명은 누설전류 측정용 테스트 패턴에 관한 것으로, 종래에는 메인 칩 내의 단락에 따른 총 누설전류가 충분히 측정할 수 있을 정도의 수준이 되도록 하기 위해서 많은 어레이 패턴이 요구되어 차지하는 면적이 증가하는 문제점이 있고, 또한 평균값을 산출함에 따라 메인 칩의 국부적 단락 누설전류에 대해서는 측정이 불가능한 문제점이 있었다. 따라서, 본 발명은 메인 칩 내의 국부적 단락에 따라 제1영역에서 제2영역으로 전류의 누설패스가 예상될 때, 메인 칩의 주변에 상기 제1영역 및 제2영역과 동일한 제3영역 및 제4영역을 형성하고, 상기 제3영역에 전원전압을 접속시키는 제1패턴과; 상기 제3영역으로부터 제4영역으로 누설되는 전류를 바이폴라 트랜지스터에 인가하여, 그 바이폴라 트랜지스터에서 증폭된 누설전류 값을 측정장비로 측정하여 실제 누설전류 값을 구하도록 함으로써, 많은 어레이 패턴이 요구되지 않아 차지하는 면적을 줄일 수 있으며, 또한 메인 칩의 국부적 단락 누설전류에 대해서 정확한 측정이 가능한 효과가 있다.The present invention relates to a test pattern for measuring leakage current, and in the related art, in order to ensure that the total leakage current due to a short circuit in the main chip can be sufficiently measured, the problem of increasing the area occupied by many array patterns is required. In addition, as the average value is calculated, there is a problem in that local short circuit leakage current of the main chip cannot be measured. Therefore, in the present invention, when the leakage path of the current is expected from the first region to the second region according to a local short circuit in the main chip, the third region and the fourth region that are the same as the first region and the second region are around the main chip. A first pattern forming a region and connecting a power supply voltage to the third region; By applying the current leaking from the third region to the fourth region to the bipolar transistor, by measuring the leakage current value amplified by the bipolar transistor by measuring equipment to obtain the actual leakage current value, many array patterns are not required It can reduce the area to be occupied, and also has the effect of making accurate measurements on the local short-circuit leakage current of the main chip.

Description

누설전류 측정용 테스트 패턴{TEST PATTERN FOR MEASURING LEAKAGE CURRENT}TEST PATTERN FOR MEASURING LEAKAGE CURRENT}

본 발명은 누설전류 측정용 테스트 패턴에 관한 것으로, 특히 테스트 패턴의 면적을 최소화함과 아울러 메인 칩내의 국부적 단락에 따른 미세 누설전류를 측정할 수 있도록 한 누설전류 측정용 테스트 패턴에 관한 것이다.The present invention relates to a test pattern for measuring leakage current, and more particularly, to a test pattern for measuring leakage current to minimize the area of the test pattern and to measure a fine leakage current according to a local short circuit in the main chip.

일반적으로, 디램 셀(DRAM cell)의 사이즈가 작아지면서 회로 동작에 악영향을 초래하는 정션(junction) 누설전류, 절연(isolation) 누설전류, 단락(short) 누설전류 등의 누설전류 값도 미세화되고 있다.In general, as the size of a DRAM cell becomes smaller, leakage current values such as junction leakage current, isolation leakage current, and short leakage current, which adversely affect circuit operation, are also miniaturized. .

따라서, 하나의 셀에 대한 누설전류 값은 장비의 측정한계 이하가 되어 직접적으로 측정할 수 없게 되었다.Therefore, the leakage current value for one cell is below the measurement limit of the equipment and cannot be measured directly.

상기와 같은 미세한 누설전류를 측정하기 위해서는 다수의 셀을 하나의 어레이(array) 패턴으로 만든 다음 총 누설전류를 측정하여 셀의 갯수로 나눔으로써, 평균값을 산출하는 방식을 적용하고 있다.In order to measure the minute leakage current as described above, a method of calculating an average value is performed by making a plurality of cells into an array pattern and then measuring the total leakage current and dividing by the number of cells.

상기한 바와같은 종래의 기술은 총 누설전류가 충분히 측정할 수 있을 정도의 수준이 되도록 하기 위해서 많은 어레이 패턴이 요구되어 차지하는 면적이 증가하는 문제점이 있고, 또한 평균값을 산출함에 따라 메인 칩의 국부적 단락 누설전류에 대해서는 측정이 불가능한 문제점이 있었다.The conventional technique as described above has a problem in that the area occupied by increasing the number of array patterns is required in order to make the total leakage current sufficiently high, and also the local short circuit of the main chip as the average value is calculated. There was a problem in that leakage current could not be measured.

본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 테스트 패턴의 면적을 최소화함과 아울러 메인 칩내의 국부적 단락에 따른 미세 누설전류를 측정할 수 있는 누설전류 측정용 테스트 패턴을 제공하는데 있다.The present invention was devised to solve the conventional problems as described above, and an object of the present invention is to minimize the area of the test pattern and to measure the leakage current according to the local short circuit in the main chip. To provide a test pattern.

도1은 본 발명의 일 실시예에 따라 콘택 사이의 키-홀(key-hole)에서 기인하는 누설전류 측정용 테스트 패턴을 보인 예시도.1 is an exemplary view showing a test pattern for measuring leakage current resulting from key-holes between contacts according to an embodiment of the present invention.

***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***

1:반도체기판 2:필드산화막1: Semiconductor Substrate 2: Field Oxide

3:콘택 플러그 B/L1,B/L2:비트라인3: Contact plug B / L1, B / L2: Bit line

Q1:바이폴라 트랜지스터 Vcc:전원전압Q1: Bipolar transistor Vcc: Power supply voltage

IL-path:누설 전류패스 IL:누설전류I L -path: leakage current path I L : leakage current

상기한 바와같은 본 발명의 목적을 달성하기 위한 누설전류 측정용 테스트 패턴은 메인 칩 내의 국부적 단락에 따라 제1영역에서 제2영역으로 전류의 누설패스가 예상될 때, 메인 칩의 주변에 상기 제1영역 및 제2영역과 동일한 제3영역 및 제4영역을 형성하고, 상기 제3영역에 전원전압을 접속시키는 제1패턴과; 상기 제3영역으로부터 제4영역으로 누설되는 전류를 바이폴라 트랜지스터에 인가하여, 그 바이폴라 트랜지스터에서 증폭된 누설전류 값을 측정장비로 측정하여 실제 누설전류 값을 구하도록 하는 제2패턴을 구비하여 이루어지는 것을 특징으로 한다.The test pattern for measuring leakage current to attain the object of the present invention as described above is provided in the vicinity of the main chip when a leakage path of current is expected from the first region to the second region according to a local short circuit in the main chip. A first pattern forming a third region and a fourth region identical to the first region and the second region, and connecting a power supply voltage to the third region; And applying a current leaking from the third region to the fourth region to the bipolar transistor, and measuring a leakage current value amplified by the bipolar transistor with a measuring device to obtain an actual leakage current value. It features.

상기한 바와같은 본 발명에 의한 누설전류 측정용 테스트 패턴을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.Referring to the accompanying drawings of the leakage current measurement test pattern according to the present invention as described above in detail as follows.

도1은 본 발명의 일 실시예에 따라 콘택 사이의 키-홀(key-hole)에서 기인하는 누설전류 측정용 테스트 패턴을 보인 예시도로서, 이에 도시한 바와같이 메인 칩 내의 국부적 단락에 따라 콘택 사이의 키-홀에서 기인하는 전류의 누설패스가 예상될 때, 메인 칩의 제조과정에서 적용되는 각 공정들을 이용하여 메인 칩 주변의 반도체기판(1) 상에 메인 칩의 액티브영역과 동일한 형상으로 필드산화막(2)을 이격 패터닝하고, 메인 칩의 액티브영역 가장자리에 형성되는 콘택 플러그와 동일한 콘택 플러그(3)를 상기 필드산화막(2)의 가장자리에 각각 형성한 다음 메인 칩의 비트라인 형성시 상기 필드산화막(2)에 형성된 콘택 플러그(3)를 수평방향으로 가로지르는 비트라인(B/L1,B/L2)을 이격되도록 형성한다.FIG. 1 is an exemplary view showing a test pattern for measuring leakage current resulting from key-holes between contacts according to an embodiment of the present invention. As shown therein, a contact according to a local short circuit in a main chip is shown. When the leakage path of the current originating from the key-holes between them is expected, each process applied in the manufacturing process of the main chip has the same shape as the active region of the main chip on the semiconductor substrate 1 around the main chip. The field oxide layer 2 is spaced and patterned, and contact plugs 3, which are the same as the contact plugs formed at the edges of the active region of the main chip, are formed at the edges of the field oxide layer 2, respectively. The bit lines B / L1 and B / L2 crossing the contact plugs 3 formed in the field oxide film 2 in the horizontal direction are formed to be spaced apart from each other.

그리고, 상기 비트라인(B/L1)에 전원전압(Vcc)을 인가함과 아울러 상기 비트라인(B/L2)을 컬렉터가 전원전압(Vcc)에 접속되고, 이미터가 접지된 바이폴라 트렌지스터(Q1)의 베이스에 인가한다.In addition, the power supply voltage Vcc is applied to the bit line B / L1, and the bit line B / L2 is connected to the power supply voltage Vcc and the emitter is grounded. ) Is applied to the base.

따라서, 상기 콘택 플러그(3) 간의 누설 전류패스(IL-path)가 있다면, 상기 비트라인(B/L1)에 접속된 전원전압(Vcc)으로 인해 누설전류(IL)가 비트라인(B/L2)을 통해 바이폴라 트랜지스터(Q1)의 베이스로 흐르게 되고, 이때 그 바이폴라 트랜지스터(Q1)의 컬렉터에 흐르는 증폭된 전류(β×IL)를 측정장비로 측정하여 실제 누설 전류값을 구한다.(여기서, β= Q1의 증폭율)Thus, if a leakage current path (I L -path) between the contact plug (3), the bit line (B / L1) as a result of a power supply voltage (Vcc), the bit line leakage current (I L) connected to (B / L2) flows to the base of the bipolar transistor Q1, and at this time, the amplified current (β × I L ) flowing through the collector of the bipolar transistor Q1 is measured by a measuring device to obtain an actual leakage current value. Where β = amplification factor of Q1)

한편, 상기 본 발명의 실시예에서는 2개의 콘택 플러그에 대한 누설전류를 측정하였지만, 바이폴라 트랜지스터의 증폭율과 누설되는 전류의 양에 따라 1개의 콘택 플러그 또는 다수개의 콘택 플러그에 확장하여 적용할 수 있을 것이다.Meanwhile, in the embodiment of the present invention, the leakage currents of the two contact plugs are measured, but may be extended to one contact plug or a plurality of contact plugs according to the amplification ratio of the bipolar transistor and the amount of leakage current. will be.

상기한 바와같은 본 발명에 의한 누설전류 측정용 테스트 패턴은 많은 어레이 패턴이 요구되지 않아 차지하는 면적을 줄일 수 있으며, 또한 메인 칩의 국부적 단락 누설전류에 대해서 정확한 측정이 가능한 효과가 있다.The test pattern for measuring leakage current according to the present invention as described above can reduce the area occupied since many array patterns are not required, and also have the effect of making accurate measurement on the local short-circuit leakage current of the main chip.

Claims (4)

삭제delete 삭제delete 삭제delete 메인 칩 내의 국부적 단락에 따라 콘택 사이의 키-홀에서 기인하는 전류의 누설패스가 예상될 때, 메인 칩의 제조과정에서 적용되는 각 공정들을 통해 메인 칩 주변의 반도체기판 상에 메인 칩의 액티브영역과 동일한 형상으로 이격 패터닝된 필드산화막과; 메인 칩의 액티브영역 가장자리에 형성되는 콘택 플러그와 동일하게 상기 필드산화막의 가장자리에 각각 형성된 콘택 플러그와; 메인 칩의 비트라인 형성시 형성되며, 상기 필드산화막 상에 형성된 콘택 플러그를 수평방향으로 가로질러 전원전압에 접속된 제1비트라인과; 상기 제1비트라인과 이격되어 상기와는 다른 필드산화막 상에 형성된 콘택 플러그를 수평방향으로 가로질러 형성되는 제2비트라인과; 상기 제2비트라인에 베이스가 접속되고, 컬렉터가 전원전압에 접속되며, 이미터가 접지된 바이폴라 트랜지스터를 구비하여, 상기 바이폴라 트랜지스터의 컬렉터에 흐르는 증폭된 누설전류값을 측정장비로 측정하여 실제 누설전류 값을 구하도록 구성된 것을 특징으로 하는 누설전류 측정용 테스트 패턴.When a leakage path of the current resulting from the key-hole between the contacts is expected due to a local short circuit in the main chip, the active area of the main chip on the semiconductor substrate around the main chip through each process applied in the manufacturing process of the main chip. A field oxide film spaced and patterned in the same shape as; Contact plugs formed at the edges of the field oxide film in the same manner as contact plugs formed at the edges of the active region of the main chip; A first bit line formed when the bit line of the main chip is formed and connected to a power supply voltage across a contact plug formed on the field oxide film in a horizontal direction; A second bit line spaced apart from the first bit line so as to cross a contact plug formed on a different field oxide film in a horizontal direction; A base is connected to the second bit line, a collector is connected to a power supply voltage, and a bipolar transistor having an emitter is grounded. The amplified leakage current flowing through the collector of the bipolar transistor is measured by a measuring device to actually leak. A test pattern for measuring leakage current, characterized in that configured to obtain a current value.
KR10-2000-0042208A 2000-07-22 2000-07-22 Test pattern for measuring leakage current KR100370956B1 (en)

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