JPH0636585A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To judge an excess erasure condition in a real set transistor by the presence of current through a bit line connected to a selected test cell transistor. CONSTITUTION:When the test cell transistor (Tr) 2 is selected, since a real cell Tr 1 is non-selective, though no current flows through a bit line B1, when the Tr 1 is in the excess erasure condition, leakage current flows through the line B1 even when the Tr 2 is selected. Then, when the Tr 2 is selected by a cell selection decoder 3, whether current flows through the line B1 or not is detected by a sense amplifier (current detection means) 4, and when flows, it is judged that the Tr 1 is in the excess erasure condition. In such a manner, when hold data in the Tr 1 is erased, the Tr 2 is selected by the decoder 3, and by detecting whether current flows through the line B1 connected to the selected Tr 2 or not by the amplifier 4, whether the Tr 1 is in the excess erasure condition or not is judged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more specifically, for example, an EEPROM (Electric)
The present invention relates to a nonvolatile semiconductor memory device capable of rewriting data, which is suitable for use in fields such as ally erasable programmable read only memory). 2. Description of the Related Art In recent years, with the spread of information processing devices such as computers and word processors, for example, EEPROM and Fl used inside the information processing devices
Many non-volatile semiconductor memory devices represented by non-volatile semiconductor memories such as ashEEPROM (hereinafter, simply referred to as flash memory) have been developed.

This is a non-volatile memory that can be programmed by a general user and can be rewritten by electrically erasing predetermined data that has been written in advance. However, there is a proper voltage value for erasing such a memory, and excessive erasing leads to device deterioration. Therefore, it is necessary to perform proper erasing.

[0003]

2. Description of the Related Art Conventionally, as a semiconductor memory device which is a non-volatile memory that can be rewritten by erasing predetermined data written in advance, for example, EPROM and EEPROM are known. However, EPROM
Has an advantage that the cell size is small, but has a disadvantage that the data erasing is troublesome because the ultraviolet rays are used for erasing the data, and the EEPROM can easily erase the data because the data can be electrically erased. However, the cell size is larger than that of the EPROM, so that it is difficult to increase the capacity.

Therefore, a semiconductor memory device called NOR type or NAND type flash memory, which has the advantages of each of these memories, has been developed. FIG. 4 is a sectional view of a typical cell of a flash memory. In the figure,
CG is a control gate, FG is a floating gate, D is an N ⁺ type drain, S is an N ⁺ type source, PS
Is a P-type substrate.

FIG. 5 is a circuit diagram showing a cell matrix structure of the flash memory shown in FIG. In the figure, C is each memory cell, WL _x is a word line, BL _x is a bit line, SL _x
Indicates a select line. (However, _x represents _i , _j , _a , _m , _n in the figure.) Next, the operation will be described.

First, when writing to the memory cell C
Is a high potential on the control gate CG and drain D
Voltage V_PPIs applied to the avalanche near the drain D.
Electrons are injected into the floating gate FG by the injection.
The memory cell C is cut off. To delete,
With the drain D floated, the source S has a high electric potential.
Pressure V _PPIs applied, electrons are emitted from the floating gate FG.
Is removed, the written data cannot be erased.
To be done.

The potential levels of the control gate CG, the drain D, the source S, and the substrate PS in the above-mentioned operating state are set to the values shown in Table 1.

[0008]

[Table 1]

By the way, in such a conventional semiconductor memory device, by applying a high potential voltage V _PP to the control gate CG and the drain D, electrons are injected into the floating gate FG by avalanche injection in the vicinity of the drain D. Is used to write data, and electrons are removed from the floating gate FG to erase the written data. , When a cell transistor is over-erased, this cell transistor has the same property as a depletion transistor, and a current always flows through the bit line even if the cell is not selected, and the bit existing in this cell is present. The data is fixed no matter which cell on the line is selected. Would be output, i.e., the non-selected memory cell occurs conduction by passing a leakage current, there is a problem that reading of the written supposed cell becomes impossible.

Therefore, in order to avoid excessive erasure, as shown in FIG. 6, the erase operation is performed in the procedure as shown in FIG. Was there. FIG. 7 is a flowchart of the erasing algorithm. First, it is checked whether or not all the cell transistors are "0" (step 1), and if there is a cell transistor that is not "0", "0" is written in all the cell transistors (step 2). ).

Below, within a range not exceeding the maximum erase count N,
Additional erasing and verifying are performed little by little, and as shown in FIG. 6, the erasing process is completed when the threshold value for verifying is exceeded.

[0012]

However, in such a conventional semiconductor memory device, additional erasing is performed little by little, and the erasing process is terminated when the threshold value for verify is lowered. However, there is a problem in that additional erasing is required many times and it takes time to erase.

Therefore, in order to shorten the erasing time,
Although it is possible to increase the erase voltage to roughen the erase step, in this case, there is a risk of excessive erase depending on the threshold value at the time of verification and the level width between the low levels. In addition, it is possible that the user erases the data excessively due to a mistake in the erasing operation.

As described above, the device in the over-erased state (see FIG. 8) has a read failure as described above. To investigate whether the cause of the read failure is over-erase, the package is etched. The chip was exposed and the cover film on the chip that blocks the ultraviolet rays was peeled off, and then the ultraviolet rays were irradiated to judge whether or not the reading was possible.

That is, when read failure occurs due to excessive erasure, as shown in FIG. 9, when ultraviolet rays are irradiated from the outside, electrons of the substrate and the control gate are emitted by the energy of the ultraviolet rays and injected into the floating gate. At the same time, it is recombined with the holes in the floating gate. This process continues until there is no electric field in the cell and eventually the cell is in a normal state (see Figure 1
Then, when writing / reading is performed, the data written in the cell is normally read.

Therefore, if the data cannot be read due to excessive erasing, it can be reused by the above processing. Therefore, it is possible that the device that cannot read data is due to excessive erasing, process problems, or other factors. It is possible to determine whether or not it is possible, but it is necessary to perform processing such as physically deforming the package or the like for the investigation, and it takes time for the investigation, so that it cannot be easily determined at present.

[Object] Therefore, an object of the present invention is to provide a non-volatile semiconductor memory device in which it is possible to easily determine whether or not the cause of a read failure is due to overerasure.

[0018]

A non-volatile semiconductor memory device according to the present invention has the principle diagram shown in FIG.
As shown in FIG. 3, a nonvolatile circuit having a plurality of bit lines Bl and a plurality of word lines Wl and having a plurality of real cell transistors 1 for storing and holding predetermined data corresponding to the intersections of the bit lines Bl and the word lines Wl A semiconductor memory device having the same bit line B as that of the real cell transistor 1.
a test cell transistor 2 which is connected to l and holds a predetermined fixed data set in advance, and a cell selection means 3 which selects the test cell transistor 2 or an arbitrary cell transistor in the real cell transistor 1. Data stored in the real cell transistor 1, and a current detection unit 4 for detecting a current flowing through a bit line Bl connected to the cell transistor when the cell selection unit 3 selects an arbitrary cell transistor. When erasing, the cell selecting unit 3 selects the test cell transistor 2 and the current detecting unit 4 detects whether or not a current flows through the bit line Bl connected to the test cell transistor. Therefore, it is possible to determine whether or not the real cell transistor 1 is in the over-erased state. It is.

[0019]

According to the present invention, when the data held in the real cell transistor is erased, the test cell transistor is selected by the cell selection means and the test cell transistor selected by the current detection means is connected to the bit line. It is detected whether or not a current is flowing through, and it is determined whether or not the real cell transistor is in the overerased state.

That is, if the current flows, it is determined that the cause of the read failure is due to over-erase, and it is easily determined whether the cause of the read failure is due to over-erase.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 2 and 3 are diagrams showing an embodiment of the non-volatile semiconductor memory device according to the present invention, and FIG. 2 is a diagram showing a main configuration of the present embodiment. First, the configuration will be described.

In FIG. 2, the same numbers as the numbers given to the principle diagram shown in FIG. 1 indicate the same parts. In FIG. 2, 1
Is a real cell transistor, 2 is a test cell transistor, 3 is a cell selection decoder which is a cell selection means, 4 is a sense amplifier which is a current detection circuit, Bl is a bit line and Wl is a word line.

The test cell transistor 2 is fixed to the data "0" in advance, and is selected only when the special bias for the test is used. As shown in FIG. 3, the cell selection decoder 3 includes an address buffer 5, a VHH detection circuit 6, inverters INV1 to INV4, and a NAND gate NAND, and based on an address signal obtained from the address buffer 5, the test cell transistor 2 An arbitrary cell is selected by outputting the selected decode output TD or the selected decode output RD of the real cell transistor 1.

The sense amplifier 4 is a differential type sense amplifier. Next, the operation will be described. First, as in the conventional example shown in FIG. 7, after the predetermined real cell transistor 1 is erased, the cell selection decoder 3 outputs the selection decode output TD of the test cell transistor 2.
Enter test mode.

When the test cell transistor 2 is selected, the real cell transistor 1 is in a non-selected state, so that no current should originally flow through the bit line Bl. However, when the real cell transistor 1 is in the over-erased state, a leak current flows in the bit line Bl even when the test cell transistor 2 is in the selected state.

Therefore, when the test cell transistor 2 is selected by the cell selection decode 3, whether or not a current flows through the bit line Bl is detected by the sense amplifier 4, so that a current flows through the bit line Bl. If so, it can be determined that the real cell transistor 1 is in the over-erased state. As described above, in the present embodiment, when erasing the data held in the real cell transistor 1, the test cell transistor 2 is selected by the cell selection decoder 3, and at this time, the test cell transistor 2 selected by the sense amplifier 4 is selected. It is possible to determine whether or not the real cell transistor 1 is in the over-erased state by detecting whether or not a current is flowing through the bit line Bl connected to.

Therefore, it is possible to easily determine whether or not the cause of the read failure is due to overerasure, and for example, it is possible to quickly confirm a device on the market that has been accidentally overerased by only electrical operation.

[0028]

According to the present invention, when the data held in the real cell transistor is erased, the test cell transistor is selected by the cell selection means and the bit line to which the test cell transistor selected by the current detection means is connected. It is possible to determine whether or not the real cell transistor is in the over-erased state by detecting whether or not a current is flowing through.

Therefore, if the current flows, it can be determined that the cause of the read failure is due to over-erase, and it can be easily determined whether the cause of the read failure is due to over-erase.

[Brief description of drawings]

FIG. 1 is a diagram showing a main configuration of a present embodiment.

FIG. 2 is a circuit diagram showing a differential voltage calculation means of FIG.

FIG. 3 is a circuit diagram showing the sense amplifier of FIG.

FIG. 4 is a sectional view of a memory cell in a conventional flash memory.

FIG. 5 is a circuit diagram showing a cell matrix configuration of a conventional flash memory.

FIG. 6 is a diagram for explaining a conventional operation example during erasing.

FIG. 7 is a flowchart of a conventional erasing algorithm.

FIG. 8 is a diagram showing a cell in an overerased state.

FIG. 9 is a diagram showing a recovery state by ultraviolet irradiation.

FIG. 10 is a diagram showing a cell returned to a normal state.

[Explanation of symbols]

 1 real cell transistor 2 test cell transistor 3 cell selection decoder (cell selection means) 4 sense amplifier (current detection circuit) 5 address buffer 6 VHH detection circuit INV1 to INV4 inverter NAND NAND gate Bl bit line Wl word line CG control gate FG floating Gate D Drain S Source PS Substrate C Memory cell WLx Word line BLx Bit line SLx Select line

Claims (1)

[Claims] 1. A non-volatile semiconductor memory device having a plurality of bit lines and a plurality of word lines, and having a plurality of real cell transistors for storing and holding predetermined data corresponding to intersections of the bit lines and the word lines. And a test cell transistor that is connected to the same bit line as the real cell transistor and holds preset predetermined fixed data, the test cell transistor, or an arbitrary cell transistor in the real cell transistor. And a current detection unit that detects a current flowing through a bit line connected to the cell transistor when an arbitrary cell transistor is selected by the cell selection unit. When erasing the retained data, the test cell transistor To determine whether or not the real cell transistor is in the over-erased state by detecting whether or not a current is flowing through the bit line connected to the test cell transistor selected by the current detection means. A characteristic non-volatile semiconductor memory device.