JPH08124392A - Method for correcting excessive writing of semiconductor memory device - Google Patents

Abstract

PURPOSE: To correct excessive writing to a normal writing state by making identification as to whether the excessive writing arises in selected pages or not and impressing an erasing voltage and writing voltage only on the word lines of selected pages in case the excessive writing arises. CONSTITUTION: Presence or absence of the excessive writing is discriminated (S4). The discrimination of the presence or absence of the excessive writing is executed by impressing the positive voltage (source voltage in this case) larger than the threshold voltage of an enhancement type cell and smaller than the threshold voltage of a cell subjected to the excessive writing on all the word lines within a block where the writing is executed. All the non-selected pages are made conducting when the source voltage is impressed and, therefore, whether the selected pages are conducting or not, i.e., the presence or absence of the excessive writing is discriminated by identifying the conduction and non-conduction between the respective bit lines and ground. Only the selected pages subjected to the excessive writing are erased (S5) and these selected pages are subjected to writing again (S6) when the excessive writing is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device overwriting correction method, which is suitable for eliminating defects caused by accidental overwriting during rewriting.

[0002]

^2. Description of the Related Art A NAND flash E ² PROM is
This is a non-volatile memory in which a plurality of double gate type MOS FET cells each having a floating gate electrically insulated from the surroundings in addition to a normal control gate are connected in series to each contact of the bit line. FIG. 5 shows a double gate type MOS.
It is sectional drawing of a FET cell. On the surface of the silicon substrate 7,
The source 1 and the drain 2 are formed with the channel 5 interposed therebetween, and the floating gate 4 is formed on the source 1 and the drain 2 and the channel 5 with the oxide film 6 interposed therebetween. A portion of the oxide film 6 on the drain 2 serves as a tunnel oxide film 6a. Further, a control gate 3 is formed on the floating gate 4 with an oxide film sandwiched between them, and these are entirely covered with the oxide film.

Data is stored in the double-gate MOS FET cell by storing "0" or "1" depending on whether or not electrons are present in the floating gate 4. That is, if a high voltage is applied to the control gate 3 and the potential of the channel 5 between the drain 2 and the source 1 is set to 0 V, a high electric field is generated in the oxide film 6 between the floating gate 4 and the channel 5. A tunnel current flows through the tunnel oxide film 6a, electrons are captured in the floating gate 4, and the threshold voltage of the memory cell rises (writing). On the contrary, if the potential of the control gate 3 is set to 0 V and a high voltage is applied to the channel 5, electrons are extracted from the floating gate 4 to the channel 5, and the threshold voltage of the memory cell drops (erasure).

FIG. 4 shows a depletion type (L1), an enhancement type (L2), and a double gate type MOS FET.
3 is a graph showing a conduction state in the case of overwriting (L3).

When electrons are trapped in the floating gate 4,
The threshold voltage of the MOS FET rises (L2) and becomes an enhancement type MOS FET. Conversely, when electrons are emitted from the floating gate, the threshold voltage of the MOS FET drops (L2) and the depletion type MOS FET
Becomes

Therefore, when a certain cell is selected and data is read out, 0 V is applied to the control gate, which is "1" (depletion type) when conducting and "0" (enhancement type) when not conducting. Identify.

As described above, the NAND flash E
² The data of the selected cell in the PROM is read by judging conduction or non-conduction when 0V is applied to the control gate of the selected cell, so it is necessary to keep all the non-selected cells in the same block conductive. There is. Therefore, in order to bring all the depletion-type and enhancement-type non-selected cells into the conductive state, a positive voltage higher than the threshold voltage of the enhancement-type cells must be applied to the control gates of all the non-selected cells.

Conventional NAND flash E ² PROM
In the above, since the voltage applied to the control gate of the non-selected cell was the power supply voltage V _CC , the threshold voltage of the enhancement type cell must be kept lower than the power supply voltage V _CC . Excessive writing is performed and the threshold voltage is the power supply voltage V _CC.
When the voltage becomes higher than L3 (L3 in FIG. 4), even if the power supply voltage V _CC is applied to the control gate of the non-selected enhancement type cell, the state does not become conductive, and the data of other cells are read. You can't do it normally.

As a method of preventing overwriting, as in the case of the ultraviolet erasable EPROM, the operation of verifying whether or not the cell is enhanced by applying a short write pulse voltage (verify) is repeated to erase the cell. A write retry method is used in which the threshold voltage is gradually increased.

The pulse width of the verify write pulse voltage in the write retry method can be any width, but normally rewriting is performed with a constant pulse width.
Set the threshold voltage of the enhancement cell to a predetermined value.

[0011]

However, although rewriting is performed with a constant pulse width when performing verification, there is a problem that excessive writing occurs which is considered to be caused by variations in cell characteristics. .

There are roughly two types of modes of occurrence of overwriting, and there are cases where overwriting always occurs in a specific cell and cases where overwriting occurs accidentally.

If there is a cell in which overwriting always occurs, it can be removed as a defective product at the time of inspection. However, when overwriting occurs accidentally in a certain cell, the frequency of occurrence of accidental overwriting is very low, such as several out of several hundreds, and therefore overwriting must be recognized during inspection before shipment. For example, a NAND flash E ^{2 in} which there is a cell in which accidental overwriting may occur
It is impossible to remove the PROM.

Therefore, if accidental overwriting occurs in the shipped NAND flash E ² PROM, the data cannot be read normally and the data cannot be used.

The present invention has been made in view of the above problems, and an object thereof is a NAND flash E ² PROM.
In the rewriting, if an accidental overwriting occurs in a cell, the overwriting state of the cell can be corrected to a normal writing state.

[0016]

According to the overwriting correction method of a semiconductor memory device of the present invention, a plurality of double gate type MOS Fs connected in series to a plurality of bit lines respectively.
NAN composed of multiple blocks with ET cells
In the rewriting of the D-type flash E ² PROM, a selected page in which writing has been performed among pages in which a plurality of double-gate type MOS FET cells in the same block whose control gates are connected to the same word line are used as a unit. Of the double-gate MOS FET cell which is larger than the threshold voltage when the double-gate MOS FET cell is enhanced and is overwritten in the word line of the non-selected page other than the selected page. By applying a voltage lower than the threshold voltage and checking whether or not there is conduction between the bit line and ground, it is possible to identify whether or not overwriting has occurred on the selected page, and overwriting occurs. If so, correct the write state by applying the erase voltage and the write voltage only to the word line of the selected page. And it features.

Writing is performed by repeatedly applying a write voltage having a predetermined pulse width to the double-gate MOS FET cell and inspecting whether or not the double-gate MOS FET cell has been enhanced to repeat the double-gate MOS FET cell. It is preferable that the writing method is such that the threshold voltage value of the FET cell is gradually increased.

Further, writing is performed by a double gate type MOS.
The threshold voltage of the double-gate MOS FET cell is determined after repeating the application of the write voltage having a predetermined pulse width to the FET cell and the inspection as to whether the double-gate MOS FET cell is enhanced or not for the first predetermined number of times. It may be preferable to inspect whether or not the voltage value is a predetermined threshold voltage.

The overwriting is corrected by applying the erase voltage and the write voltage once to the word line of the selected page and then applying a predetermined voltage to the word line of the selected page and the word line of the non-selected page, respectively. It is good to inspect whether it has occurred.

Further, to correct the overwriting, whether the erase page and the programming voltage are applied and whether the overwriting has occurred is repeated a second predetermined number of times, and then the normal writing can be performed on the selected page. It is good to judge whether or not.

[0021]

The non-structure includes a word line of a selected page on which writing has been performed and a page which has been erased for rewriting and has not been written or a page which has already been written and has been confirmed to have not overwritten. A voltage higher than the threshold voltage when the double-gate MOS FET cell is enhanced and lower than the threshold voltage of the overwritten double-gate MOS FET cell is applied to the word line of the selected page. Therefore, by checking whether or not there is a conduction state between the bit line and the ground,
It is possible to identify whether overwriting has occurred in the selected page. If overwriting has occurred,
Since the erase voltage and the write voltage are applied only to the word line of the selected page, the normal write can be corrected.

Writing is repeated by applying a write voltage having a predetermined pulse width to the double-gate MOS FET cell and inspecting whether the double-gate MOS FET cell has been enhanced or not, thereby repeating the double-gate MOS FET cell. Since the writing method is such that the threshold voltage value of the FET cell is gradually increased, the occurrence of excessive writing is suppressed.

Further, writing is performed by double gate type MOS.
The threshold voltage of the double-gate MOS FET cell is determined after repeating the application of the write voltage having a predetermined pulse width to the FET cell and the inspection as to whether the double-gate MOS FET cell is enhanced or not for the first predetermined number of times. Since it was decided to inspect whether or not the voltage value is a predetermined threshold voltage,
It is possible to exclude defective products that cannot enhance the double gate MOS FET cell by the write operation.

The overwriting is corrected by applying the erase voltage and the write voltage once to the word line of the selected page and then applying a predetermined voltage to the word line of the selected page and the word line of the non-selected page, respectively. Since it is supposed to re-examine whether or not it has occurred, it is possible to surely correct excessive writing to normal writing, and if it cannot be corrected, appropriate measures can be taken.

Further, to correct the overwriting, whether the erase page and the programming voltage are applied and whether or not the overwriting has occurred is repeated a second predetermined number of times, and then normal writing can be performed on the selected page. Since it is determined whether or not the accidental overwriting can be surely corrected to the normal writing, if it cannot be corrected, it can be determined as unusable and appropriate measures can be taken.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for correcting overwriting of a semiconductor memory device according to the present invention will be described below with reference to the drawings. FIG. 1 is a flow chart of a method for correcting overwriting of a semiconductor memory device according to the present invention, FIG. 2 is a flow chart of writing by a write retry method, and FIG. 3 is a NAND.
FIG. 3 is a circuit diagram showing a circuit configuration of a type flash E ² PROM.

As shown in the circuit diagram of FIG. 3, one block BLK1 in the NAND flash E ² PROM is
It is configured as follows. Bit line BTL1, BT
L2 and BTL3 are respectively provided with a selection transistor BST.
A cell area C1 in which a plurality of double-gate MOS FET cells are connected in series via 1, BST2, BST3,
C2 and C3 are connected, and select transistors BS
It is grounded via T4, BST5, and BST6. The selection transistors BST1, BST2, BST3 are connected to the selection transistors BST4, BST4 by the block selection line BSL1.
BST5 and BST6 are connected by the block selection line BSL2.
Each is controlled. Double gate type M in each cell area
Of the OS FET cells, the word lines WDL1 and WDL
2, each page is composed of cells connected to WDL3. Here, page P1 is connected by cells connected to word line WDL1.

A method of rewriting while overwriting occurs when rewriting the NAND flash E ² PROM will be described with reference to the flowchart of FIG. NAND flash E
² PROM is a page write method in which a unit of an arbitrary number of addresses is used in a write operation, and is a block erase method in which a unit of an arbitrary number of pages is used in an erase operation. In the overwriting correction method according to the present invention, since it is necessary to erase only an arbitrary page, it is possible to erase a voltage suitable for page erase, that is, a page to be erased without affecting the data of other pages. A page erasing circuit that generates a voltage of a certain magnitude is incorporated in advance.

First, all data in the block to be rewritten is erased by block erasing (S1). The cells in the erased block are depleted and all become conductive regardless of the presence or absence of a bias voltage. An arbitrary page is selected from the pages that have not been written yet (S2), and writing to the selected page is performed (S3).

Writing is performed by the write retry method shown in the flowchart of FIG. First, a write pulse voltage is applied (WS1). Although the pulse width of the write pulse voltage is arbitrary, it is fixed here, and the pulse width is such that it is necessary to apply the voltage a certain number of times to enhance the cell. After applying the write pulse voltage, the threshold voltage V _{TH of the} cell is measured (WS2) and compared with the threshold voltage V _E of the enhancement type cell. When the threshold voltage V _TH of the cell has reached the threshold voltage V _E of the enhancement type cell, the writing is completed (WS4), but the threshold voltage V _TH of the cell is higher than the threshold voltage V _{E of the} enhancement type cell. If it is smaller, it is discriminated whether or not the number of voltage applications up to that point exceeds a predetermined number (WS3).
If the number of times of voltage application has not exceeded the predetermined number of times, the write pulse voltage is applied again. If the number of times of voltage application has exceeded the predetermined number of times, a write failure determination is performed (WS5) and writing is stopped. If writing cannot be performed even though the write pulse voltage is applied enough times to enhance the cell, it is determined that one of the cells in the selected page is defective, and the selected page is selected. There is no choice but to take measures such as switching to a redundant circuit. Writing is performed as described above.

Returning to FIG. 1, after the writing (S3) is completed, it is determined whether or not there is excessive writing (S4). Whether or not there is overwriting is determined by an appropriate value that is higher than the threshold voltage V _E of the enhancement type cell and lower than the threshold voltage of the overwritten cell in all the word lines in the block that is being rewritten. Is applied by applying a positive voltage. In this embodiment, the power supply voltage V _CC is applied. Non-selected pages other than the selected page are of two types: a page that has been erased for rewriting and has not yet been written, and a page that has already been written and it has been confirmed that overwriting has not occurred. Therefore, the power supply voltage V _CC
When applied, all non-selected pages become conductive. Therefore, by identifying conduction / non-conduction between each bit line and ground, whether or not the selected page is conductive, that is, the selected page It is possible to determine whether or not excessive writing has occurred.

If no overwriting has occurred, the presence or absence of an unselected page is identified (S8), and if there is an unselected page, one page is selected from the unselected pages (S8).
2) If there is no unselected page, rewriting ends (S9).

If excessive writing has occurred, only the overwritten selected page is erased (S5), and the selected page is rewritten (S6). The writing at this time is also performed by the writing retry method shown in the flowchart of FIG.

After the rewriting (S6) is completed, it is determined whether or not there is excessive writing in the selected page (S7). If excessive writing has not occurred, the presence or absence of an unselected page is identified (S8), and if there is an unselected page, one page is selected from the unselected pages (S2), and there is no unselected page. In this case, the rewriting ends (S9).

If excessive writing has occurred in the selected page, it is determined whether or not the number of write operations performed up to that point exceeds a predetermined number (S10). If it exceeds the predetermined number of times, the rewriting is stopped (S1).
1). In this case, there is no choice but to take measures such as switching the selected page to a redundant circuit by judging that the overwriting that has occurred in the selected page is not an accidental one, but is due to a defective cell in the selected page. .

If the predetermined number of times is not exceeded,
Erase selected page (S5), write to selected page (S5)
6) The presence / absence of excessive writing is determined (S7). Depending on the presence / absence of excessive writing, the rewriting operation is advanced or stopped according to the above procedure.

When the rewriting operation is completed by the procedure described above, the accidental excessive writing is surely eliminated, the data can be read normally, and the occurrence of the operation abnormality can be prevented. In addition, NAND flash E ² PR
It is possible to identify whether the OM itself is good or bad.

[0038]

As described above, since the NAND flash E ² PROM is rewritten by using the overwriting correction method for a semiconductor memory device according to the present invention, it is possible to discriminate whether or not the overwriting has occurred. , It is possible to eliminate accidental overwriting and correct it to normal writing.

Since the writing is performed by the writing retry method, the occurrence of excessive writing is suppressed.

Further, since the number of times of writing by the writing retry method is limited, defective products which cannot enhance the double gate type MOS FET cell by the writing operation can be excluded.

The overwriting is corrected by applying the erase voltage and the writing voltage once to the word line of the selected page and then reinspecting whether the overwriting has occurred. Can be corrected to normal writing, and if it cannot be corrected, appropriate measures can be taken.

Further, since the number of times the erase voltage and the write voltage are applied to correct the overwriting and the number of times of checking whether or not the overwriting has occurred are limited, the accidental overwriting is surely performed. It can be corrected to normal writing, and if it cannot be corrected, it can be judged as unusable and appropriate measures can be taken.

[Brief description of drawings]

FIG. 1 is a flowchart of a method for correcting overwriting of a semiconductor memory device according to the present invention.

FIG. 2 is a flowchart of writing by a write retry method.

FIG. 3 is a circuit diagram showing a circuit configuration of a NAND flash E ² PROM.

FIG. 4 is a graph showing conduction states of a depletion type, an enhancement type, and an overwritten state of a double gate type MOS FET cell.

FIG. 5 is a sectional view of a double gate MOS FET cell.

[Explanation of symbols]

 BLK1 block P1 page C1 to 3 cell area BTL1 to 3 bit line WDL1 to 3 word line BSL1 and 2 block selection line BST1 to 6 block selection transistor L1 graph showing conduction state of depletion type cell L2 showing conduction state of enhancement type cell Graph shown L3 Graph showing conduction state of overwritten cell 1 Source 2 Drain 3 Control gate 4 Floating gate 5 Channel 6 Oxide film 6a Tunnel oxide film 7 Silicon substrate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792

Claims (5)

[Claims] 1. A NAND flash E ² PR comprising a plurality of blocks each having a plurality of double-gate MOS FET cells connected in series to a plurality of bit lines.
In the rewriting of OM, the word of the selected page in which writing is performed among pages in which the plurality of double-gate MOS FET cells in the same block whose control gates are connected to the same word line are used as a unit Line and the word lines of non-selected pages other than the selected page are larger than the threshold voltage when the double gate type MOS FET cell is enhanced and are overwritten, and the double gate type MOS FET cell is overwritten. By applying a voltage lower than the threshold voltage and checking whether or not there is a conduction state between the bit line and the ground, it is discriminated whether or not overwriting has occurred in the selected page, If excessive programming has occurred, normal programming is performed by applying the erase voltage and programming voltage only to the word line of the selected page. Excess writing correction method of a semiconductor memory device characterized by modifying the look state. 2. The double gate type MOS is used for the writing.
The application of the write voltage having a predetermined pulse width to the FET cell and the inspection as to whether or not the double gate type MOS FET cell is enhanced are repeated to determine the threshold voltage of the double gate type MOS FET cell. 2. The overwriting correction method for a semiconductor memory device according to claim 1, wherein the writing method is such that the value is gradually increased. 3. The double gate type MOS is used for the writing.
After the application of the write voltage having the predetermined pulse width to the FET cell and the inspection as to whether or not the double gate type MOS FET cell is enhanced are repeated a first predetermined number of times, the double gate type MOS FET 3. The overwriting correction method for a semiconductor memory device according to claim 2, further comprising inspecting whether or not the value of the threshold voltage of the cell is a predetermined threshold voltage. 4. The overwriting correction is performed by applying the erase voltage and the write voltage once to the word line of the selected page, and then applying the word line of the selected page and the word of the non-selected page. 2. The overwriting correction method for a semiconductor memory device according to claim 1, wherein the predetermined voltage is applied to a line to check whether overwriting has occurred. 5. The correction of the overwriting is performed by repeating the application of the erase voltage and the programming voltage and the inspection of whether the overwriting has occurred a second predetermined number of times, and then the selected page. 5. The method according to claim 4, wherein it is determined whether normal writing can be performed.