JPH05314783A - Erasure method for nonvolatile semiconductor memory provided with erasure function and writing device - Google Patents

Abstract

PURPOSE:To correct excess erasure by detecting the excess erasure and writing for an excess erasure memory cell with a weaker condition than a normal writing condition. CONSTITUTION:When the memory cell of the memory cell array 1 of an E<2> PROM is erased, the memory cell is read through a sense amplifier 6 and compared with the data of a data latch part 8 by a comparator 7 and the presence of the excess erasure is detected. Then when the existence of the excess erasure is decided, a write control part 10 is controlled by the comparator 7 and the memory cell is written with the weaker condition than the normal condition and the excess erasure is corrected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for erasing a non-volatile semiconductor memory device, and more particularly, a method for erasing a non-volatile semiconductor memory device capable of correcting over-erasing when an over-erased memory cell is generated by erasing. The present invention relates to a non-volatile semiconductor memory device having an erasing circuit capable of correcting excessive erasing and a writing device having an erasing function for correcting excessive erasing.

[0002]

^2. Description of the Related Art Stack gate type Flash E ² PR
The OM can be rewritten, but it must be erased when it is rewritten. Specifically, erasing is performed by applying a voltage with a high negative absolute value to the control gate and applying a positive voltage of about 5 V to the source to tunnel-inject the electrons in the floating gate to the source.

FIG. 8 is a flow chart showing the procedure of a conventional method of erasing a nonvolatile semiconductor memory device. First, an address and data are set, a counter that counts the number of times of erasing (there is a hardware counter or a software counter) is reset, and all memory cells belonging to the word line to which the address is set are erased. .. Then, determine whether the erasure has been completed,
If the determination result is Yes, erasing the memory cell of the word line is completed. If the determination result is No, then Ye
The erasing is repeated until the judgment result of s is obtained.

If complete erasure cannot be performed even after erasing a predetermined number of times, for example, 3000 times, it is determined to be defective. In the past, in general, it was determined whether or not erasing was sufficiently performed, but it was not made to determine the presence or absence of excessive erasing after erasing.

[0005]

By the way, in the prior art, since the presence or absence of overerase was not confirmed (verified) after erasing, there were the following problems. First, the excessive erase will be described. This means that the electrons are excessively extracted from the floating gate to the source, and a normal-on state is brought about. That is, 0
The threshold value, which must be appropriately higher than V, is 0V to 0V or less. Then, this causes an inconvenience that all the cells of the same bit line as that of the overerasure at the time of reading all output "1" as data, which causes a malfunction and is not preferable. Such overerasure is
This occurs because the thickness of the gate insulating film of each memory cell becomes non-uniform and the characteristics vary, and the variation can be reduced with the development of the manufacturing technology. be able to. But,
Complete elimination is difficult or impossible.

The present invention has been made to solve such a problem, and an object of the present invention is to make it possible to correct excessive erasing of overerased memory cells after erasing.

[0007]

According to the present invention, after erasing processing is performed, presence / absence of overerasure is detected for each memory cell subjected to the erasing processing, and normal operation is performed on the overerased memory cell. It is characterized in that overwriting is corrected by performing writing under a condition weaker than the writing condition.

[0008]

According to the present invention, since light writing is performed on an overerased memory cell, it is possible to raise the threshold value of 0 V or lower to obtain a normal erased state.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of erasing a nonvolatile semiconductor memory device, a nonvolatile semiconductor memory device having an erasing function, and a writing device according to the present invention will be described in detail below with reference to illustrated embodiments. FIG. 1 is a circuit diagram showing one embodiment of a nonvolatile semiconductor memory device of the present invention, and FIG. 2 is a flow chart showing an erase operation. In the drawing, 1 is a memory cell array, 2 is a row decoder,
3 is a column decoder, 4 is an internal address generator, 5 is an address buffer, 6 is a sense amplifier, 7 is a comparator for comparing the data of the data latch unit 8 with the data of the sense amplifier 6, and 9 is an input / output buffer. ..

Reference numeral 10 is a write controller, 11 is a write pulse generator, 12 is a write verify pulse generator, 13 is an erase controller, 14 is an erase pulse generator, 15 is an erase verify pulse generator, and 16 is all bits. This is an all-bit non-selection circuit that is deselected. FIG. 2 is a flowchart showing an erasing method including data writing. In the erasing method of the present nonvolatile semiconductor memory device, erasing is performed in word line units, and FIG. 2 shows how to erase one word line and write data.

First, an address to be erased is selected, data is set, and a counter for counting the number of erases is reset. Then, a write pulse is applied once to the word line of the set address. That is, prewriting is performed. This is performed in order to make Vth of each cell uniform by writing to a cell that has not been written before erasing. Then, the word line of the set address is erased (each memory cell of the word line), and it is determined whether or not the erase is performed. If the judgment result is No, it is judged whether or not the count value of the counter for counting the number of times of erasure is 3000, and if the judgment result is No, the value of the counter is incremented by 1 and re-erasure is performed. If a determination result of Yes, which means that the erase count has reached 3000, is determined to be defective.

By the way, when the result of the judgment as to whether or not the erasing is performed is Yes, data is written, and then, whether or not the memory cell which should be "0" by the data writing is "0". It is determined whether or not, and if a determination result of No is obtained, the data is written again. And Ye
When the determination result of s is obtained, all the bits are deselected. As described above, the flow shown in FIG. 2 has a data writing step.

Next, a row address for selecting the word line just erased is set. Next, a column address reset is performed to select the first bit line among the bit lines. next,
It is determined whether the memory cell is not over-erased. If the determination result is No, that is, if the memory cell is over-erased, writing is performed under a weaker (lighter) condition than the normal write condition.
This is done in order to raise the threshold voltage of the memory cell which is too low to bring it into a normal erased state.

FIG. 3A shows a normal writing condition.
FIGS. 3B to 3D show Condition Examples 1 to 3 which are lighter than a normal write condition for eliminating excessive erase, and FIG. 3B shows the original write voltage. Write voltage (12
This is the case when the voltage is lower (6 V) than V). FIG. 3C shows the case where the pulse width of the write voltage is narrower (3 μ) than the original value (10 μs), and FIG. 3D shows the write voltage low (6 V) and the pulse width narrow. (3 μs) is shown.

When the writing for correcting the excessive erasure is completed, it is judged whether or not the number of times of writing reaches 25 times, and if the judgment result of Yes is obtained, it is treated as defective. When the determination result of No is obtained, the count value of the write number counter is incremented by 1, and it is determined again whether it is over-erasure.

The result of determination as to whether or not it is over-erased is Yes.
If it is, it is determined whether or not the cell is the column address of the last bit. If the determination result is No, the column address is incremented by 1, the counter that counts the number of times of writing is reset, and the process returns to the determination step as to whether or not it is over-erase. If the result of the determination step for determining whether or not the cell is the column address of the last bit is Yes, that is, if all cells are erased and data is written to the word line, and correction of excessive erase is completed, address reset, Reset the data and exit. That is, erasing of one word, writing of data, and correction of excessive erasing are completed.

FIG. 4 shows erase and erase verify.
7 is a time chart in the write and write verify operations. When the erase control signal is generated from the erase controller 13, the erase pulse generator 14 generates one erase pulse. Then, the erase verify pulse is immediately generated and the verify is performed. If it cannot be erased, the sense output becomes "0" and the comparator output becomes "0".
If the erase operation is performed again, the erase verify is performed again, and the sense output becomes “1”, it means that the erase operation is successful (whether or not it is over-erased), and the comparator Output becomes "1". Then, next, data write and write verify are performed.

At the time of writing, a write control signal is generated, one write pulse is generated, and one write verify pulse is generated.
Generates a pulse. This is performed until the sense output becomes "0" and the comparator output becomes "1". FIG. 5 is a time chart showing the verifying operation of whether or not overerasure has occurred and the overerasure correction operation.

First, when the column address is reset and the leading address of the word line is specified, all the bits are deselected, and when the sense output becomes "0", it means that the bit is passed. Then, the comparator output becomes "1" indicating acceptance. Then, it advances to the next address (next bit). In the example shown in FIG. 5, there is overerasure in the memory cell at the address A3. There is over-erasure and the comparator output is "1"
If it does not occur, the non-selected state of all bits is stopped, a write control signal is generated, a row address is set, and excessive erasing by light writing is corrected. Then, when it is confirmed that the over-erasure has been corrected, the process moves to the next address.

FIG. 6 is a flowchart for performing a light write for correcting erase and overerase. The difference from the flowchart shown in FIG. 2 is that there is no step for writing data. The erasing method is executed by the CPU 17 incorporated in the nonvolatile semiconductor memory device,
The program is stored in the built-in ROM 18.
As shown in FIG. 7, if the ROM writer is provided with an erasing function capable of correcting the excessive erasure, erasing and data writing can be performed by the ROM writer while correcting the excessive erasure.

[0021]

According to the erasing method of the non-volatile semiconductor memory device of the present invention, the presence or absence of over-erase is detected for each memory cell subjected to the erasing process, and the over-erasing memory cell is detected. It is characterized in that overwriting is corrected by performing writing under a condition weaker than the normal writing condition. Therefore, according to the erasing method of the nonvolatile semiconductor memory device of the present invention, since writing is performed to the overerased memory cell, it is possible to raise the threshold value of 0 V or lower to obtain a normal erased state.

The nonvolatile semiconductor memory device of the present invention detects the presence or absence of overerasure for each memory cell that has undergone the erase process and then performs the normal write operation for the overerased memory cell. It is characterized by incorporating an erasing circuit for correcting over-erase by performing writing under a condition weaker than the condition. Therefore, according to the nonvolatile semiconductor memory device of the present invention, it is possible to perform erasing without using an erasing device different from the nonvolatile semiconductor memory device and to prevent excessive erasing due to its own function.

The erasing device of the present invention detects the presence or absence of excessive erasing in each memory cell that has undergone the erasing process and then performs the erasing process, and detects the excessive erasing memory cell from the normal writing condition. Is also equipped with an erasing function for performing overwriting by performing writing under weak conditions. Therefore, according to the writing device of the present invention, erasing and data writing can be performed while preventing excessive erasing.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing one embodiment of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a flowchart showing one embodiment of an erasing method of the nonvolatile semiconductor memory device of the present invention.

3A to 3D are time charts showing different write conditions, FIG. 3A showing a normal write condition, and FIGS. 3B to 3C showing a normal write condition. The different conditions 1 to 3 suitable for correcting the slight over-erasure are shown.

FIG. 4 is a time chart showing erase, erase verify, write, and write verify.

FIG. 5 is a time chart showing verification of overerasure and overerasure correction writing.

FIG. 6 is a flowchart showing another embodiment of the erasing method of the nonvolatile semiconductor memory device of the present invention.

FIG. 7 is a circuit block diagram showing one embodiment of the writing device of the present invention.

FIG. 8 is a flowchart showing a conventional example of an erasing method of a nonvolatile semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 memory cell array 2 row decoder 3 column decoder 7 comparator 10 write controller 12 write verify pulse generator 13 erase controller 15 erase verify pulse generator 19 write device

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/792 H01L 29/78 371

Claims (3)

[Claims] 1. After erasing processing, presence / absence of over-erasing is detected for each memory cell subjected to the erasing processing, and the over-erasing memory cell is detected under a condition weaker than a normal write condition. Erase method for a non-volatile semiconductor memory device characterized by performing overwriting to correct excessive erasure 2. After performing the erasing process, the presence or absence of overerasing is detected for each memory cell that has undergone the erasing process, and the overerasing memory cell is detected under a condition weaker than a normal write condition. A non-volatile semiconductor memory device having a built-in erasing circuit for writing to correct excessive erasing 3. After erasing processing, presence / absence of over-erasing is detected for each memory cell subjected to the erasing processing, and the over-erasing memory cell is detected under a condition weaker than a normal write condition. Writing device having an erasing function for writing to correct excessive erasing