JPH08106793A - Flash electrically erasable programmable rom and erasing method thereof - Google Patents

Abstract

PURPOSE: To realize an erase operation with a lower voltage and higher accuracy and in a small erase unit by performing a first write back operation to eliminate a memory cell overerased and a second write back operation to compress variations in threshold voltage sequentially. CONSTITUTION: An address generation circuit 1505 generates an address for a writing, erasing or writing back operation. A selector prewriting circuit 1504 performs a prewriting per word line and an automatic deletion control circuit 1502 performs an erasing operation. A write back control circuit 1511 detects a data line where a memory cell suffering an excessive deletion to a negative threshold voltage exists to accomplish a writing operation at a potential reduced in terms of an absolute value with respect to the writing operation and detects a memory cell which has been overerased to a small threshold voltage to accomplish a writing operation at the same potential sequentially. This enables the securing of a wide temperature guaranteeing range thereby realizing an erase suspending function during the period other than the period during which a first writing back is completed from the starting of the erasing operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a batch erasing type non-volatile memory device (hereinafter, simply referred to as a flash memory) and a technique effectively applied to its erasing method.

[0002]

2. Description of the Related Art A flash memory is a non-volatile memory element (hereinafter simply referred to as a memory cell) in a write operation.
By setting the drain potential of the device to about 4V and the word line connected to the control gate to about 11V, hot electrons generated near the drain are injected into the floating gate to raise the threshold voltage (logic "0"). ). In the erase operation, the source potential is set to about 4 V, the word line is set to about −10 V to generate a tunnel current, and the charge accumulated in the floating gate is extracted to bring the threshold voltage to a low state (logic “1”). To do.

As shown in FIG. 23A, in the initial state before erasing, there are the memory cell group 301 corresponding to "1" and the memory cell group 302 corresponding to "0" as described above. Before reading, select "1" memory cells and perform write operation (pre-write) and read operation (pre-verify) before all memory cells are in "0" state as shown in (B). After doing, erase all at once like (C)
(erase) and read operation (erase verify).

At this time, an over-erased state (depletion failure) occurs due to variations in threshold voltage due to batch erasing due to process variations such as tunnel oxide film thickness and impurity profile, and influence of parasitic resistance of internal potential. I will end up. If even one memory cell having such a negative threshold voltage exists, a current flows through the memory cell even if the word line to which the memory cell is connected is in a non-selected state, and reading becomes impossible. Therefore, various proposals have been made to detect the overerased memory cells and perform write back to prevent the depletion failure. Regarding such measures for depletion failure, JP-A-4-6698, JP-A-4-222994, and JP-A-5-896.
No. 88 publication is available.

[0005]

In the flash memory, the erase operation is slower than the read or write operation.
Therefore, in order to improve usability, even during the erase operation, the erase operation is temporarily stopped by inputting a certain command so that the memory cells other than the erase target can be read (hereinafter, such a function will be described). Erase suspend function).

Recently, there has been an increasing demand for reduction of the erase unit for the flash memory for the purpose of replacing files and disk memories. On the other hand, when the memory array is created as in the conventional case shown in FIG. 22, the memory array size increases due to the division of the source line.

Therefore, as shown in FIG. 2, it is conceivable to reduce the erase unit by the applied voltage, instead of reducing the erase unit by dividing the source line. That is,
A voltage of -10V is applied to the word line W006 to which the memory cell to be erased is connected, a voltage of 2V is applied to the word line to which the memory cell to be non-erased is connected, and a voltage of 4V is applied to the source line. A potential difference of 14 V is applied between the control gate and the source of the memory cell to be erased, and the erasing proceeds. With such a method, the erase unit can be reduced to the word line unit (401A) without increasing the memory array size as in the conventional source line dividing method. Further, also in the conventional erase unit (401B), by applying −10 V to a plurality of word lines, it is possible to similarly erase all at once.

However, in the memory array configuration as shown in FIG. 2, while it is advantageous in that the erase unit is reduced,
It has been clarified by the research of the inventor of the present invention that a problem occurs in the erase suspend function. For example, the memory cell 41
When 6 is depleted, the memory cell 41 to be erased
411, 412, 413 which are not to be erased except 4, 415
Also becomes unreadable. That is, it is necessary to delay the suspend operation until a depletion defect is detected and writing (writing back) is completed.

Further, the above-mentioned write-back method has a problem that the guaranteed power supply lower limit Vccmin is deteriorated by the write-back. Also in the flash memory, a reduction in power supply voltage Vcc of about 3 V is under study, and the threshold voltage due to the erasing operation has to be lowered with such a reduction in power supply voltage. Is more likely to occur, which is a major obstacle to lowering the power supply voltage of the flash memory.

An object of the present invention is to provide a batch erasing type non-volatile memory device and a method of erasing the same, which realizes a highly accurate erasing operation in small erasing units. Another object of the present invention is to provide a batch erasing type nonvolatile memory device which realizes an erasing operation at a low power supply voltage and an erasing method thereof.
Another object of the present invention is to provide a batch erasing type nonvolatile memory device which realizes stable operation at a low voltage and an erasing method thereof. Still another object of the present invention is to provide a batch erasing type non-volatile memory device having an erasing interruption function and realizing an erasing operation in small erasing units, and an erasing method thereof. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, in the batch erasing type nonvolatile memory device including a memory array in which memory cells arranged in a matrix are arranged so that the electric charges accumulated in the floating gate by the write operation are discharged to the source side and erased, Sometimes, a pre-write operation is performed in which a memory cell in an erase unit is read and a write operation and a write determination operation are performed on a memory cell in which charges are not accumulated in the floating gate, and an erase reference voltage is applied to the memory cell in the erase unit. The erase operation for performing the erase operation and the erase determination operation collectively, and the data line in which the memory cell over-erased to the negative threshold voltage exists in the erase unit is detected, and the memory provided in the data line is detected. Writing to the cell at a potential that is made smaller in absolute value than the above writing operation A first write-back operation to be performed and a memory operation in which over-erased to a threshold voltage smaller than a desired erased state in the erase unit is detected, and a write operation is performed at a potential similar to that of the first write-back operation. An automatic erase circuit for sequentially performing the second write back operation for performing the above is provided.

[0012]

According to the above-mentioned means, overerasure (depletion) which is the cause of read failure in the first write-back operation
The erased memory cell can be eliminated, and the variation of the threshold voltage in the erased state can be suppressed by the second write-back operation, so that a wide temperature guarantee range can be secured, and the first erased operation can be started. Since it is necessary to prohibit the erase suspension only while the write-back of the above is completed, it is possible to realize the erase suspend function in other cases.

[0013]

The outline of other typical inventions among the inventions disclosed in the present application will be briefly described as follows. That is, in the batch erasing type nonvolatile memory device including a memory array in which memory cells arranged in a matrix are arranged so that the electric charges accumulated in the floating gate by the write operation are discharged to the source side and erased, Sometimes, a pre-write operation is performed in which a memory cell in an erase unit is read and a write operation and a write determination operation are performed on a memory cell in which charges are not accumulated in the floating gate, and an erase reference voltage is applied to the memory cell in the erase unit. The erase operation for performing the erase operation and the erase determination operation collectively, and the data line in which the memory cell over-erased to the negative threshold voltage exists in the erase unit is detected, and the memory provided in the data line is detected. Writing to the cell at a potential that is made smaller in absolute value than the above writing operation A first write-back operation to be performed and a memory operation in which over-erased to a threshold voltage smaller than a desired erased state in the erase unit is detected, and a write operation is performed at a potential similar to that of the first write-back operation. The second write back operation for performing the above is sequentially performed.

[0014]

According to the above means, the overerased (depleted) memory cell which is the cause of the read failure can be eliminated by the execution of the first write-back operation, and the erased state can be maintained by the execution of the second write-back operation. Since the variation of the threshold voltage is compressed, a wide temperature guarantee range can be secured, and the erase interruption can be prohibited only during the period from the start of the erase operation to the completion of the first write-back. The erase suspend function can be added.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an overall block diagram of a flash memory according to the present invention. Each circuit block in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The memory cell array 101 is provided with a control gate and a floating gate, as will be described later, and memory cells are arranged in a matrix so that the electric charge accumulated in the floating gate by the write operation is discharged to the source side for erasing. Consists of X
The decoder 102 forms a selection signal of a word line to which the control gate of such a memory cell is connected. The Y decoder 103 performs a selection operation of a data line (also called a bit line or a digit line) to which the drain of the memory cell is connected.

The control circuit 104 judges the operation mode by a signal supplied from the outside, detects a read signal from a selected data line and sends it out from an external terminal, or a write input from an external terminal. A writing circuit for transmitting data to the selected data line and a circuit for performing sequence control of a series of writing and erasing operations are included.

FIG. 2 shows a circuit diagram of an embodiment of the memory cell array. In the figure, the data line D00
1-D006, word lines W001-W006, these data lines D001-D006 and word lines W001-W001.
A memory cell provided at the intersection of W006 is illustrated as a representative. The control gates of the memory cells are connected to the corresponding word lines W001 to W006,
The drains of the memory cells have corresponding data lines D001 to D001.
Connected to D006. The sources of the memory cells are connected to the common source line S. By sharing the source lines S in this way, high integration of the memory cell array is realized.

FIG. 3 is a schematic sectional view of an embodiment of a memory cell in the flash memory according to the present invention. In the semiconductor substrate 503 in which the P-type impurity is introduced,
For example, a control gate 501 made of N-type impurity-doped polycrystalline silicon, for example, a control gate 502 made of N-type impurity-doped polycrystalline silicon.
Are stacked and formed with an interlayer insulating film 507 made of a silicon oxide film, a silicon nitride film or the like interposed therebetween. A thin tunnel insulating film 506 made of a silicon oxide film is formed between the semiconductor substrate 503 and the floating gate 502.

The source regions 509 of the two memory cells are formed in common and connected to the source line 504 formed of a polycrystalline silicon layer having an N-type impurity introduced. A drain region 508 is formed in the source region 509 with the floating gate 502 and the control gate 501 interposed therebetween. Although not particularly limited, impurities such as boron and arsenic are introduced into the drain region 508 in order to improve write characteristics, and N-type impurities such as phosphorus and arsenic are introduced into the source region to improve erase characteristics. The drain region 508 is connected to the data line 505 made of an aluminum-based metal material.

FIG. 4 is a schematic layout diagram of one embodiment of the memory cell in the flash memory according to the present invention. (A) shows the diffusion layers of the source and drain, the floating gate FG, the word line (control gate) SG and the source line TG, and (B).
Shows the data line. (A) and (B) are
The contact holes CONT are stacked so that they are in the same position. The word line formed of the second-layer polycrystalline silicon layer SG and the source line formed of the third-layer polycrystalline silicon layer TG are extended in the lateral direction so that they partially overlap each other. The floating gate is composed of the first-layer polycrystalline silicon layer FG.

FIGS. 5 to 7 are schematic flow charts for explaining an embodiment of the flash memory erasing method according to the present invention. FIG. 8 shows a distribution diagram of the threshold voltages of the memory cells corresponding thereto. Hereinafter, the erasing method according to the present invention will be described with reference to FIGS.

In FIG. 5, in step 701, an erase command designating an erase mode and an erase target address are input to the control circuit. The control circuit decodes the erase command and the address to be erased and executes step (1). In step (1), pre-write
Pre-verify is performed. That is, as shown in FIG. 8A, in the pre-erase (initial) state, a group of memory cells of logic “0” that are set to have a high threshold voltage Vth by the write operation and an erase state (logic). Since the memory cell group of "1" exists, the memory cell included in the erase unit is read and the threshold voltage is lowered, in other words, it is in the erased state (logic "1"). The memory cell group is changed to Step 7 in FIG.
If it is detected by the pre-verification of No. 02, the write operation is performed to such a memory cell in step 703.

In this operation, the first memory cell is
X address is set to the start address of the erase unit,
When the prewriting in steps 702 and 703 is executed for the address, the Y address is updated and the final Y address is repeatedly performed. The write operation is performed until the write operation is performed for a unit time and the result is read by pre-verification to reach a desired threshold voltage. When such write-back exceeds the predetermined number of times, the operation is terminated as an error that cannot be erased due to the number of times being exceeded. By such step (1), as shown in FIG. 8B, all the memory cell groups in the erase unit have the threshold voltage of the distribution corresponding to “0”.

In step (2) of FIG. 5, all the memory cells corresponding to the erase unit are collectively erased. In this erasing operation, erasing in an appropriate unit time and its erasing verification are repeatedly performed. That is, although omitted in the figure, the memory cells to be erased are read one by one after the erase operation in the unit time, and all the memory cells to be erased are in the erased state (“1”). The erase operation and the erase verify are repeatedly performed until it is determined to be.

The erase unit and its erase operation will be described with reference to the embodiment circuit shown in FIG. 2. When the erase operation is performed in units of a plurality of word lines like the erase object 401B, the memory cell to be erased is Connected word lines W004 to W0
A voltage of about −10 V with respect to 06 is supplied from the X decoder circuit 102. Word line W001 not to be erased
A voltage of about 2V is supplied from the X decoder circuit 102 to W003. A voltage of about 4 V is supplied to the source line S of the memory cell. In this way,
A high voltage such as 14 V is applied between the control gate and the source of the memory cell of the erase target 401B, a tunnel current flows from the floating gate to the source, and the charge accumulated in the floating gate is extracted to the source. On the other hand, since only a low voltage such as 2 V is applied between the control gate and the source for the memory cells that are not to be erased, the tunneling current as described above does not occur and the accumulated charge in the floating tink is not generated. It is maintained as it is.

As a result of the erase operation and erase verify in step (2) above, the distribution of the threshold voltages of all the memory cells to be erased is as shown in FIG. The distribution is such that the threshold voltage of the cell becomes the erase verify potential. At this time, in some memory cells, an overerased state 801 having a negative (−) threshold voltage may occur due to overerasure.

The presence of such a memory cell 801 having a negative threshold voltage causes the following problems. In the embodiment circuit of FIG. 2, when the memory cell 416 has a negative threshold voltage (depleted), even if the word line W006 connected to this has a non-selected state of 0 V, the drain of the memory cell 416 is ， Current will flow between the sources. For example, the memory cell 4 connected to the same data line D001 to which the memory cell 416 is connected.
Even if 11 is selected and the logic "0" held therein is read out, the logic "1" is output by the depletion. In this way, if there is even one depleted memory cell in the data line, reading of that data line becomes impossible.

The depleted cell has two generation modes. One mode is by accelerated erasing with moisture from outside the memory cell or due to the manufacturing process of the memory cell. This occurs because moisture penetrates into the source part of the memory cell to enhance the electric field of the source tunnel insulating film, and the threshold voltage after erasing has a relatively large negative voltage. , Appears as a drop bit as in 801 above.

On the other hand, another mode is caused by process process variations such as the film thickness of the tunnel insulating film, the source parasitic resistance, and the impurity profile of the source diffusion layer. This is a mode in which the threshold voltage becomes remarkable as the power supply voltage is lowered, and the threshold voltage after erasing does not become a negative voltage, but has a small threshold voltage around 0V. The device 802 having a small threshold voltage near 0 V is a potential depletion defect because a memory current may flow due to a temperature change or the like.

In this embodiment, the first deplete verify (first write-back operation) in step (3) shown in FIG. 6 is performed corresponding to the above two failure modes.
Then, the second deplete verify (second write-back operation) in step (4) shown in FIG. 7 is performed.

In FIG. 6, the Y address is set as the start address to be erased, and the X address is set as the start address. Then, in the deplete verify 704, the potential of the word line is set to 0 V, in other words,
The deplete verify potential (1) is set to 0 V, and a memory cell in which a memory current flows is searched for by having a negative threshold voltage, and write back 705 is performed. This write-back 705 is different from the pre-write in step (1) as described above. In other words, the memory cell erased to “1” is made to be the same as the original write like “0”. In order to prevent this, the potential of the word line is set to a low potential of about 4V instead of + 11V as in the normal write operation. At this time,
The data line to which the drain is connected is set to about 4.2V as in the normal write operation.

The write operation at this time is performed in units of data lines. That is, since it is not known in the deplete verify 704 which memory cell has the depletion defect, it is repeated until the memory cells of all X addresses have no depletion defect for one Y address, and then the Y address is updated. By repeating the same operation as described above, the depletion defect group 801 having a negative threshold voltage for all the memory cells to be erased is eliminated.

In FIG. 7, the Y address is set as the start address to be erased, and the X address is set as the start address. Then, in the deplete verify, in order to find the threshold voltage close to 0 V as described above,
In other words, by setting the potential of the word line to 1.2V,
The deplete verify potential (2) is set to 1.2 V, and a memory cell in which a memory current flows is searched for by having a small threshold voltage less than that, and the write back is performed. In this write-back, the word line (control gate) is set to 4 V as in step (3) described above.
It is performed with a low potential. At this time, the data line to which the drain is connected is set to about 4.2V as in the normal write operation.

The write-back operation at this time is performed in memory cell units. In other words, due to the deplete verify,
Since such a depletion defect is found, the process is repeated until the depletion defect disappears for each memory cell, and then X
By updating the address and repeating the same operation as described above and the Y address and repeating the same operation, the depletion failure group 802 having a small threshold voltage for all the memory cells to be erased is eliminated. As a result, it is possible to ensure the operation guarantee even when the reading temperature is different from the erasing temperature.

FIG. 9 shows the write back characteristic of the memory cell. In the write back operation in the present invention, the potential of the word line is calculated from the final memory cell threshold voltage and set to a low voltage of about 4V. In the depletion mode as described above, in the case of the threshold voltage of negative voltage, the electric field between the floating gate and the drain becomes large, and the write-back speed becomes faster accordingly. On the contrary,
For the normally erased cells connected to the same data line, the electric field between the floating gate and the drain is not relatively large, and the write-back speed becomes slow.

When the threshold voltage is relatively large, on the contrary, the threshold voltage decreases. This is shown in FIG.
As described above, in a memory cell having a relatively high threshold voltage, this is a phenomenon that hot hole injection occurs in the floating gate. In FIG. 10 (A),
For a memory cell having a negative threshold voltage, hot carriers generated near the drain are injected into the floating gate to change the threshold voltage in the positive direction.

As described above, as shown in the characteristic diagram of FIG. 9, the threshold voltage of the memory cell in the erase operation in step (2) has a large threshold voltage in the positive direction. When the voltage is lowered, the negative voltage and the low voltage are eliminated, the threshold voltage in the erased state is entirely within a small range, and the power supply is controlled by such highly accurate control of the erased state. The voltage Vcc can be applied to a low power supply voltage of about 3V.

The distribution of the threshold voltage of the memory cell which has been erased and rewritten by the steps (1) to (4) shown in FIGS. 5 to 7 is shown in FIG. 8D. As described above, it can be accommodated in a small range with high accuracy, and a wide temperature guarantee can be realized. Table 1 below shows an example of the operating voltage in each operation. In Table 1, ── indicates a floating state.

[0040]

[Table 1]

11 and 12 are schematic timing diagrams of an embodiment for explaining the outline of the erase operation according to the present invention. In the time axis of the figure, the erase and write-back portions are shown in a compressed form in order to represent the entire operation sequence. Further, in the figure, the entire erase sequence corresponding to the schematic flow charts of FIGS. 5 to 7 is conceptually shown, and is not faithfully corresponded to the actual erase sequence.

At the pre-write time of FIG. 11, memory cells are sequentially selected by the write verify activation signal,
For the memory cell in the erased state, the word line potential to be erased is raised and pre-writing is performed. The word lines and source lines that are not to be erased are left at 0V.

In the erase operation, an erase signal is generated, the potential of the word line to be erased is set to a negative voltage such as -10V, and the potential of the source line is set to a relatively high voltage such as + 4V. At this time, the potential of the non-erasing target word line is 2V.
The erase blocking potential is set to a certain level. That is, in the memory cell connected to the word line which is not erased, the tunnel current does not occur because the potential difference between the source and the control gate is only about 2V.

In the erase verify, the memory cell is read by the erase verify activation signal. At this time, if there is one having a higher threshold voltage due to the erase verify potential, the erase operation is repeated. The erase operation is repeatedly performed so that no memory cell has a higher threshold voltage due to the erase verify potential in all memory cells. In the same drawing, one erase operation and erase verify are shown as an example.

Then, as shown in FIG. 12, deplete verify (1) and write back operation are performed. In this deplete verify (1), the word line is set to 0V.
The write back word line potential is implemented by a low voltage of about + 4V as described above. Deprecated Blythe (1)
When is completed, the deplete verify (2) and the write back operation are performed. In this deplete verify (2), the word line is set to a low voltage of about 1 V as described above, but it is omitted in the figure.

In the erasing method of the above embodiment, the prewrite operation of step (1) can be omitted. In other words, if step (1) is omitted and the erase operation is performed in step (2), the memory cell in the logic "1" state is inevitably over-erased. That is, when the erase operation as described above is performed on the memory cell of logic "1",
It has a negative threshold voltage. However, in the erase method and the automatic erase circuit according to the present invention,
In step (3), a memory cell having a negative threshold voltage due to over-erasing as described above is searched for by depletion verify (1), and the write-back is performed, so there is virtually no need to do so. It doesn't matter.

FIG. 13 is a flow chart for explaining the suspend function according to the present invention.
Shows the timing diagram. The suspend (erase suspend) function was introduced to improve usability in response to the fact that the erase time of the flash memory is much longer than the read time, so the erase operation is suspended. Then, the read operation is performed.

That is, as shown in the timing chart of FIG. 13, at the timing 1301 at which the write enable signal / WE changes from the low level to the high level, the input / output terminal I
The command is fetched from / O, and when it is an erase command, the erase address is fetched at the timing 1302 when the signal / WE changes from the high level to the low level. In the case of designating the erase area, this address fetching operation is performed again to fetch the erase start address and the erase end address.
In this way, the erase operation is started.

During the erase operation, if an erase suspend command is input from the input / output terminal I / O at the timing 1303 when the signal / WE is changed from the low level to the high level, the erase operation is suspended, and if necessary. Read operation is performed. Then, in the same manner as above, the signal / W
When the erase restart command is input at timing 1304 when E is changed from the low level to the high level, the interrupted erase operation is continuously performed.

When the erase suspend operation is instructed in this way,
In the flash memory of this embodiment, as shown in the flowchart of FIG. 13, when the suspend command is input during the execution of the step (1) consisting of the prewrite and preverify, there is a possibility of depletion failure. Since there is no such address, the program is interrupted when the programming or programming verification for the address at that point is completed.

If a suspend command is input during the erase and erase verify operations in step (2), it is possible that a memory cell with a depletion defect has occurred as described above. Absent. Until the completion of the deplete verify (1), in other words, until the step (3) is completed, the erasing operation is prioritized, and after waiting for the end of the operation, in other words, until the depletion failure is resolved. A series of erase operations is interrupted. Then, if a suspend command is input during the step (4), there is no possibility of depletion failure, and therefore, the write-back of the address at that time or the interruption at the end of deplete verify (2).

When the step (1) is omitted as described above, if a suspend command is input during the erase and erase verify corresponding to the step (2), the memory cell having the depletion defect as described above is detected. It has happened, so there is no interruption at that point. In other words, until the above-mentioned deplete verify (1) is completed, in other words, the erase operation is prioritized until the first write-back operation corresponding to the above step (3) is completed, and the erase operation is waited until the erase is completed. Operation interruption is allowed.

FIG. 15 shows the flash (F
A schematic block diagram of one embodiment of a microcomputer or the like using a LASH) memory is shown. The figure mainly shows the flow of the erase interruption signal from the microprocessor CPU. An erase operation is started in the flash memory by inputting an address or a command from the central processing unit or the microprocessor CPU, but an erase suspending instruction may be input for the reason as described above. In the flash memory of this embodiment, when an erase suspend command is input through the input buffer (Data input Buffer) circuit during the erase operation, the command decoder (Command D
command is read by the circuit,
A control signal is supplied to the automatic control circuit (Auto Control). In the automatic control circuit, the erase operation is interrupted by the sequence shown in FIG.

FIG. 16 is a schematic block diagram of an embodiment of the flash memory according to the present invention. Each circuit block in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

Reference numeral 1 is an address buffer, which also has an address latch function. An address change detection circuit 2 generates a one-shot pulse when a change in the address signal is detected. This pulse is used for equalizing the potential of the bit line in order to speed up the read operation, although not particularly limited.

An X decoder 3 selects a word line of the memory mat (memory cell array) 5. In the flash memory, the potential of the word line is set to various potentials as described above according to the operation mode. That is, a high voltage such as + 11V is applied during the write operation, and a negative voltage such as -10V is applied during the erase operation. Then, as shown in Table 1, the potential is set according to the write or erase verify, the write back operation, or the like, and is set to the voltage corresponding to the power supply voltage Vcc during the read operation. Therefore, a word driver 12 having a voltage switching function, which will be described later, is provided on the input side of the X decoder 3.

Reference numeral 4 is a Y decoder, which forms a selection signal for the bit line of the memory mat 5. The switch control of the Y gate circuit 6 is performed by the selection signal of the bit line. Y
The gate circuit 6 receives the memory mat 5 in response to the selection signal.
, And the sense amplifier 9 or write latch 8 are connected.

As shown in FIG. 2, the memory mat 5 is constructed by arranging memory cells in a matrix at intersections of word lines and bit lines. That is, the word line is connected to the control gate, the drain is connected to the bit line, and the source is connected to the source line. A floating gate is provided under the control gate,
Electrons are injected into this floating gate to perform writing, and such electrons are extracted to the source side to perform an erase operation.

The write latch 8 has an external terminal I / O.
The write signal input from i is the data input buffer 1
Input through 1. The output signal of the sense amplifier 9 is
On the other hand, it is output to the external terminal I / Oi through the data output buffer 10. The output signal of the sense amplifier 9 is also transmitted to the automatic control circuit 15 for the verify operation.

The control buffer 13 has a chip enable signal / CE and an output enable signal / OE.
The operation mode is determined by. Command decoder 1
As described above, reference numeral 4 decodes the input command and supplies a write control signal or an erase control signal to the automatic control circuit 15 to perform an erase operation corresponding to the erase method shown in FIGS. 5 to 7. Alternatively, the sequence control necessary for the write operation is performed. The automatic control circuit 15 includes an address counter as described later, generates an address signal for write verify or erase verify, and inputs the address signal to the X decoder 3 and the Y decoder 4 through the address buffer 1. To form. Driver 1
2 switches a plurality of types of voltages applied to the word line and supplies the voltage to the X decoder. In practice, the driver 12 selectively drives one word line from the plurality of types of voltages as described above, according to the output of the X decoder and the operation mode signal.

The status register 16 stores internal states such as an operation mode and an operation sequence, and is read out from the data output buffer as needed. That is, the host system such as a microcomputer grasps the internal state of the flash memory by data polling or the like and controls it. That is,
During an erase operation requiring a long time of about 10 ms, when a microcomputer or the like issues an erase command and an address to the flash memory, the flash memory is immediately disconnected from the bus and another peripheral device is connected to the bus. Then, other data processing is started during the above-mentioned erasing time. Then, the end of erasing can be detected by the above-mentioned polling, and the operation such as writing can be started.

The voltage detection circuit 18 detects the power supply voltage Vcc and the high voltage Vpp. In particular, the write high voltage Vpp is used for the detection because a high voltage such as 11 V needs to be supplied only during the write or erase operation. The voltage generation circuit 17 has a voltage for verifying as described above,
In addition to erase verify and deplete verify (2), an erase blocking voltage and an erase negative voltage are generated. With the automatic control circuit provided inside as in this embodiment,
Since a series of erasing operations can be executed, a convenient flash memory can be obtained.

FIG. 17 shows a schematic block diagram of an embodiment of the automatic control circuit. An address generation circuit 1505 generates an address signal for write verify, erase verify or deplete verify. Reference numeral 1503 is a counter, which is used to count the number N of times of write back as described above. 1501
Is a multi-sector control circuit, which is used to control block erasing over a plurality of word lines. 150
Reference numeral 2 is an automatic erase control circuit, which controls a series of erase operations. A block prewrite circuit 1503 performs a prewrite operation of an erase operation across a plurality of word lines. Reference numeral 1504 denotes a sector prewrite circuit, which performs a prewrite operation in word line units. Reference numeral 1509 denotes a write and erase pulse generation circuit. 1507 is a wait time control circuit. 1506 is a verify control circuit. Reference numeral 1510 is a write control circuit. Reference numeral 1511 is a write-back control circuit.

FIG. 18 shows a specific circuit diagram of an embodiment of a partial selection circuit of the memory mat in the flash memory according to the present invention. In the figure, a part of a word line selection circuit and a bit line selection circuit are shown. The word driver shown in the same figure is composed of a changeover switch circuit, and outputs a negative voltage formed by a negative voltage generating circuit, Vpp or Vcc selectively supplied through a power supply switching circuit, and a bias voltage supplied from a bias voltage terminal to a word line. Tell.

For such switch control of the word driver, an X decoder divided into two stages is provided,
In one of the X decoders, selection / non-selection is switched by a signal generated by the erase control circuit.
That is, in the write or read operation, the selected one is at the high level and the non-selected one is at the low level, while in the erase operation, the selected one becomes the low level like a negative voltage and the unselected one is erased. Since it becomes the high level corresponding to the blocking, the X decoder also sets it to the opposite level and notifies the word driver.

The source bias circuit supplies a relatively high voltage such as 4V to the source line in response to the erase signal, and grounds the circuit during a period other than the erase operation, in other words, writing and reading (including verify). Supply electric potential. A level conversion circuit is provided at the output of the Y decoder. A write high voltage Vpp is selectively supplied to the level conversion circuit by a voltage switching circuit controlled by a write signal and a write back signal. That is, in the write operation and the write-back operation, in order to supply a high voltage to the bit line, such as 4V, with respect to the power supply voltage Vcc (3.3V) as described above, the V formed by the Y decoder is used.
The high level corresponding to cc is supplied to the gate of the switch MOSFET forming the Y gate as a high voltage corresponding to Vpp to perform switch control. As a result, there is no level loss due to the threshold voltage in the switch MOSFET,
A high voltage such as 4V formed by the write load circuit described below can be supplied to the bit line.

In the figure, P-channel type MOSFE
The T is distinguished from the N-channel MOSFET by adding an arrow to its gate. And MOSF
The MOSFET in which an L-shaped line is added to the drain to which the high voltage of ET is supplied indicates that the MOSFET has a high breakdown voltage. The same applies to the following circuit diagrams.

FIG. 19 shows a concrete circuit diagram of an embodiment of another partial selection circuit of the memory mat in the flash memory according to the present invention. In the figure, the bit line selection circuit is mainly shown. Therefore, a part of the bit line selection circuit is shown redundantly with that of FIG. That is, the Y gate circuit, which is a bit line selection circuit, is divided into two stages. One Y-decoder divided into two is supplied to the gate of the switch MOSFET whose one end is connected to the bit line through the level conversion circuit as described above. A switch MO composed of a plurality of these
A switch MOSFET whose switch is controlled by the other Y decoder is provided corresponding to the SFET. Since these second-stage switch MOSFETs are used only for reading, the selection signal of the corresponding Y decoder is supplied as they are. These switch mosfets
Connects the signal of the selected bit line to the input terminal of the sense amplifier SA. The output signal of the sense amplifier SA is
It is supplied to the output buffer and the read determination circuit used in the verify operation.

The write control circuit includes a write latch circuit, and writing (page write) can be performed in units of a plurality of bit lines. That is, data for a plurality of bit lines is stored in the write latch circuit, and the switch MOSF is set by the write signal and the write back signal.
The ET is controlled to transmit the write high voltage to the bit line. During the write operation and write-back operation in units of one bit line, only one of the write load circuits corresponding to the plurality of bit lines is activated.

FIG. 20 is a circuit diagram of an embodiment of the voltage switching circuit in the flash memory according to the present invention. That is, the power supply voltage Vcc and the write high voltage Vpp are input, and in accordance with the write signal and the erase signal,
Any of Vpp, Vcc, write verify voltage, write back voltage, and deplete verify (2) voltage is output as the X-triver potential. The write verify voltage is a switch MOS that transmits the threshold voltage of the memory cell to detect that the threshold voltage is set to Vcc or higher.
The control signal of the FET is level-shifted to the high voltage corresponding to the high voltage Vpp. Thus, the switch control signal transmitted to the gate of the switch MOSFET that outputs a voltage higher than the power supply voltage Vcc such as 3.3 V is output via the level conversion circuit. The level conversion circuit includes a P-channel type MOSFET in which a gate and a drain are cross-connected, and such a P-channel type MOSFET.
It is composed of an N-channel MOSFET which is provided between the drain of T and the ground potential of the circuit and whose gates are supplied with input signals of opposite phases.

FIG. 21 shows a circuit diagram of an embodiment of the negative voltage generating circuit. The negative voltage generation circuit supplies a clock pulse to the level conversion circuit through the gate circuit controlled by the erase signal to convert the clock pulse to the Vpp level, and the charge pump circuit driven by the clock pulse generates a negative voltage. Such a negative voltage is a constant voltage set by the Zener diode based on the erase potential. That is, for the erase voltage, the MOS whose gate is supplied with it
The added voltage of the threshold voltage of the FET and the Zener voltage is transmitted to the X driver as an erase voltage. The drain of the MOSFET whose gate is supplied with the erase voltage is connected to the high voltage Vpp through a P-channel MOSFET. The P-channel MOSFET is switch-controlled by the output signal of the level conversion circuit that receives the erase signal, and is turned off at any time other than the erase operation.

Further, a level conversion circuit using the negative voltage as an operating voltage is provided, and an N channel type MOS provided between the negative voltage output and the ground potential of the circuit during the erase operation.
The FET is turned off, and when the erase operation is completed, it is turned on to reset the negative voltage to the ground potential of the circuit.

In the microcomputer system using the flash memory of this embodiment as shown in FIG. 15, since the flash memory has the automatic erasing function as described above, the microprocessor CPU has such a problem. Generates a signal and command to specify the erase mode by specifying the erase address of the flash memory. After this, the flash memory enters the automatic erase mode internally as described above. When the flash memory enters the erase mode, the address terminals, data terminals and all control terminals become free as described above, and the microprocessor C
The flash memory is electrically separated from the PU. Therefore, the microprocessor CPU simply instructs the erase mode to the flash memory, and thereafter uses the system bus to read other memory device ROM.
It is possible to execute data processing involving the exchange of information with the RAM, the RAM, or the input / output port.

As a result, the flash memory can be erased in the state where it is mounted in the system as in the case of the full-function (byte rewritable) memory without sacrificing the system throughput. After instructing the erase mode as described above, the microprocessor CPU specifies the data polling mode for the flash memory at an appropriate time interval, reads the status register, and when the erase is completed, the flash memory If there is data to be written in, the write is instructed. Then, if necessary, the erase suspending command can be issued to read necessary memory cells.

The operational effects obtained from the above embodiment are as follows. That is, (1) in the erase mode of the memory cell in which the charge accumulated in the floating gate by the write operation is discharged to the source side to perform the erase, the memory cell in the erase unit is read and the charge is accumulated in the floating gate. A pre-write operation that performs a write operation and a write determination operation on a memory cell that has not been erased; an erase operation that collectively performs an erase operation and an erase determination operation on the memory cells in the erase unit based on an erase reference voltage; For the erase unit, a data line in which a memory cell overerased to a negative threshold voltage exists is detected, and the memory cell provided in the data line is made smaller in absolute value than the above write operation. The first write-back operation for writing at a potential and the erase unit is smaller than the desired erase state. By providing an automatic erase circuit that detects a memory cell that is over-erased to a different threshold voltage and sequentially performs a second write-back operation that performs a write operation at the same potential as the first write-back operation, In the first write-back operation, the over-erased (depleted) memory cell that is the cause of unreadable data is eliminated, and the second write-back operation compresses the variation in the threshold voltage in the erased state, which is wide. The temperature guarantee range can be secured, and the erase suspension can be prohibited only during the period from the start of the erase operation to the completion of the first write-back. Therefore, the erase suspend function can be realized in other cases. can get.

(2) Due to the above (1), the operating voltage of the flash memory can be lowered by about 3V.

(3) By setting the operation modes including the erasing mode by the command, it is possible to obtain an effect that many kinds of operation modes can be realized with a small number of terminals.

(4) Relatively long by adding the function of judging the completion of the prewrite operation, the first write-back operation or the second write-back operation and interrupting the series of erase operations. Since the memory access can be performed during the erase operation performed over time, there is an effect that the usability can be improved.

(5) In the erase operation of the memory cell in which the charge accumulated in the floating gate by the write operation is discharged to the source side to perform the erase, the memory cell in the erase unit is read and the charge is accumulated in the floating gate. The pre-write operation including the write operation and the write determination operation is performed on the memory cells that are not erased, and the erase operation including the erase operation and the erase determination operation is collectively performed on the memory cells in the erase unit under the erase reference voltage. And detecting a data line in which a memory cell overerased to a negative threshold voltage for the erase unit exists,
The memory cell provided on the data line is subjected to the first write-back operation, which is a write operation at a potential that is made smaller in absolute value than the write operation, and the erase unit is set to a desired erase state. In comparison with the first write-back operation, a memory cell that is over-erased to a threshold voltage smaller than that of the first write-back operation is detected, and a second write-back operation including a write operation is performed at the same potential as the first write-back operation. Over-erasure (depletion) that causes unreadable in operation
The erased memory cell is eliminated, and the variation of the threshold voltage in the erased state is compressed by the second write-back operation, so that a wide temperature guarantee range can be secured and the first erased operation can be performed. Since it is necessary to prohibit the erase interruption only while the write-back is completed, the effect that the erase suspend function other than that can be realized can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the above-described series of erasing methods is necessary for the above-described erasing operation directly from a control circuit provided outside the flash memory or a microcomputer in addition to those performed by an automatic control circuit built in the flash memory. Alternatively, the control signal or address may be input.

The write operation of the flash memory may be performed by using hot electrons as described above or by injecting electrons into the floating gate by a tunnel current. A specific circuit for implementing the above-described erase sequence can take various embodiments. The present invention can be widely used for a flash memory and its erasing method.

[0082]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in the erase mode of the memory cell in which the charge accumulated in the floating gate is released to the source side by the write operation to erase, the memory cell in the erase unit is read and the memory in which the charge is not accumulated in the floating gate is read. Regarding a pre-write operation that performs a write operation and a write determination operation on a cell, an erase operation that collectively performs an erase operation and an erase determination operation on a memory cell in the above erase unit under an erase reference voltage, and the above erase unit A data line in which a memory cell over-erased to a negative threshold voltage exists is detected, and the memory cell provided in the data line is detected with a potential that is made smaller in absolute value with respect to the write operation. A first write-back operation for writing and a threshold smaller than the desired erase state for the erase unit By providing an automatic erasing circuit that detects a memory cell that has been over-erased to a value voltage and sequentially performs a second write-back operation that performs a write operation at the same potential as the first write-back operation described above, The overwriting (depletion) of memory cells, which is the cause of unreadable in the write-back operation, is eliminated, and the variation of the threshold voltage in the erased state is compressed by the second write-back operation. The range can be secured, and the erase suspension can be prohibited only during the period from the start of the erase operation to the completion of the first write-back, so that the erase suspend function in other cases can be realized.

As described above, the operating voltage of the flash memory can be lowered to about 3V.

By setting the operation modes including the erase mode by the command, various kinds of operation modes can be realized with a small number of terminals.

By adding the function of judging the completion of the pre-write operation, the first write-back operation, or the second write-back operation and interrupting the series of erase operations, it is possible to perform the operation for a relatively long time. Since the memory access can be performed during the erase operation, the usability can be improved.

In the erase operation of the memory cell in which the charge accumulated in the floating gate by the write operation is discharged to the source side to erase, the memory cell in the erase unit is read and the charge is not accumulated in the floating gate. A pre-write operation including a write operation and a write determination operation is performed on the memory cells, and an erase operation including an erase operation and an erase determination operation is collectively performed on the memory cells in the erase unit described above based on an erase reference voltage to perform an erase operation. A data line in which a memory cell overerased to a negative threshold voltage per unit is present is detected, and the memory cell provided on the data line is reduced in absolute value with respect to the write operation. The first write-back operation consisting of the write operation in In comparison with the first write-back operation, a memory cell that is over-erased to a threshold voltage smaller than that of the first write-back operation is detected, and a second write-back operation including a write operation is performed at the same potential as the first write-back operation. Since the overerased memory cell which is the cause of unreadable in the operation is eliminated and the variation of the threshold voltage in the erased state is compressed by the second write-back operation, a wide temperature guarantee range can be secured. In addition, since it is necessary to prohibit the erase interruption only during the period from the start of the erase operation to the completion of the first write-back, it is possible to realize the erase suspend function in other cases.

[Brief description of drawings]

FIG. 1 is an overall block diagram showing an embodiment of a flash memory according to the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the memory cell array of FIG.

FIG. 3 is a schematic cross-sectional view showing one embodiment of a memory cell in the flash memory according to the present invention.

FIG. 4 is a schematic layout diagram showing one embodiment of a memory cell in the flash memory according to the present invention.

FIG. 5 is a partial schematic flowchart for explaining an embodiment of a flash memory erasing method according to the present invention.

FIG. 6 is a schematic flowchart of another part of the embodiment of the erasing method of the flash memory according to the present invention.

FIG. 7 is a schematic flowchart of the remaining part for explaining one embodiment of the flash memory erasing method according to the present invention.

FIG. 8 is a distribution diagram of threshold voltages of memory cells corresponding to the flash memory erasing method according to the present invention.

FIG. 9 is a write-back characteristic diagram of a memory cell by the erase method according to the present invention.

FIG. 10 is a principle diagram for explaining an erase operation of a memory cell by an erase method according to the present invention.

FIG. 11 is a partial schematic timing diagram showing an embodiment for explaining the outline of the erase operation according to the present invention.

FIG. 12 is a schematic timing chart of the remaining part showing one embodiment for explaining the outline of the erase operation according to the present invention.

FIG. 13 is a flow chart diagram for explaining a suspend function according to the present invention.

FIG. 14 is a timing chart for explaining the suspend function of the present invention.

FIG. 15 is a schematic block diagram showing an embodiment of a microcomputer or the like using the flash memory according to the present invention.

FIG. 16 is a block diagram showing an embodiment of a memory mat and its peripheral circuit in the flash memory according to the present invention.

FIG. 17 is a block diagram showing an embodiment of an automatic erasing circuit according to the present invention.

FIG. 18 is a specific circuit diagram showing an embodiment of a partial selection circuit of the memory mat in the flash memory according to the present invention.

FIG. 19 is a specific circuit diagram showing an embodiment of another partial selection circuit of the memory mat in the flash memory according to the present invention.

FIG. 20 is a circuit diagram showing an embodiment of a voltage switching circuit in the flash memory according to the present invention.

FIG. 21 is a circuit diagram showing an embodiment of a negative voltage generating circuit in the flash memory according to the present invention.

FIG. 22 is a circuit diagram showing an example of a memory cell array of a conventional flash memory.

FIG. 23 is a distribution diagram of threshold voltages of memory cells for explaining an erase method in a conventional flash memory.

[Explanation of symbols]

101 ... Memory cell array, 102 ... X decoder, 10
3 ... Y decoder, 104 ... Control circuit, D001-D00
6 ... Data line, W001 to W006 ... Word line, S ... Source line, 501 ... Control gate, 502 ... Floating gate, 503 ... Semiconductor substrate, 504 ... Source line, 505 ... Data line, 506 ... Tunnel insulating film, 50
7 ... Interlayer insulating film, 508 ... Drain region, 509 ... Source region, CPU ... Microprocessor (central processing unit), 1 ... Address buffer, 2 ... Address signal change detection circuit, 3 ... X decoder, 4 ... Y decoder, 5 ... memory mat, 6 ... Y gate circuit, 7 ... source MOSFET,
8 ... Write latch, 9 ... Sense amplifier, 10 ... Data output buffer, 11 ... Data input buffer, 12 ... Driver, 13 ... Control buffer, 14 ... Command decoder, 15 ... Automatic control circuit, 16 ... Status register, 17 ... Voltage Generation circuit, 18 ... Voltage detection circuit, 150
1 ... Multi-sector control circuit, 1502 ... Automatic erase control circuit, 1503 ... Block prewrite circuit, 1504 ... Sector prewrite circuit, 1505 ... Address generation circuit, 1506 ... Verify control circuit, 1507 ... Wait time control circuit, 15
08 ... Counter, 1509 ... Write / erase pulse generation circuit, 1510 ... Write control circuit, 1511
… Write-back control circuit.

Front page continuation (72) Masato Takahashi, 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Semiconductor Company, Hitachi, Ltd. (72) Inventor, Takeshi Furuno 5--20, Kamimizuhoncho, Kodaira, Tokyo No. 1 Incorporated company, Hitachi, Ltd. Semiconductor Division (72) Inventor Masashi Wada 5-201-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Hirate RLS Engineering Co., Ltd. (72) Inventor Kenji Kosakai 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Within Hitachi, Ltd. Semiconductor Business Division (72) Inventor Hideaki Kameyama 5-22-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd.

Claims (7)

[Claims] 1. A memory array comprising a control gate and a floating gate, wherein memory cells arranged in a matrix are arranged so that charges accumulated in the floating gate by a write operation are discharged to a source side for erasing. An address selection circuit for selecting a memory cell in the memory array and a write operation and a write determination operation for a memory cell in which the memory cell in the erase unit is read out in the erase mode and electric charge is not accumulated in the floating gate. The pre-write operation is performed, the erase operation is performed collectively on the memory cells in the erase unit based on the erase reference voltage, and the erase determination operation is performed collectively, and the erase unit is over-erased to a negative threshold voltage. The data line where the memory cell exists is detected and the data line provided A first write-back operation of writing to the memory cell at a potential that is made smaller in absolute value than the write operation, and a threshold voltage smaller than the desired erase state in the erase unit are exceeded. Batch erasing characterized by comprising an automatic erasing circuit for detecting erased memory cells and sequentially performing a second write-back operation for performing a write operation at the same potential as the first write-back operation Type non-volatile storage device. 2. A memory array, comprising a control gate and a floating gate, in which memory cells arranged in a matrix are arranged so that the electric charge accumulated in the floating gate by a write operation is discharged to the source side for erasing. An address selection circuit that performs a memory cell selection operation of the memory array, an erase operation that collectively performs an erase operation and an erase determination operation based on an erase reference voltage for memory cells in an erase unit, and a negative erase operation for the erase unit. A data line in which a memory cell over-erased to a threshold voltage exists is detected, and the memory cell provided in the data line is written at a potential that is made smaller in absolute value than the above write operation. First write-back operation and over-erasing to a smaller threshold voltage than the desired erased state for the erased unit Batch erasing characterized by comprising an automatic erasing circuit for detecting the removed memory cells and sequentially performing a second write-back operation for performing a write operation at the same potential as the first write-back operation Type non-volatile storage device. 3. The collective erasure type nonvolatile memory according to claim 1, wherein the setting of the operation mode including the erase mode is determined by a command decoder which receives a command supplied from the outside. Sex memory device. 4. The detection of the over-erased memory cell in the second write-back operation is performed by determining the potential of the word line by turning on the memory cell with respect to a relatively small voltage corresponding thereto. A batch erasing type non-volatile memory device according to claim 1 or 2, wherein 5. A function for determining whether the pre-write operation, the first write-back operation or the second write-back operation is completed and suspending the series of erase operations is added. 3. The batch erasing type non-volatile memory device according to claim 1. 6. A batch erasing type non-volatile memory device comprising a memory cell for erasing by discharging charges accumulated in a floating gate to a source side by a writing operation, in which a memory cell in an erasing unit is erased in an erasing mode. A pre-write operation is performed to perform a write operation and a write determination operation on a memory cell that has been read out and has no charges accumulated in the floating gate. An erase determination operation is performed, a data line in which a memory cell overerased to a negative threshold voltage exists in the erase unit is detected, and the memory cell provided in the data line is subjected to the write operation. The first write-back operation is performed by the potential that is made smaller in absolute value, and the desired erase state is obtained for the erase unit. A memory cell that has been over-erased to a threshold voltage smaller than that of the above-mentioned memory cell is detected, and a second write-back operation is performed at the same potential as the first write-back operation described above. Method of erasing non-volatile memory device. 7. A collective erase type non-volatile memory device comprising a memory cell for erasing by discharging electric charges accumulated in a floating gate to a source side by a write operation, in the erase unit memory cell. The erase operation and the erase determination operation are collectively performed on and, the data line in which the memory cell over-erased to the negative threshold voltage exists in the erase unit is detected, and the memory cell provided in the data line is detected. On the other hand, the first write-back operation is performed by the potential that is made smaller in absolute value with respect to the write operation, and the memory cell that is over-erased to a threshold voltage smaller than the desired erased state is erased for the erase unit. A batch erasing non-volatile memory device, which is configured to detect and perform a second write-back operation at the same potential as the first write-back operation. How to erase.