JP3945652B2 - Nonvolatile memory device - Google Patents

Description

  The present invention relates to a non-volatile storage device (hereinafter simply referred to as a flash memory) and a technique effective when used for an erasing method thereof.

  A flash memory has hot electrons generated in the vicinity of a drain by setting a drain potential of a nonvolatile memory element (hereinafter simply referred to as a memory cell) to about 4 V and a word line connected to a control gate to about 11 V in a write operation. Is injected into the floating gate to bring the threshold voltage to a high state (logic “0”). In the erasing operation, the source potential is set to about 4 V, the word line is set to about -11 V, a tunnel current is generated, the charge accumulated in the floating gate is drawn, and the threshold voltage is lowered (logic “1”). To do.

As shown in FIG. 14, in the initial state before erasure, there are a memory cell group corresponding to “1” and a memory cell group corresponding to “0” as described above. Select 1 ”memory cell and perform write operation (pre-write) and read operation (pre-verify) to set all memory cells to“ 0 ”state, then erase and read operation (erase verify) ) I do. At this time, an overerased state (depletion failure) occurs due to variations in threshold voltage due to batch erase due to process variations such as tunnel oxide film thickness and impurity profile, and influence of parasitic resistance of internal potential. If there is even one memory cell having such a negative threshold voltage, even if the word line to which the memory cell is connected is in a non-selected state, a current flows through the memory cell, making it impossible to read. Various proposals have been made to detect the over-erased memory cells and perform write back to prevent the depletion failure. Regarding countermeasures against such depletion defects, there are JP-A-4-6698, JP-A-4-222994, and JP-A-5-89688.
Japanese Patent Laid-Open No. 4-6698 JP-A-4-222994 Japanese Patent Laid-Open No. 5-89688

  In any of the above erasing methods, measures against depletion failure are taken by rewriting. However, once a depletion failure occurs in a memory cell, there is a problem in that the write / erase characteristics and the information retention characteristics are deteriorated, resulting in an adverse effect that the number of rewritable times is reduced. In addition, a reduction in power supply voltage of about 3 V is also being studied for flash memories, and the threshold voltage due to the erase operation has to be lowered along with such a reduction in voltage. This increases the possibility of the occurrence of the flash memory, and becomes a major obstacle to the low-voltage operation of the flash memory.

  An object of the present invention is to provide a nonvolatile memory device that realizes a highly accurate erase operation in a single time and an erase method thereof. Another object of the present invention is to provide a batch erasing nonvolatile memory device that realizes a stable operation at a low voltage and an erasing method thereof. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, in a batch erase type nonvolatile memory device having a memory cell in which charges accumulated in a floating gate by a write operation are released to the source side to perform erase, erase in the batch erase operation of such a nonvolatile memory element A first operation of reading a unit memory cell and performing pre-write on a nonvolatile element in which no charge is accumulated in the floating gate; A second operation for performing an erasing operation at a high speed under a relatively large erasing reference voltage, and a writing operation with respect to the erasable all nonvolatile elements read to a relatively low threshold voltage. The third operation to be performed and the non-volatile memory element in the erase unit are collectively relatively small by relatively small energy. Providing a fourth auto-erase circuit that performs operations sequentially in the erasing operation in the low speed to the original erase reference voltage.

  The outline of other representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, as an erasing method of a batch erasing type nonvolatile memory device having a nonvolatile element that performs erasing by discharging the charge accumulated in the floating gate by the writing operation to the source side, the memory cell of the erasing unit is read and the floating gate A first operation of performing pre-write on a nonvolatile element in which no charge is stored, and a relatively large erase reference voltage based on relatively large energy collectively for the nonvolatile elements in the erase unit. A second operation for performing an erase operation at a high speed, a third operation for performing a write operation on all the nonvolatile elements that have been erased and having a relatively low threshold voltage, and the erase operation First, the erase operation is performed at a low speed on the basis of a relatively small erase reference voltage with relatively small energy for the unit nonvolatile memory element. It performs the operation and sequentially.

  The threshold voltage in the erased state can be set with high accuracy up to a low voltage while preventing overerasing.

  FIG. 1 is a schematic flowchart for explaining one embodiment of a flash memory erasing method according to the present invention. FIG. 2 shows a distribution diagram of the threshold voltage of the corresponding memory cell. Hereinafter, the erasing method according to the present invention will be described with reference to FIGS.

  In FIG. 1, when the erase mode is started, prewrite and preverify are performed in steps (1) and (2). That is, as shown in FIG. 2A, in a state before (initial) erasing, a memory cell group of logic “0” that has a high threshold voltage Vth by a write operation and an erased state (logic Since there is a memory cell group of “1”), the memory cell included in the erase unit is read and the threshold voltage is lowered, in other words, in the erased state (logic “1”). When a memory cell group is detected by the pre-verify in step (2) in FIG. 1, a write operation is performed on the memory cell in step (1).

  In this embodiment, the pre-verification is performed unconditionally in step (1), but in practice, the memory cell at the head address passes through step (1) and step (2). If the final address is not the final address of the erase unit, the process returns to step (1), and if the erase state is in accordance with the result of the pre-verify, the pre-write is performed, and if it is in the write state, Pre-verification is performed. If (1) pre-write corresponding to (2) pre-verify is performed on all memory cells in the erase unit, the process proceeds to the next step (3). By completing the pre-verification as described above, as shown in FIG. 2B, all memory cell groups in the erase unit have a threshold voltage having a distribution corresponding to “0”.

  In step (3) in FIG. 1, all the memory cells corresponding to the erase unit are collectively erased. In this erasing operation, erasing is performed in a short time with relatively large energy. That is, the source potential is set to a relatively high voltage of about 4V, the word line connected to the control gate is set to a high voltage such as -11V, and the floating gate is switched to the source in an erasing time corresponding to a relatively short pulse width. A tunnel current is generated toward the surface to extract charges.

  In step (4) of FIG. 1, the first erase verify is performed. At this time, the set voltage EV1 corresponding to a relatively high voltage is used, and if at least one threshold voltage is higher than that, the process returns to step (3), and the erase operation is performed in the unit time. By repeating such an operation, as shown in FIG. 2C, the threshold voltages of all the memory cell groups in the erase unit are made to fall within a distribution lower than the relatively high set voltage EV1.

  In step (4) and step (5) in FIG. 1, similarly to the above-described pre-write and pre-verify, a write operation is performed by selecting a memory cell lower than the relatively low set potential WV1. That is, in this step (4) and step (5), the memory cell that is likely to be over-erased is detected by the second erase operation to be performed next, and the threshold value is obtained by performing the write back. The value voltage is increased. In the writing in this step (5), unlike the normal writing operation, the memory cell having the set voltage WV1 or lower is subjected to a write operation shallow enough not to exceed the erase voltage EV1. As a result, as shown in FIG. 2D, the threshold voltage distribution of the memory cell group in the erase unit can be set in a relatively narrow range lower than the erase voltage EV1 and higher than the set voltage WV1. .

  In step (7) in FIG. 1, all the memory cells corresponding to the erase unit are collectively erased. In this erasing operation, erasing is performed over a relatively long time with relatively small energy. That is, the source potential is set to a relatively low voltage of about 3V, the word line connected to the control gate is set to a high voltage such as -11V, and a tunnel current is generated from the floating gate to the source in a unit erase time. The charge is extracted.

  In step (8) of FIG. 1, the second erase verify is performed. At this time, the set voltage EV2 corresponding to a relatively low voltage is used, and if at least one threshold voltage is higher than that, the process returns to step (7) and the erase operation is performed in the unit time. By repeating such an operation, as shown in FIG. 2E, the threshold voltages of all the memory cell groups in the erase unit are made to fall within a distribution lower than the relatively high set voltage EV2.

  FIG. 4 is a schematic cross-sectional view of the memory cell. In a write operation, a high voltage such as 11 V is supplied to the control gate G connected to the word line, a voltage such as 4 V is applied to the drain D connected to the bit line, and the source connected to the source line A voltage such as 0V is applied to S. As a result, the memory cell is turned on, and hot electrons generated near the drain pass through the thin gate insulating film and are injected into the floating gate FG.

  In the erase operation, a negative voltage such as -11 V is supplied to the control gate G connected to the word line, the drain D connected to the bit line is opened, and 4 V is applied to the source S connected to the source line. Apply such voltage. As a result, a tunnel current flows through the thin tunnel insulating film between the floating gate FG and the source, and charges accumulated in the floating gate FG are extracted to the source side.

  In such an erasing operation, when the source voltage is increased to 4 V, a large tunnel current is generated and erasing can be performed at high speed. On the other hand, when the source voltage is lowered to 3 V, the tunnel current is greatly reduced and the writing operation is delayed. In terms of the time spent for extracting the same charge, when the source voltage is lowered to 3V, the time is increased by about one digit compared to the case where the source voltage is increased to 4V as described above.

  FIG. 5 is a characteristic diagram showing the relationship between the source voltage and the threshold voltage Vth. As described above, when the source voltage is increased, erasing is performed in a short time, but the variation of the threshold voltage Vth of the erased memory cell group is increased. In other words, the threshold voltage distribution in the erased memory cell group becomes wider. On the other hand, when the source voltage is lowered to 3V, the erase time becomes extremely long, but the variation of the threshold voltage Vth becomes small. That is, the threshold voltage distribution in the erased memory cell group can be kept within a narrow range.

  In this embodiment, the verify (read operation) or write operation is negligibly short compared to the time required for the erase operation, and the relationship between the source voltage and the Vth in the erase operation as described above is utilized. In the first time, the source voltage is set to a relatively high voltage such as about 4 V, and the erase operation is performed with a relatively high setting voltage EV1 in consideration of the variation in Vth under the source voltage. In addition, the threshold voltage Vth of the memory cell group is shifted to a low level within the range where over-erasing is not performed. Thereafter, when the threshold voltage Vth becomes too small by the high-speed erasing operation, the set voltage WV1 is detected and rewriting is performed.

  In the second erasing operation, the erasing operation is performed while taking a relatively long time so that the source voltage is lowered to 3 V and becomes a relatively small setting voltage EV2 or less. By such a second erase operation, it is possible to perform an erase operation having a low threshold voltage Vth while preventing generation of an over-erased memory cell.

  That is, in the second erasing operation, the threshold voltage of the memory cell group erased by the first erasing operation is shifted low as a whole, so even if the source voltage is lowered as described above, erasing is performed. Since the amount itself is small, the entire erasing time can be shortened even if the operations of steps (1) to (6) are performed.

  For example, when there are about 2K (2048 bits) memory cells in one word line when the erase unit is performed in units of word lines, erasing can be performed in about 10 ms. The time ratio takes about 8 ms in the second erase operation in steps (7) and (8) of FIG. 1, and is one digit less than that in the first erase operation in steps (3) and (4). About 1 to 2 ms, which is short, is spent, and the remaining steps (1) and (2) and (5) and (6) have a short time of 1 ms or less. Incidentally, by using steps (7) and (step 8), the erased state as shown in FIG. 2 (E) can be created by performing only one erase operation on the memory cells after the pre-write as described above. However, the time required for this is about 100 ms or more, which is no longer practical.

  FIG. 3 shows a schematic timing chart of an embodiment for explaining the outline of the erase operation according to the present invention. In the time axis of the figure, the erase and write-back portions are shown compressed to represent the entire operation sequence. 1 conceptually shows the entire erase sequence corresponding to the schematic flowchart of FIG. 1, and does not correspond exactly to the actual erase sequence.

  At the time of prewrite, memory cells are sequentially selected by a write verify start signal, and the word line potential to be erased is increased and prewrite is performed on the memory cells in the erased state.

  In the first erase (1), an erase signal is generated, the potential of the erase target word line is set to a negative voltage such as −10V, and the potential of the source line is set to a relatively high voltage such as + 4V. . At this time, the potential of the erasure non-target word line is set to an erasure prevention potential of about 2V. That is, in a memory cell connected to a word line that is not erased, a tunneling current does not occur because the potential difference between the source and the control gate is only about 2V.

  In the first erase verify (1), the memory cell is read by an erase verify (1) activation signal. At this time, the erase verify (1) potential EV1 is selected such that a depletion failure does not occur due to variations in the threshold voltage Vth by the erase (1).

  Next, write back is performed on a memory cell that may cause a depletion failure. In the write verify, the word line is set to WV1, and the write back is performed on the memory cell that is turned on.

  After this, the second erase (2) is performed. At this time, the operation is carried out with a source line potential as low as about 3V. In the erase verify, the potential of the word line is set to be equal to or lower than the voltage EV2 corresponding to the lower limit voltage Vccmin. For example, when the power supply voltage Vcc is lowered to 3.3V and the allowable variation is ± 10%, the erase verify voltage EV2 is set to 2.9V or less.

  FIG. 6 is a schematic block diagram showing one embodiment of a flash memory according to the present invention. Each circuit block shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

  An address buffer 1 has an address latch function. An address change detection circuit 2 generates a one-shot pulse when a change in the address signal is detected. This pulse is not particularly limited, but is used to equalize the potential of the bit line in order to speed up the read operation.

  Reference numeral 3 denotes an X decoder, which selects a word line of the memory mat 5. In the flash memory, the potential of the word line is set to various potentials as described above according to the operation mode. That is, a high voltage such as +11 V is set during the write operation, and a negative voltage such as −11 V is set during the erase operation. In writing or erasing verification, the potential is set to WV1, EV1, EV2, or the like, and in reading operation, the voltage corresponds to the power supply voltage Vcc. Therefore, a word driver 12 having a voltage switching function as described later is provided on the input side of the X decoder 3.

  Reference numeral 4 denotes a Y decoder which forms a bit line selection signal of the memory mat 5. The switch control of the Y gate circuit 6 is performed by this bit line selection signal. The Y gate circuit 6 connects the bit line of the memory mat 5 and the sense amplifier 9 or the write latch 8 according to the selection signal.

  The memory mat 5 is configured by arranging memory cells in a matrix at intersections of word lines and bit lines. That is, the word line is connected to the control gate, the drain is connected to the bit line, and the source is connected to the source line. A floating gate is provided under the control gate, and writing is performed by injecting electrons into the floating gate, and the erase operation is performed by extracting the electrons to the source side. Although not particularly limited, the source MOSFET 7 switches the bias voltage applied to the source line. That is, a circuit ground potential is applied during the read operation and the write operation, and switching between 4V and 3V is performed as described above during the erase operation.

  A write signal input from the external terminal I / Oi is input to the write latch 8 through the data input buffer 11. On the one hand, the output signal of the sense amplifier 9 is output to the external terminal I / Oi through the data output buffer 10. The output signal of the sense amplifier 9 is also transmitted to the automatic control circuit 15 for the verify operation.

  The control buffer 13 determines the operation mode based on the chip enable signal / CE and the output enable signal / OE. For example, when only the signal / CE is set to the low level, the data input from the external terminal I / Oi is taken into the command decoder 14 as a command. The command decoder 14 decodes the input command and determines the write / erase operation. In the read mode, the signal / CE and the signal / OE are set to the low level, and the control buffer 13 determines them.

  The command decoder 14 decodes the input command and inputs a write control signal or an erase control signal to the automatic control circuit 15. The automatic control circuit 15 performs a sequence control operation necessary for the erase operation or the write operation corresponding to the erase method as in the embodiment of FIG. 1 by the write control signal or the erase control signal. The automatic control circuit 15 includes an address counter, generates an address signal for pre-verify, write verify, or erase verify in the erase operation as described above, and passes through the address buffer to the X decoder 3 and the Y decoder. 4 is formed. The driver 12 switches a plurality of types of voltages applied to the word lines and supplies them to the X decoder. In practice, the driver 12 selects one of the above-described plurality of voltages according to the output of the X decoder and the operation mode signal to drive the word line.

  The status register 16 stores an internal state such as an operation mode and an operation sequence, and is read from the data output buffer as necessary. That is, a host system such as a microcomputer grasps the internal state of the flash memory by data polling or the like and controls it. In other words, when an erase operation requiring a long time of about 10 ms is performed as described above, when a microcomputer or the like issues an erase command and an address to the flash memory, the flash memory is immediately disconnected from the bus, The other peripheral devices are connected so that other data processing can be started during the erasing time. When the end of erasure is detected by the above polling, an operation such as writing can be started.

  The voltage detection circuit 18 detects the power supply voltage Vcc and the high voltage Vpp. In particular, the write high voltage Vpp is used for detection because a high voltage such as 12 V needs to be supplied only during a write or erase operation. The voltage generation circuit 17 generates an erase prevention voltage and an erase negative voltage in addition to the verify voltages WV1, EV1, EV2 as described above. Since a series of erase operations can be executed by an automatic control circuit provided inside as in this embodiment, a flash memory that is easy to use can be obtained.

  FIG. 7 shows a schematic block diagram of an embodiment of the automatic control circuit. The automatic control circuit is classified into one that controls the source MOSFET and one that controls the X decoder. A circuit for controlling the source MOSFET is a source bias circuit, and an erase time is set by a pulse length setting circuit in accordance with a signal from a command decoder, and a source bias voltage is set by a power supply voltage control circuit. Note that the erase pulse length is fixed when the erase operation is performed twice and the source voltage is switched as in the above embodiment.

  Along with the switching of the source voltage as described above, the erase time may be different between the first time and the second time. For example, at the time of the first erase, the source voltage is set to a large voltage such as 4V and the erase time is lengthened to increase the erase energy determined by the voltage and time, and at the second erase, the source voltage is set to 3V. In addition, the erase time is shortened to reduce the erase energy so as to suppress the variation in Vth. Alternatively, it is equivalent to setting the source voltage to be the same as 4 V and reducing the source voltage by making the second erase time significantly shorter than the first erase time by the pulse length setting circuit. An operation may be performed.

  What controls the X decoder includes a sector (word line unit) erase bias circuit, an erase verify bias circuit, a write bias circuit, and a write verify bias circuit. That is, in the sector erase bias circuit, the bias voltage of the word line is set to two types of bias voltages, that is, an erase target word line and an erase non-target word line (erase prevention). In the erase verify bias circuit, EV1 and EV2 corresponding to the first and second erase are set. The write bias circuit sets a bias voltage corresponding to the write operation. In the write verify bias circuit, a bias voltage for normal write operation and a bias voltage WV1 corresponding to the write back are set. Each of these circuits is operated in response to a timing pulse formed by the address generator.

  FIG. 8 shows a block diagram of an embodiment of the memory mat and its peripheral circuits. The memory mat has a memory cell composed of a control gate indicated by a solid line and a floating gate indicated by a dotted line at the intersection of a word line W0 to W3 extended in the horizontal direction and a bit extended in the vertical direction. A matrix is arranged. The word line is driven by an X decoder, and the bit line is connected to a write load circuit through a Y gate composed of a MOSFET that is switch-controlled by a Y gate driver. Further, it is connected to a sense amplifier via a switch MOSFET that is switch-controlled by the Y gate and Y pre-gate driver.

  Although not particularly limited, the erase unit is a word line unit (sector). Since 2048 memory cells are connected to the word line, an erasing operation is performed in units of about 2K bits. Instead of this configuration, it is also possible to employ a configuration in which erasure is performed in units of blocks each consisting of a plurality of word lines or memory mats are erased collectively. In accordance with such an erase unit, the number of word lines selected at the time of erasure is increased. In the erase verify, the address of the word line is switched so that a plurality of word lines corresponding to the erase unit are sequentially switched.

  FIG. 9 shows a specific circuit diagram of an embodiment of a memory mat partial selection circuit. This figure shows part of a word line selection circuit and a bit line selection circuit. The word driver shown in FIG. 1 is composed of a changeover switch circuit, and a negative voltage formed by a negative voltage generation circuit, Vpp or Vcc selectively supplied through a power supply switching circuit, and a bias voltage supplied from a bias voltage terminal are connected to a word line. To tell.

  For such word driver switch control, an X decoder divided into two stages is provided, and one of the X decoders is switched between selection and non-selection switching formed by an erase control circuit. That is, in the write and read operations, the selected one is high level and the non-selected one is low level, while in the erase operation, the selected one is low level like a negative voltage, and the non-selected one is erased. Since it becomes a high level corresponding to the blocking, the X decoder also transmits the signal to the word driver at a reverse level accordingly.

  The source bias circuit supplies a relatively high voltage such as 4V to the source line during the first erase operation by the erase signal, and a relatively low voltage such as 3V to the source line during the second erase operation. Supply. Then, when it is other than the erase operation, in other words, at the time of writing and reading (including verification), the ground potential of the circuit is supplied.

  A level conversion circuit is provided at the output section of the Y decoder. The level conversion circuit is selectively supplied with a write high voltage Vpp by a voltage switching circuit controlled by a write signal. In other words, at the time of the write operation, in order to supply a high voltage with respect to the power supply voltage Vcc (3.3 V) such as 4 V to the bit line as described above, a high level corresponding to Vcc formed by the Y decoder is set. , A high voltage corresponding to Vpp is supplied to the gate of the switch MOSFET constituting the Y gate to perform switch control. As a result, a high voltage such as 4 V formed by a write load circuit described below can be supplied to the bit line without level loss due to the threshold voltage in the switch MOSFET.

  In the figure, a P-channel MOSFET is distinguished from an N-channel MOSFET by adding an arrow to its gate. A MOSFET in which an L-shaped line is added to a drain to which a high voltage of the MOSFET is supplied indicates that the withstand voltage is increased. The same applies to the following circuit diagrams.

  FIG. 10 shows a specific circuit diagram of an embodiment of another partial selection circuit of the memory mat. In the figure, a bit line selection circuit is mainly shown. Therefore, a part of the bit line selection circuit is shown overlapping with that of FIG. That is, the Y gate circuit, which is a bit line selection circuit, is divided into two stages. One Y decoder divided into two is supplied to the gate of the switch MOSFET whose one end is connected to the bit line through the level conversion circuit as described above. Corresponding to the plurality of switch MOSFETs, a switch MOSFET that is switch-controlled by the other Y decoder is provided. Since these second-stage switch MOSFETs are used exclusively for reading, the corresponding Y decoder selection signal is supplied as it is. These switch MOSFETs connect the signal of the selected bit line to the input terminal of the sense amplifier SA. An output signal of the sense amplifier SA is supplied to an output buffer and a read determination circuit used in a verify operation.

  The write control circuit includes a write latch circuit, and writing (page write) is possible in units of a plurality of bit lines. That is, data for a plurality of bit lines is stored in the write latch circuit, and the write MOSFET is controlled by the write signal to transmit the write high voltage Vpp to the bit line. In the write operation in units of one bit line, only one of the write load circuits corresponding to the plurality of bit lines is activated.

  FIG. 11 shows a circuit diagram of an embodiment of the voltage switching circuit. That is, the power supply voltage Vcc and the write high voltage Vpp are input, and Vpp, Vcc, the write verify voltage WV1, and the erase verify voltages EV1 and EV2 are output as the X triver potential according to the write signal and the erase signal. In order to detect that the threshold voltage of the memory cell has become equal to or higher than Vcc, the write verify voltage WV1 is level-shifted to a high voltage corresponding to the high voltage Vpp. . Thus, the switch control signal transmitted to the gate of the switch MOSFET that outputs a voltage higher than the power supply voltage Vcc such as 3.3 V is output via the level conversion circuit. The level conversion circuit is provided between a P-channel MOSFET in which a gate and a drain are cross-connected, and a drain potential of the P-channel MOSFET and a ground potential of the circuit, and input signals having mutually opposite phases are supplied to the gate. N-channel MOSFET.

  FIG. 12 shows a circuit diagram of an embodiment of the negative voltage generating circuit. The negative voltage generation circuit supplies a clock pulse to the level conversion circuit through the gate circuit controlled by the erase signal to convert it to the Vpp level, and generates a negative voltage by the charge pump circuit driven thereby. Such a negative voltage is a constant voltage set by a Zener diode based on the erase potential. That is, the addition voltage of the threshold voltage and the Zener voltage of the MOSFET whose gate is supplied to the erase voltage is transmitted to the X driver as the erase voltage. The drain of the MOSFET to which the erase voltage is supplied to the gate is connected to the high voltage Vpp via a P-channel MOSFET. This P-channel type MOSFET is switch-controlled by the output signal of the level conversion circuit that receives the erase signal, and is turned off at times other than the erase operation.

  Further, a level conversion circuit using the negative voltage as an operating voltage is provided, and during the erase operation, the N-channel MOSFET provided between the negative voltage output and the circuit ground potential is turned off, and the erase operation is completed. Turns on and resets negative voltage to circuit ground potential.

  FIG. 13 shows a connection relation diagram of signals focusing on the microprocessor CPU and the flash memory. When an address signal specifying an address space assigned to the flash memory is supplied to the address decoder, the chip enable terminal / CE, output enable terminal / OE and write enable terminal / WE of the flash memory are decoded here. Formed by gate circuits receiving the signals / RD and / WR for designating the operation mode. In this embodiment, the write mode is set by the write enable terminal / WE. However, when the write mode is designated by the command as described above, this terminal / WE can be omitted.

  The data buffer is a bidirectional buffer and transfers write data from the microcomputer to the flash memory during a write operation. When the operation mode is instructed by a command as described above, data transfer is performed in the above-described direction even when the flash memory is accessed. In the read operation, data read from the flash memory is transferred to the microcomputer.

  When accessing the flash memory, the data register takes in data and controls the relay to supply a voltage of 5V or 12V to the high voltage terminal Vpp.

  In the microcomputer system of this embodiment, the flash memory has the automatic erasure function as described above. Therefore, in the microcomputer (MPU), the erase mode is designated by designating the erase address of the flash memory. Signals / RD, / WE and / DEN and commands are generated. Thereafter, the flash memory enters an automatic erasing mode internally as described above. When the flash memory enters the erase mode, the address terminal, data terminal and all control terminals become free as described above, and the flash memory is electrically isolated from the microcomputer MPU. Therefore, the microcomputer MPU merely instructs the flash memory to be in the erasing mode, and thereafter transmits / receives information to / from other memory devices ROM and RAM (not shown) or input / output ports using the system bus. The accompanying data processing can be performed.

  As a result, the flash memory can be erased as it is mounted on the system in the same manner as a full function (byte-by-byte rewritable) memory without sacrificing system throughput. After instructing the erase mode as described above, the microprocessor CPU designates the data polling mode for the flash memory at an appropriate time interval, reads the status register, and when the erase is completed, the flash memory If there is data to be written to, an instruction for writing is given.

The effects obtained from the above embodiment are as follows. That is,
(1) In a batch erase type nonvolatile memory device having a memory cell in which charge accumulated in a floating gate by a write operation is discharged to the source side to perform erase, in the batch erase operation of such a nonvolatile memory element A first operation for reading a memory cell in an erase unit and performing pre-write on a nonvolatile element in which no charge is accumulated in the floating gate, and relatively large energy for the nonvolatile element in the erase unit collectively A second operation for performing an erasing operation at a high speed under a relatively large erasing reference voltage, and a writing operation for reading out all the erased non-volatile elements to a relatively low threshold voltage And a relatively small erase with a relatively small energy at a time with respect to the nonvolatile memory element of the erase unit. By providing an automatic erase circuit that sequentially performs a fourth operation for performing an erase operation at a low speed under a reference voltage, a memory cell that may be over-erased in the third operation is detected and written in advance. The threshold voltage in the erased state can be accurately increased to a low voltage while preventing over-erasure by combining the return operation and the collective erase operation with low energy variation in the fourth operation. The effect that it can be set is obtained.

  (2) According to the above (1), the operating voltage of the flash memory can be lowered to about 3V.

  (3) The source potential of the nonvolatile memory element in the erase operation in the second operation is set to a relatively high voltage, and the source potential of the nonvolatile memory element in the erase operation in the fourth operation By setting to a relatively low voltage, the threshold voltage in the erased state can be set in a short time and with high accuracy.

  (4) The write operation for injecting charges into the floating gate can shorten the write time by using hot electrons generated in the vicinity of the drain, so that the operation speed can be increased.

  (5) In a batch erasure type nonvolatile memory device having a nonvolatile element that performs erasing by discharging the charge accumulated in the floating gate by the write operation to the source side, the memory cell in the erase unit is read and the charge is charged in the floating gate. The first operation of performing pre-write on the non-volatile element in which no charge is stored, and the non-volatile element in the erase unit are collectively brought into a relatively large erase reference voltage by a relatively large energy. A second operation for performing an erase operation; a third operation for performing a shallow write operation on all of the erased nonvolatile elements read to a relatively low threshold voltage; and the erase unit A fourth erasing operation is performed on all the non-volatile memory elements so as to be lower than a relatively small erasing reference voltage with a relatively small energy. By sequentially performing the operation, it is possible to detect a memory cell that is likely to be over-erased in the third operation and perform write back in advance, and to reduce the variation in low energy in the fourth operation. It is possible to set the threshold voltage in the erased state to a low voltage with high accuracy while preventing over-erasure by combining with a small batch erase operation.

  (6) In the erasing method, the source potential of the nonvolatile memory element in the erasing operation in the second operation is set to a relatively high voltage, and the source of the nonvolatile memory element in the erasing operation in the fourth operation By setting the potential to a relatively low voltage, it is possible to set the threshold voltage of the erased state in a short time and with high accuracy.

  The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, the erasing method described above is implemented by an automatic control circuit built in the flash memory, or a control necessary for the erasing operation directly from a control circuit provided outside the flash memory or a microcomputer. It may be performed by inputting a signal or an address.

  The write operation of the flash memory may be performed by injecting electrons into the floating gate by a tunnel current in addition to using hot electrons as described above. A specific circuit for executing the erase sequence as described above can take various embodiments. The present invention can be widely used for flash memories and erasing methods thereof.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a batch erase type nonvolatile memory device having a memory cell in which charges accumulated in a floating gate by a write operation are released to the source side to perform erase, erase in the batch erase operation of such a nonvolatile memory element A first operation of reading a unit memory cell and performing pre-write on a nonvolatile element in which no charge is accumulated in the floating gate; A second operation for performing an erasing operation at a high speed under a relatively large erasing reference voltage, and a writing operation with respect to the erasable all nonvolatile elements read to a relatively low threshold voltage. The third operation to be performed and the non-volatile memory element in the erase unit are collectively relatively small by relatively small energy. By providing an automatic erase circuit that sequentially performs a fourth operation for performing an erase operation at a low speed under the erase reference voltage, a memory cell that may be over-erased in the third operation is detected in advance. The combination of the write-back operation and the batch erase operation with low energy and small variation in the fourth operation prevents the over-erasure, and the threshold voltage in the erase state is highly accurate up to a low voltage. Can be set to

  With the above (1), the operating voltage of the flash memory can be reduced to about 3V.

  The source potential of the nonvolatile memory element in the erase operation in the second operation is set to a relatively high voltage, and the source potential of the nonvolatile memory element in the erase operation in the fourth operation is relatively By setting the voltage to a low voltage, the threshold voltage in the erased state can be set in a short time and with high accuracy.

  The write operation for injecting charges into the floating gate can shorten the write time by using hot electrons generated in the vicinity of the drain, so that the operation speed can be increased.

  In a batch erasure type nonvolatile memory device having a nonvolatile element that performs erasing by releasing the charge accumulated in the floating gate by the write operation to the source side, the memory cell in the erase unit is read and the charge is accumulated in the floating gate. A first operation of performing pre-write on a non-volatile element that has not been erased, and an erasing operation on the non-volatile element in the erase unit so that the non-volatile element is reduced to a relatively large erase reference voltage or less by a relatively large energy. A second operation to be performed; a third operation to perform a shallow write operation on all of the erased non-volatile elements read to a relatively low threshold voltage; and a non-volatile of the erase unit A fourth operation for performing an erasing operation so that the memory element is reduced to a relatively small erasing reference voltage or less by a relatively small energy at a time. Are sequentially performed to detect memory cells that may be over-erased in the third operation and perform write back in advance, and there is little variation in low energy in the fourth operation. The threshold voltage in the erase state can be set to a low voltage with high accuracy while preventing over-erasure by a combination with the batch erase operation.

  In the erase method, the source potential of the nonvolatile memory element in the erase operation in the second operation is set to a relatively high voltage, and the source potential of the nonvolatile memory element in the erase operation in the fourth operation is compared. By setting the target low voltage, the threshold voltage of the erased state can be set in a short time and with high accuracy.

1 is a schematic flowchart for explaining one embodiment of a flash memory erasing method according to the present invention. FIG. FIG. 5 is a distribution diagram of threshold voltages of memory cells corresponding to the flash memory erasing method according to the present invention. FIG. 5 is a schematic timing chart showing an embodiment for explaining an outline of an erase operation according to the present invention. It is a schematic sectional drawing which shows one Example of the memory cell to which this invention is applied. It is an erasing characteristic diagram showing the relationship between the source voltage and the threshold voltage Vth of the memory cell to which the present invention is applied. 1 is a schematic block diagram showing an embodiment of a flash memory according to the present invention. It is a schematic block diagram which shows one Example of the automatic control circuit of FIG. 1 is a block diagram showing one embodiment of a memory mat and its peripheral circuits in a flash memory according to the present invention. FIG. 3 is a specific circuit diagram showing one embodiment of a memory mat partial selection circuit in the flash memory according to the present invention; FIG. It is a specific circuit diagram showing one embodiment of another partial selection circuit of the memory mat in the flash memory according to the present invention. 1 is a circuit diagram showing one embodiment of a voltage switching circuit in a flash memory according to the present invention. FIG. 1 is a circuit diagram showing one embodiment of a negative voltage generating circuit in a flash memory according to the present invention. FIG. It is a connection relation diagram of each signal paying attention to the microprocessor CPU and the flash memory. It is a threshold voltage distribution diagram by a conventional erasing method.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Address buffer, 2 ... Address signal change detection circuit, 3 ... X decoder, 4 ... Y decoder, 5 ... Memory mat, 6 ... Y gate circuit, 7 ... Source MOSFET, 8 ... Write latch, 9 ... Sense amplifier, 10 Data output buffer, 11 Data input buffer, 12 Driver, 13 Control buffer, 14 Command decoder, 15 Automatic control circuit, 16 Status register, 17 Voltage generation circuit, 18 Voltage detection circuit

Claims (17)

A plurality of memory cells for storing information by a threshold voltage;
A command decoder that decodes the supplied command;
A control circuit for performing a predetermined operation according to a result decoded by the command decoder,
Each of the plurality of memory cells includes a floating gate,
A first threshold voltage distribution indicating that the information stored in the memory cell is in the first state, and a second threshold indicating that the information stored in the memory cell is in the second state The first threshold voltage distribution and the second threshold voltage distribution are both set to a voltage range of 0 V or more,
According to the result of the command decoder decoding a command for instructing a threshold voltage change operation, the control circuit supplies electrons from the floating gate so that the threshold voltage of the memory cell changes within a positive voltage range. A first discharge operation for discharging and changing a threshold voltage of the plurality of memory cells into a third threshold voltage distribution between the first threshold voltage distribution and the second threshold voltage distribution; After the first discharge operation, the threshold voltage of the memory cell determined to have a threshold voltage lower than a predetermined positive voltage in the third threshold voltage distribution is set to the predetermined positive voltage. Injection operation for injecting electrons into the floating gate so as to be higher than that, and after the injection operation, electrons are discharged from the floating gates of the plurality of memory cells so that the threshold voltage becomes 0 V or higher. Nonvolatile memory device characterized by causing the second release operation to. In claim 1,
A voltage generating circuit for forming the predetermined positive voltage from the supplied power supply voltage;
Having a plurality of word lines to which the control gates of the memory cells are coupled;
The nonvolatile memory device, wherein the predetermined positive voltage is selectively applied to the plurality of word lines. In claim 1,
Each of the plurality of memory cells has a control gate, the floating gate is formed on the control gate, and a pair of semiconductor regions of the floating gate is formed,
The difference between the internal voltage applied to the control gate of the memory cell in the first discharge operation and the internal voltage applied to one of the pair of semiconductor regions is the control of the memory cell in the second discharge operation. A nonvolatile memory device, wherein a difference between an internal voltage applied to a gate and an internal voltage applied to one of the pair of semiconductor regions is larger. In claim 1,
The non-volatile memory device, wherein the injection operation is performed using hot electrons. In claim 3,
The non-volatile memory device, wherein a voltage applied to one of the semiconductor regions in the first emission operation is lower than a voltage applied to one of the semiconductor regions in the second emission operation. In claim 1,
According to the decoding result of the command decoder, before the first discharge operation, charges are injected into the floating gate in order to shift the threshold voltages of the plurality of memory cells in the direction of the first threshold voltage distribution. A non-volatile memory device that performs a prewrite operation. Each of the plurality of blocks includes at least one word line, a plurality of data lines, and a plurality of memory cells storing information according to a threshold voltage;
A selection unit for selecting at least one block of the plurality of blocks;
A command decoder that decodes the supplied command;
A control circuit for controlling a predetermined operation in accordance with a decoding result of the command decoder,
Each of the plurality of memory cells has a floating gate,
A first threshold voltage distribution indicating that the information stored in the memory cell is in the first state, and a second threshold indicating that the information stored in the memory cell is in the second state The first threshold voltage distribution and the second threshold voltage distribution are both in the positive voltage range,
The control circuit controls the first discharge operation, the injection operation, and the second discharge operation according to a result of the command decoder decoding a command for instructing a threshold voltage change operation,
In the first discharge operation, an erase voltage for discharging charges from the floating gate is applied to the memory cell so that the threshold voltage of the memory cell in the selected block transitions within a positive voltage range. The threshold voltage of a memory cell having a threshold voltage included in the first threshold voltage distribution is shifted in the direction of the second threshold voltage distribution, and the memory cell in the selected block Is set within a third threshold voltage distribution between the first threshold voltage distribution and the second threshold voltage distribution,
In the injection operation, after the first discharge operation, the threshold voltage of the memory cell determined to be lower than the predetermined positive voltage in the third threshold voltage distribution is set higher than the predetermined positive voltage. To inject electrons into the floating gate
In the second discharge operation, after the injection operation, the charge from the floating gate of the memory cell in the selected block is set so that the threshold voltage of the memory cell in the selected block is set higher than 0V. A non-volatile memory device, wherein the threshold voltage of the discharged memory cell is changed so as to be included in the second threshold voltage distribution. In claim 7,
Each of the plurality of memory cells has a control gate and a pair of semiconductor regions,
The non-volatile memory device according to claim 1, wherein the charge in the floating gate is discharged to one of the pair of semiconductor regions in the first and second emission operations. In claim 8,
In the first discharge operation, the difference between the internal voltage to be supplied to the control gate of the memory cell and the internal voltage to be supplied to one of the pair of semiconductor regions is the second discharge operation. A non-volatile memory device, wherein a difference between an internal voltage to be supplied to a control gate of a memory cell and an internal voltage to be supplied to one of the pair of semiconductor regions is different. In claim 8,
The time during which the internal voltage is supplied to one of the control gate and the one semiconductor region in the first emission operation is the same as the time period in which the internal voltage is supplied to one of the control gate and the pair of semiconductor regions in the second emission operation. A non-volatile memory device, characterized in that it differs from the time during which voltage is supplied. In claim 7,
In accordance with the decoding result of the command decoder, before the first discharge operation, charges are injected into the floating gate to shift the threshold voltages of the plurality of memory cells in the first threshold voltage distribution direction. A non-volatile memory device that performs a pre-write operation. A plurality of word lines, a plurality of memory cells, and a control circuit;
Each of the plurality of memory cells stores a first state of information to be stored by setting a threshold voltage of the memory cell between the first voltage and the second voltage, and the threshold value of the memory cell Storing a second state of information to be stored by setting the voltage between the third voltage and the fourth voltage;
The potential difference between the first voltage and the fourth voltage is larger than the potential difference between the second voltage and the third voltage, and the second voltage and the second voltage are between the first voltage and the fourth voltage. 3 voltage is set, and the second voltage is closer to the first voltage than the third voltage, and the third voltage is closer to the fourth voltage than the second voltage, All of the fourth voltages are positive,
Each of the plurality of word lines is connected to a corresponding group of memory cells among the plurality of memory cells,
The control circuit selects one word line in response to an operation command from the outside, applies a predetermined voltage to the selected word line, stores information in the memory cell, and stores the information in the memory cell. Control each operation to erase information or read information stored in the memory cell,
In the control of erasing information stored in the memory cell, the control circuit applies an erasing voltage at least twice to the selected word line, and the first of the group of memory cells connected to the selected word line. Control is performed to transition the threshold voltage of the memory cell storing the state between the third voltage and the fourth voltage,
By applying the first erase voltage, the threshold voltages of all the groups of memory cells connected to the selected word line are moved in the direction of the fourth voltage within a positive voltage range,
By applying the second erase voltage, the threshold voltages of all the groups of memory cells connected to the selected word line are moved between the third voltage and the fourth voltage,
After the application of the first erase voltage and before the application of the second erase voltage, the threshold voltages of all of the group of memory cells connected to the selected word line are the third voltage and the first voltage. In a state in which the voltage does not move between the first voltage and the fourth voltage, the fifth voltage among the threshold voltages of the group of memory cells with the fifth voltage between the first voltage and the fourth voltage as a reference. A non-volatile memory device comprising determination control for moving a threshold voltage of a memory cell that is moving between a fourth voltage and a fifth voltage between the fifth voltage and the first voltage. In claim 12,
In the determination control, the control circuit performs a read operation by applying the fifth voltage to the selected word line after the first erase operation, and the group of memory cells according to a read result A non-volatile memory device characterized by determining whether or not the threshold voltage is moving between the fifth voltage and the fourth voltage. In claim 12,
The non-volatile memory device, wherein the control circuit performs the determination control after performing the first erasing voltage application a plurality of times. In claim 14,
A non-volatile memory device, wherein after the determination control is performed, the second erase voltage is applied a plurality of times. Storing a first state of information by having a threshold voltage higher than the first voltage, and having a threshold voltage between a second voltage lower than the first voltage and a third voltage lower than the second voltage; A non-volatile memory device having a memory cell for storing a second state of information in which all of the first voltage, the second voltage, and the third voltage are in a voltage range higher than 0V;
In the operation of moving the threshold voltage of the memory cell storing the first state between the second voltage and the third voltage to store the second state,
A first operation in which a voltage for lowering the threshold voltage of the memory cell is applied to the memory cell within a range where the threshold voltage of the memory cell does not become 0 V or less; and a first operation in which the threshold voltage of the memory cell is higher than 0 V When the voltage is lower than 4, the second operation of applying a voltage to the memory cell to make the threshold voltage of the memory cell higher than the fourth voltage, and further the threshold voltage of the memory cell is A third voltage is applied to the memory cell to lower the threshold voltage of the memory cell within a range not lower than 0 V, and the threshold voltage of the memory cell is moved between the second voltage and the third voltage. A non-volatile memory device that performs control to perform an operation. In claim 16,
A plurality of the memory cells;
In the operation of moving the threshold voltages of the plurality of memory cells storing the first state between the second voltage and the third voltage to store the second state, the second operation Performing the second operation in a state where a threshold voltage of at least one memory cell among the plurality of memory cells storing the first state is higher than the second voltage. Non-volatile storage device.

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