JPH07182877A - Method of erasing data of nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the dispersion in a threshold value after erasure by repeating erasure operation and verification in a short period. CONSTITUTION:By implanting an electron into a floating gate electrode 3, the data are written. An drain voltage Vd is applied to a drain area 6, and a substrate voltage Vsub of 0V and source data Vs are applied to a semiconductor substrate 1 and a source area 7, respectively, and a gate voltage Vcg is applied to a control gate electrode 5. The potential of the electrode 3 is decided unequivocally from the voltages Vd, Vs, Vsub, Vcg by a capacitance ratio formed by a gate oxidized film 2 and a gate insulation film 4. The erasure of the data is performed by pulling out the electron from the electrode 3. Before the erasure, the whole bits are written. The maximum value of the threshold value after erasure is set, and the erasure and the verification by a short pulse are repeated until the whole memory cells are satisfied with the condition. By such a manner, the dispersion in the threshold value after erasure is put within a prescribed range.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for erasing data in a non-volatile semiconductor memory device, and more particularly to a method for erasing data in a non-volatile semiconductor memory device in which a field effect transistor having a floating gate electrode is used as a memory cell. Regarding

[0002]

2. Description of the Related Art Among electrically rewritable nonvolatile semiconductor memory devices (EEPROM), a plurality of memory elements (E
A flash memory has a function of electrically erasing EPROM elements simultaneously at once. An example of the structure of this flash memory is shown in FIG.

In the flash memory shown in FIG. 3, an n-type drain region 6 and a source region 7 are formed on the surface of a p-type semiconductor substrate 1, and a channel region 8 between the two regions is formed.
On the top and on the end portion 9 of the drain region 6 and the end portion 10 of the source region 7, a gate oxide film 2 having a film thickness of 10 nm, a floating gate electrode 3 formed of polycrystalline silicon, a gate insulation film having a film thickness of about 25 nm. This is a structure in which the film 4 and the control gate electrode 5 are laminated. The operation of this flash memory will be described below.

Data writing means floating gate electrode 3
Is to inject electrons into. For that purpose, for example, a drain voltage Vd of + 7V is applied to the drain region 6, and a substrate voltage Vsub and a source voltage Vs of 0V (ground potential) are applied to the semiconductor substrate 1 and the source region 7, respectively.
Further, for example, a gate voltage V of + 12V is applied to the control gate electrode 5.
Apply cg. Since the floating gate electrode 3 is not connected to an external power source, its potential depends on the capacitance ratio formed by the gate oxide film 2 and the gate insulating film 4, and the drain voltage Vd, the source voltage Vs, the substrate voltage Vsub, and the gate voltage Vsub. It is uniquely determined from the voltage Vcg. Usually, when the potential of the floating gate electrode 3 becomes approximately equal to the potential of the drain region 6 (drain voltage Vd), hot electrons (gate oxide film) generated by the current flowing between the drain region 6 and the source region 7 are generated. The maximum amount of electrons having an energy exceeding the insulation energy of 2) is injected into the floating gate electrode 3. Each of the voltage examples described above is a value that is in that state.
At that time, electrons are injected into the floating gate electrode 3 and push down the potential of the floating gate electrode 3 to a negative level.
The threshold of the memory cell, that is, the threshold seen from the control gate electrode 5 shifts in the positive direction. Normally, the threshold value of the memory cell is set to about + 7V or higher.

On the other hand, erasing data means extracting the electrons injected into the floating gate electrode 3. For that purpose, for example, the source voltage Vs is set to +12 V, the substrate voltage Vsub and the gate voltage Vcg are set to 0 V (ground potential), and the drain region 6 is opened. In the state where the data is written, the floating gate electrode 3 is at a negative potential, and therefore a potential difference is further applied, and a considerably strong electric field (() is applied to the gate oxide film 2 between the source region 7 and the floating gate electrode 3. In the above voltage examples, 10 MV / cm or more) is applied. Under such a strong electric field, Fowler-Nordheim current (hereinafter referred to as “FN current”) in the gate oxide film 2 based on quantum mechanical tunnel effect.
Say. ) Flows. Data is erased by utilizing this effect to extract electrons from the floating gate electrode 3 to the source region 7.

In this specification, a state in which electrons are injected into the floating gate electrode 3 to shift the threshold value of the memory cell in the positive direction is “writing”, and electrons are extracted from the floating gate electrode 3 to cause the memory cell. The state in which the threshold value of is shifted in the negative direction is defined as "erase", but the write and erase states need only represent two different states of the memory cell, and are not necessarily limited to this expression. is not.

Writing and erasing of memory cells are performed in this way. In the case of a flash memory, writing is performed by the above-described method, whereas erasing is performed by sharing the sources of memory cell arrays arranged in a matrix. The voltage is simultaneously applied to the sources in the connected state. As a result, it is possible to erase all at once, and it is possible to shorten the erase time even when the storage capacity of the storage device becomes large.

However, in the flash memory, the FN
The erasing method of drawing electrons from the floating gate electrode 3 to the source region 7 by a current has a problem that the threshold value of each memory cell after erasing varies. The reason is that the FN current with respect to the applied voltage is determined by the film thickness of the gate oxide film 2 and the area of the overlapping region of the source region 7 and the floating gate electrode 3, and the FN currents do not always match in a plurality of memory cells. by. Therefore, even if the erasing operation is simultaneously performed on a plurality of memory cells, the amount of electrons extracted from each floating gate electrode 3 to the source region 7 varies, and the potential of each floating gate electrode 3 does not become constant,
This means that the threshold value of each memory cell after erasing varies.

FIG. 4 shows the result of measuring the variation in threshold value after erasing in the conventional flash memory.

In the figure, the horizontal axis is the threshold value (V) after erasing, and the vertical axis is the cumulative frequency. It can be seen that the conventional variation in threshold value after erasing has a shape close to a normal distribution and has a width of about 2V. Ie, for example
When erasing memory cells of 256 kilobits (32 kilobytes) at the same time, a difference of about 2V occurs between the erased memory cells and the erased memory cells. Considering such variations in the threshold value, in the case of simultaneously erasing a memory cell array of a certain scale such as a flash memory, the entire erasing should be performed before the threshold value of the memory cell that is erased earliest becomes 0 V or less. I have to stop. This is because when the threshold value becomes 0 V or less, the potential of the bit line (column line) connected to the memory cell cannot be raised, and all memory cells connected to the bit line can be written and read. Because you can't do that either.

For this reason, the entire erasing is stopped before the threshold voltage of the memory cell that is erased earliest becomes 0 V or less. However, the threshold value is actually set to about 0.5V to 1V. , The threshold of the slowest erased memory cell is
It will be set from 2.5V to 3V. Therefore, the potential of the word line (row line) at the time of writing / reading cannot be set lower than the threshold value of the memory cell that erases the latest. That is, the conventional write / read voltage cannot be lowered from 2.5V to 3V or less. Therefore, in order to reduce the voltage of the flash memory, various measures for reducing the variation in the threshold value of each memory cell have been studied.

An example thereof will be described below with reference to the erasing algorithm shown in FIG. This algorithm is based on the literature (VNKynett et al., = A 90ns One-Million Er
ase / Program Cycle 1Mbit Flash Memory ", IEEE Journa
l of Solid-State Circuits, vol.24, No.5, 1989).

First, all bits are written before erasing. This is performed in order to suppress variations in threshold value after erasing. Next, set the maximum threshold value after erasing to, for example, 3.2 V, perform erasing with a short pulse until all memory cells satisfy this condition, and read to confirm whether all memory cells have been erased. The operation (verify) is repeated. By performing such erasing, it becomes possible to keep the variation in the threshold value after erasing within a predetermined range even if various parameters are changed as compared with the case of erasing with a single pulse. . This is because, for example, even if the tunnel film thickness varies and the erase characteristic of the memory cell changes, it is absorbed by repeating erase and verify. Finally, a depletion check is performed to determine whether or not there is a memory cell through which a current flows at a voltage equal to or lower than a predetermined control gate voltage. If a memory cell through which a current flows exists, it is determined to be defective.

[0014]

By the way, in the conventional data erasing method shown by the algorithm of FIG. 5, it is possible to keep the variation of the threshold value within a predetermined range by repeating the erasing and verifying operations. Some storage elements may be erased. If even one over-erased cell occurs on the same bit line, subsequent programming cannot be performed, and all the storage elements on that bit line become defective cells, which cannot be relieved except by exchanging the bit line.

Further, in a series of operations, the ratio of writing all bits before erasing is high with respect to the entire erasing time, the erasing time increases significantly as the integration degree of the memory element increases, and the current consumption also increases. There was a problem.

According to the present invention, variations in threshold values after erasing a plurality of storage elements are reduced, and storage elements that have been over-erased can be relieved, and the erasing time and current consumption can be shortened. An object of the present invention is to provide a data erasing method for a non-volatile semiconductor memory device.

[0017]

The data erasing method of the present invention is performed by the following procedure. The threshold value of each storage element is set to a predetermined value by repeating an erase operation in which electric pulses of a predetermined voltage are simultaneously applied to a plurality of storage elements (memory cells) to be erased and a verify for making an erase determination by reading the storage element. Set below the threshold of. A depletion check is performed to determine whether or not there is a storage element through which a current flows at a predetermined control gate voltage or less. If there is a memory element through which a current flows in the depletion check, a positive voltage is applied to the control gate until the memory element does not exist, and writing is performed to increase the threshold value of the memory element (FN writing). Once again, if there is a storage element that exceeds a predetermined threshold value among the storage elements by verifying that the erase determination is performed by reading the storage element, the erase operation and subsequent steps are repeated.

[0018]

By repeating the erase operation and the verify in a short cycle, the threshold value of each memory element can be set below a predetermined threshold value. A depletion check is continuously performed, and a positive voltage is applied to the control gate to increase the threshold value of the storage element until there is no storage element that is turned on below a predetermined control gate voltage. Further, the verify is performed again, and if there is a storage element that exceeds a predetermined threshold value, the threshold values of a plurality of storage elements can be converged within a predetermined range by repeating the first erase operation.

[0019]

1 shows the algorithm of an embodiment of the method according to the invention.

First, for example, an electric pulse of +12 V is applied to the source region 7 to erase it. At this time, erasing is performed while performing verification so that the memory cell having the highest threshold value among all bits has a predetermined threshold value, for example, + 3V. After this erasing is completed, a depletion check is performed to determine whether or not there is a memory cell in which a current flows (turns on) at a predetermined control gate voltage or less. At this time, if there is no memory cell through which a current flows, the erasing operation is completed through verification again.

On the other hand, if there is a memory cell through which a current flows, the drain voltage Vd, the source voltage Vs, and the substrate voltage Vsu.
Writing is performed by applying +12 V to the control gate electrode 5 with b as the ground potential (hereinafter referred to as “FN writing”). This FN writing is performed until a positive voltage is applied to the control gate electrode 5 to raise the threshold value of the memory cell and no memory cell through which a current flows exists. After that, if there is no memory cell through which a current flows, verification is performed again to determine whether or not all bits have been erased. At this time, for example, if there is a memory cell having a threshold value of 3.5 V or higher, the erase operation is resumed and a series of operations is repeated.

FIG. 4 shows how the threshold value varies after the erase operation is performed according to the algorithm of this embodiment. It can be seen that the variation in the threshold value is reduced to about 1 V by performing the FN writing after the erasing. Further, even if there is a depletion memory cell due to a large variation in threshold value, it can be relieved by FN writing.

Further, since it is not necessary to perform writing before erasing, the total time required for erasing can be shortened and the current consumption can be reduced accordingly. FIG. 2 shows the erase time by the conventional method and the erase time by the method of the present invention. In the conventional method, in the case of 16 Mbit scale, 1.
It takes 25 seconds, 0.01 seconds to erase, and 2.55 seconds to verify. On the other hand, in the method of the present invention, 0.01 seconds for erasing, 0.1 seconds for depletion check, 0.1 seconds for FN writing, and 10 seconds for verifying.
It takes 2.55 seconds. Thus, the time required for erasing according to the method of the present invention can be shortened by the time required for writing before erasing, which is performed by the conventional method. Therefore, the effect of shortening the erasing time becomes large with the large integration scale of 64 Mbits. Further, by performing FN writing after normal erasing, the variation of the threshold value is suppressed and the number of times of verification is reduced, so that there is a possibility that the entire erasing time can be further shortened.

The erasing used in the above description is not limited to the source erasing in which a positive voltage is applied to the source region 7. If electrons are to be extracted from the floating gate electrode 3, another method is used, for example, a source gate erasing method in which a positive voltage is applied to the source region 7 and a negative voltage is applied to the control gate electrode 5, or a negative voltage is applied to the control gate electrode 5. The data erasing method according to the present invention can also be applied to the channel erasing method in which a voltage is applied and a positive voltage is applied to the semiconductor substrate 1.

[0025]

As described above, according to the present invention, it is possible to reduce variations in threshold values after erasing of a plurality of memory elements. In addition, since it becomes possible to rescue the memory elements that are excessively erased, the yield can be improved. In addition, since the writing before erasing, which is performed by the conventional algorithm, is unnecessary, it is possible to reduce the erasing time and the current consumption.

[Brief description of drawings]

FIG. 1 is a diagram showing an algorithm of an embodiment of the method of the present invention.

FIG. 2 is a diagram comparing erasing times by the conventional method and the method of the present invention.

FIG. 3 is a diagram showing an example of a structure of a flash memory.

FIG. 4 is a diagram comparing variations in threshold value after erasing by the conventional method and the method of the present invention.

FIG. 5 is a diagram showing an algorithm of a conventional data erasing method.

[Explanation of symbols]

 1 semiconductor substrate 2 gate oxide film 3 floating gate electrode 4 gate insulating film 5 control gate electrode 6 drain region 7 source region 8 channel region 9 edge of drain region 10 edge of source region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/788 29/792 H01L 29/78 371

Claims (2)

[Claims] 1. A data erasing method for a nonvolatile semiconductor memory device configured by arranging a plurality of memory elements having a two-layer structure gate of a floating gate and a control gate, wherein a threshold value of the plurality of memory elements to be erased is set to a predetermined value. When the depletion check is performed after setting the threshold value below, and if there is a storage element through which current flows, a positive voltage is applied to the control gate until the storage element does not exist, and the threshold value of the storage element is increased. Data erasing method for nonvolatile semiconductor memory device. 2. A data erasing method for a non-volatile semiconductor memory device configured by arranging a plurality of memory elements having a two-layer structure gate of a floating gate and a control gate, wherein a predetermined number of memory elements are simultaneously erased. The threshold value of each memory element is set below a predetermined threshold value by repeating the erase operation of applying an electric pulse of voltage and the verification of erasing judgment by reading out the memory element. A depletion check is performed to determine whether or not a memory element through which a current flows is present. If a memory element through which a current flows is present in the depletion check, a positive voltage is applied to the control gate until the memory element does not exist. Each memory element is verified by verifying that writing is performed to increase the threshold value and then erasing is determined by reading the memory element again. Data erase method of a nonvolatile semiconductor memory device characterized by repeating the erase operation after if any memory element exceeds a predetermined threshold of.