JPS6166297A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To attain an electrical test of a leakage current, etc. in a wafer state by connecting a diode as prescribed among a terminal of the highest potential and a digit line and a word line at the low potential side respectively. CONSTITUTION:The decoupling diodes D1, D2 and D3 whose anodes are set at the side of a terminal 12 are connected among the terminal 12 of the highest potential containing an output transistor TRQ5 of a high impedance state as long as no load is connected to a collector, digit lines D and D' and a word line at the lower potential side respectively. When the leakage is detected between the emitter E and the base B or between the collector C and the base B of TRQ1-Q4 which form an FF of a memory cell, a current flows to a word line WT from the terminal 12 via the leakage current path before the breakdown occurs between E and B or C and B. Thus the diode characteristics of diodes D1 and D2 or the diode D3 are observed. This attains an electrical test of a leakage microcurrent, etc. in a wafer state.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention detects leakage current existing in semiconductor elements, etc.
The present invention relates to a semiconductor memory that can remove such a semiconductor memory.

(Prior Art) Conventionally, semiconductor memories have been subjected to rigorous electrical tests at low and high temperatures after the wafer stage or package assembly to eliminate defective products or those that do not meet electrical standards. However, in recent miniaturized ICs (MP conductor integrated circuits), although there are sometimes current paths within the element, they are shipped as non-defective products because they satisfy electrical standards, and after being mounted in equipment. This leakage current path increases, and there are many cases where ICs are caused to fail. For example, even if the operating current of the circuit is 1 mA and there is a leakage current of KIOμ, it is only 1 mA.
This is because it only disturbs the voltage level to a certain extent, but has no effect on the characteristics and cannot be ruled out in initial electrical tests. That is, the conventional semiconductor memory has the disadvantage that defective elements having minute leakage current paths cannot be completely removed by electrical testing in a non-uniform state.

(Object of the Invention) An object of the present invention is to provide a highly reliable semiconductor memory that can detect even a small surface leakage current in an electrical test in a wafer state by eliminating the above-mentioned drawbacks.

(Structure of the Invention) A semiconductor memory according to a first aspect of the present invention is a semiconductor memory in which memory cells constituting seven lip-flops whose paces and collectors are cross-connected to each other are arranged in a word line direction and a digit line direction. The device includes a diode connected between the highest potential terminal of the digit line and a word line on the low potential side of the digit line and the word line, with the anode connected to the highest potential terminal side.

The semiconductor memory of the second invention is provided with a signal input of the semiconductor memory connected to one of the word lines on the high potential side and the lowest potential terminal of the semiconductor memory in the semiconductor memory of the first invention. It is constructed by adding a word line voltage fixing circuit on the high potential side which is controlled by a control signal applied to the terminal.

A semiconductor memory according to a third aspect of the present invention is constructed by adding a control circuit to the semiconductor memory according to the second aspect of the invention, which controls the holding current and read current of the memory cell array of the semiconductor memory using the control signal. Ru.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a main part of an embodiment of the first invention.

In this embodiment, cell transistors Ql-Q have their bases and collectors cross-connected to form a flip 70 tube.
4 (Ql and Q2 and Q3 and Q4 are each two-emitter type NPN); forming a y-in transistor. ), a load resistance R1, and a load resistance fL.
1, one end of 几2 is commonly connected to the word line WTK on the high potential side, and the cell transistor Q! , Q4 are commonly connected, the emitters of the word line WBK1 on the low potential side are connected to the digit line, and the emitters of the cell transistor Q3 are connected to the digit line DK, forming a memory cell array. Diodes D1 . Ds and Ds are anode tone Vcc
It is connected to the system terminal 12. Furthermore, Vcc^ terminal 12
is connected to the collector of an NPN type output transistor Qs whose emitter is connected to output terminal 0.

A normal ECL type logic circuit has the highest potential terminal as the power supply Vcc terminal connected to the internal circuit and the output transistor Qs.
It has two Vccm terminals 120 to which the collector of the Vcc is connected. Here, when the VCC terminal 12 is connected to the emitter of the output transistor Qs,
Since only the collector of the output transistor Qs is connected, it is in a high impedance state as long as there is no leakage current path between the pace and the collector of the output transistor Qs.

On the other hand, word line WB and digit line H on the low potential side of the memory cell array have cell transistors Q1 to Q4.
Since only the emitter of the word line and the collector of the constant current transistor for supplying constant current to these word lines and digit lines are connected, if the word line WB, digit line, or U is forced to the high potential side, , word line WB and digit line, and the borders are cell transistors Q1~
It remains in a high impedance state until it exceeds the emitter-pace breakdown voltage (BVmm) or emitter-collector breakdown voltage (BY'mc) of Q4. Therefore, as shown in Fig. 1, by connecting the VCCA terminal 12 to the word line WB, digit line, and U through the decoupling diodes DI, D2 and D3, the Vcc terminal 12 is connected to the BVIB of the cell transistor, BVIC can be observed.

FIG. 2 shows the current characteristics when the voltage of the word line WT is QV and a voltage is applied to the VCC& terminal 12. Normally, BYis or BVmc has a value of about 3.5V, so if the forward voltage of diodes Di, Dm, and Da is set to 0.8V and the voltage Vcem is increased to 4.2V or more, the cell transistor will break down. TeVc
diode Ds from cm terminal 12 to Siward line WT;
Current can be passed through Dm and D3'.

By the way, now the cell transistors Q"+Qx, Qs
, If there is a leak between EB (emitter pace) or EC (emitter collector) in any one of Qa, the Vccm terminal will be 12) Since a current flows through the word line WTK, almost the diode characteristics of the diode DI, I)2 or D8 are observed as shown in FIG. 2B. Note that in FIG. 2, A indicates normal characteristics.

As is clear from the above explanation, in this example, memory cells having even the slightest leakage current path can be reliably detected in the electrical test in the wafer state, and a highly reliable semiconductor memory can be obtained. .

FIG. 3 is a circuit diagram showing a main part of an embodiment of the invention of Reiraku 3.

In this embodiment, memory cells Mll...Mnm are word lines W'r+...WTn, WBI...WB
n and digit lines DI, DI...Dm, and fjim, respectively, and constitute a memory cell array 21. and digit line D1. D1...Dm, Dm are each connected to the collector of the constant current transistor of the read current circuit 22, word lines WB1...WBn are each connected to the collector of the constant current transistor of the hold current circuit 23, and the word #! WTt...WTn are each connected to the emitter of the driver transistor of the word driver circuit 24. Furthermore, the word line WTs...WT
n are connected to the collector of the output transistor of the word line voltage fixing circuit 25 via the diode Dwt1...])wtl, and the input transistor Qll of the word line voltage fixing circuit 25 is connected to the internal circuit 26 via the diode Da. is connected to the signal input terminal IN of the memory cell array 21, and this signal input terminal IN is connected to the holding current IWB of the memory cell array 21.
1...If! Ill and read current IDI, I
DI...Inm I is connected to a reference voltage terminal 30 of a reference voltage circuit 27 via a diode Ddt-, which serves as a control circuit for controlling I, etc., and the reference voltage terminal 30 is further used for reading '! ! Flow circuit 22. It is connected to the constant current transistor pace of the holding current circuit 23 and the word driver circuit 24. On the other hand, digit lines Dt, Dt-・Dm, D
The word lines WB1...Wa++ are connected to diodes DDi and DDI...Dm, respectively.

DD; and diode]) wsH...]) Connect diode to cand of van)'Dot, DDI
・"Dam, Dam and])win...D
The anodes of waa are commonly connected to diodes Da and Db.
It is connected to a Vccm terminal 29 connected to the collector of the output transistor 22 through a series connection circuit.

That is, a diode Da is connected to the VCCA terminal 29 to which the collector of the output transistor 28 is connected.

Each digit line DI, through Db...Dm
Diode DDI to Dm, DDI...Doa+,
Dos is connected, and each word line WB1...WBn
are connected to diodes DWBI...DwII-.

In the case of a normal continuous write operation of a memory, the potentials of the digit lines Dt, Dt...Dm, Dm and word lines WBr...WBn are lower than the voltage Vcc of the power supply Vcc by the forward voltage (Vf) of the diode. These diodes Da and Db do not drop to a potential less than three times the potential.

DDI, DDI-DDm, DDffi, Dw+
There is no shadow at-DwamO.

In normal operation, -0.9V is applied to the signal input terminal IN.
A normal logic level of /-L7V is applied, but when observing the leakage current characteristics of the memory cell of this example,
The same level as the voltage V1m of the power supply ■i+m is applied.

When the signal input terminal IN becomes the same level as Vllll, the output level of the reference voltage circuit 27 is first lowered via the diode Dd, and the holding current circuit 23. All constant current transistors of the R output current circuit 22 and the word driver circuit 24 are turned off.

As a result, the holding current Iwet of the memory cell array 21...
・iwna and wire setting current ro1. IDI...I
Since o, , I tin is turned off, it becomes easy and accurate to observe the leakage current characteristics of the memory cell.

On the other hand, the word line voltage fixing circuit 25 is turned on by the diode Dc connected to the signal input terminal IN. That is, when a normal logic level is input to the signal input terminal IN, the word line voltage fixing circuit 250 input transistor Qll is on and the output current Iw is zero, but the signal input terminal When IN becomes the same level as Vlm, transistor Qll is turned off and an output current w is generated. As a result of all the constant current transistors of the word driver circuit 24 being off, the output current Iw is equally divided into the diodes])wtl...Dwt@, and the output current Iw is equally divided into the word lines WTl...WTnt-Vcc. The potential is fixed to be lower by the forward voltage Vf.

In this state, a voltage Vc higher than Vcc is applied to the Vcc terminal 29.
When cm is applied, leakage current flows through the cell transistor W
r is fk<BVms, BVmc=3.5v! : then, t
EEVcc person is 3.5V+2XVf =3.5V+0.
8VX2=5. , IV, no current flows because the cell transistor does not break down. However, if there is a leakage current path in any one of the cell transistors, a current begins to flow at a voltage of Vccm equal to or higher than 2xVf = L6V. That is, Vccm terminal 29
It is sufficient to apply a voltage of approximately 2V, which is larger than 1.6V, to the VCCA terminal 29, detect the presence or absence of current flowing through the VCCA terminal 29, and determine whether the semiconductor memory is good or bad.

Further, in this embodiment, there is a method of applying a word address input signal without turning off the constant current transistor of the word driver circuit 24. In this way, one of the word lines WT1...WTn is selected according to this word address input signal.
Since only one word line is selected and has a high level, and the remaining ones are all low level, it is possible to selectively check the leakage current characteristics of only the memory cells on one word line.

Note that the semiconductor memory of the second invention is the circuit shown in FIG. 3 without the diode Dd, and since the holding current circuit and the readout current circuit cannot be turned off, the semiconductor memory consists of the holding current and the lead-out current. Leakage current of the memory cell is observed superimposed on the constant current. Therefore, although the accuracy is inferior to the semiconductor memory of the third invention, it is still possible to check the leakage current of the memory cell.

(Effects of the Invention) As described above in detail, the semiconductor memory of the present invention has the following features:
The decoupling diode connected between the highest potential terminal (Vcc) and the digit line and word line on the low potential side is connected to the word line voltage fixing circuit connected to the word line on the high potential side. If a transistor constituting a memory cell has a leakage current path, a current path is formed between the highest potential terminal and the lowest potential terminal (Via) via the diode and the memory cell with the leakage current path. Therefore, it is possible to easily test whether there is a memory cell having a leakage current path.

Further, the semiconductor memory of the present invention has the effect that leakage current paths can be checked more accurately by turning off the constant current transistor of the optical circuit and the read current circuit when the external control signal is used to hold the memory.

Therefore, according to the present invention, a highly reliable semiconductor memory that can detect even a slight leakage current in an electrical test in a wet state can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the first invention;
FIG. 2 is a current-voltage characteristic diagram between the word line WT and Vccm terminals in FIG. 1, and FIG. 3 is a circuit diagram showing a main part of an embodiment of the third invention. 11...Memory cell, 12...Vcc
a terminal, 21...Memory cell array, 22...
... Read current circuit, 23 ... Holding current circuit, 24 ... Word driver circuit, 25 ...
. . . Word line voltage fixing circuit, 26 . . . Internal circuit, 27 . . . Reference voltage circuit, 28 digit line, D1 to D3. DC, Dd, Dot, Dot.

Claims (3)

[Claims] (1) In a semiconductor memory in which memory cells constituting flip-flops whose bases and collectors are cross-connected to each other are arranged in a word line direction and a digit line direction, the highest potential terminal of the semiconductor memory and the digit line and the word line 1. A semiconductor memory comprising: a diode connected between a word line on a lower potential side and an anode on the highest potential terminal side. (2) In a semiconductor memory in which memory cells constituting flip-flops whose bases and collectors are cross-connected are arranged in a word line direction and a digit line direction, the highest potential terminal of the semiconductor memory and the digit line and the word a diode connected between the word line on the low potential side of the lines with its anode on the highest potential terminal side; and a diode connected to the word line on the high potential side of the word lines and the lowest potential terminal of the semiconductor memory. a high potential side word line voltage fixing circuit controlled by a control signal applied to a signal input terminal of the semiconductor memory. (3) In a semiconductor memory in which memory cells constituting flip-flops whose bases and collectors are cross-connected to each other are arranged in a word line direction and a digit line direction, the highest potential terminal of the semiconductor memory and the digit line and the word a diode connected between the word line on the low potential side of the lines with its anode on the highest potential terminal side; and a diode connected to the word line on the high potential side of the word lines and the lowest potential terminal of the semiconductor memory. a high-potential side word line voltage fixing circuit that is controlled by a control signal applied to a signal input terminal of the semiconductor memory; and a control that controls a holding current and a read current of a memory cell array of the semiconductor memory by the control signal. A semiconductor memory comprising a circuit.