JPH0528799A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To judge the presence or absence of the leak currents of the data input and output terminal of a memory cell by allowing a load transistor to be conductive or non-conductive according to the level of a load control signal. CONSTITUTION:On applying a power source when an inside writing control signal IWE is held to a low level, the load control signal LC of a load control circuit 5 is turned to the low level. Then, a pair of transistors TrQ41 and Q42 which input the signal LC to the gates are turned to a non-conductive state while the control signal IWE is held to the low level. When the signal IWE is turned to a high level, and a reading operation is started, a TrQ51 is turned ON, and the output of a flip flop constituted of inverters IV1 and IV2 is inverted. Then, the signal LC being the output signal of the circuit is turned to the high level regardless of the level of the signal IWE, and the TrQ41 and Q42 are always in the ON states. Thus, the presence or absence of the leak currents of the data input and output terminal N1 of a memory cell MC can be exactly judged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a static RAM type semiconductor memory device.

[0002]

2. Description of the Related Art Conventionally, in this type of semiconductor memory device, as shown in FIG. 4 as an example, a first transistor Q1 having a source connected to a ground potential point, a source connected to a ground potential point and a gate connected to a transistor Q1. A second transistor Q2 connected to the drain of the transistor Q1 and the drain connected to the gate of the transistor Q1, and a high resistance first load resistor connected to the drain of the transistor Q1 at one end and to the power supply end of the power supply potential Vcc. R1 and a high resistance second load resistor R2 having one end connected to the drain of the transistor Q2 and the other end connected to the power supply terminal, and the drains of the transistors Q1 and Q2 are connected to the first and second data input / output terminals. A plurality of flip-flop type memory cells MC (only one is shown) for receiving and storing data as N1 and N2 and outputting the stored data; First, second digit lines DL1, DL2 to form a plurality of pairs for transmitting data from the transmission and the memory cells of data to Luo memory cell MC (1
Only a pair), and a plurality of word lines WL (only one is displayed) for bringing a selected one of a plurality of memory cells MC into a selected state in response to an address signal.
The gate is connected to the corresponding word line WL and this word line W
A plurality of switching transistors Q3 for connecting the first and second data input / output terminals (storage nodes) of the memory cell MC and the corresponding first and second digit lines DL1 and DL2 when L is at the selection level. , Q4 (only one pair is shown), and transistors Q41 and Q42, which are diode-connected between one end of each digit line DL1 and DL2 and the power supply end and serve as load resistance of a circuit connected to the digit lines DL1 and DL2. A plurality of load circuits 4a (1
(Only circuit is shown), data buses DB1 and DB2 for transmitting write data and read data, and predetermined ones of digit lines DL1 and DL2 forming a plurality of pairs are selected to connect to the data buses DB1 and DB2. And a write circuit 1 for controlling the writing of data to the memory cell MC
And a read circuit 2 for controlling the reading of the data read from the memory cell MC.

In this semiconductor memory device, the word line W
When L becomes the selection level, the switching transistors Q3 and Q4 are turned on, and one of the digit lines DL1 and DL2 (for example DL
2) is low level and the other is high level.

The transistors Q1 of the normal memory cell MC
Since Q2 is smaller than the transistors Q41 and Q42 of the load circuit 4a, the on-resistances of the transistors Q1 and Q2 are larger than those of the transistors Q41 and Q42, and the low level digit line DL2 is not completely lowered to the ground potential (0V). . Therefore, when the read operation is completed, the word line WL becomes the non-selection level, the transistors Q3 and Q4 are turned off, and the low level of the digit line DL2 is charged to the same potential as the digit line DL1, the low level is 0V. Compared to the time, it can be charged more quickly. Therefore, the transistor Q forming the load circuit 4a
It is possible to obtain a static RAM type semiconductor memory device capable of operating at high speed by optimally designing the sizes of 41 and Q42, the timing of the selection level of the word line WL, and the timing of the non-selection level.

[0005]

In the conventional semiconductor memory device described above, the load resistances R1 and R2 of the memory cell MC are high, and the transistor Q4 of the load circuit 4a is high.
Since 1 and Q42 are diode-connected and have a predetermined ON resistance, the write circuit 1 causes the memory cell MC
When the current flowing in the write circuit 1 is measured by setting the data input / output terminals N1 and N2 of the data input / output terminals N1 and N2 to high level and low level to test the insulation state of the data input / output terminals N1 and N2, for example, the data input / output terminal N1 Even if there is a leakage resistance Rx between the ground potential point and the ground potential point, since there is a current flowing through the transistors Q41 and Q42, it is clarified whether there is an abnormal current due to the leakage resistance Rx and its value. There was a problem that it could be measured.

An object of the present invention is to be able to clearly determine and measure the presence / absence of a leak current at a data input / output terminal (storage node) of a memory cell, a leak current, etc., and to facilitate failure analysis and the like. It is to provide a semiconductor memory device.

[0007]

According to another aspect of the present invention, there is provided a semiconductor memory device in which first and second transistors having sources connected to a first power supply potential point and drains and gates cross-connected to each other, and one end of which is the first transistor The first and second load resistors of high resistance, which are respectively connected to the drains of the first and second transistors and use this connection point as a data input / output terminal and the other end thereof are both connected to the second power supply potential point, A plurality of memory cells respectively arranged in a matrix in the row direction and the column direction; a plurality of word lines for selecting these memory cells in a predetermined unit in the row direction at a selection level; and the plurality of memory cells A plurality of digit lines provided corresponding to memory cells of a predetermined unit in the column direction for transmitting read data and write data of the corresponding memory cells, and corresponding gates. A plurality of switching transistors which are connected to a word line and which bring the memory cell into a selected state by setting a conduction state between a data input / output terminal and a digit line of the corresponding memory cell when the word line is at a selected level; Data bus for transmitting write data to the memory cell and transmitting read data from the memory cell, and a data transfer circuit for selecting a predetermined one of the plurality of digit lines and connecting it to the data bus A write circuit and a read circuit for controlling transmission of write data to the selected memory cell and read data from the memory cell, and a load transistor and a load transistor, respectively, which are respectively connected to the respective digit lines. In a semiconductor memory device having a load circuit which becomes a load of a circuit connected to these digit lines And a load control circuit for generating a load control signal that maintains the first level when the power is turned on in the write state and becomes the second level when the power is first read out and maintains the second level. A configuration in which the load control signal controls a load transistor of the load circuit so as to be in a non-conductive state when the load control signal is at a first level and to be in a conductive state when the load control signal is at a second level. have.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment differs from the conventional semiconductor memory device shown in FIG. 4 in that a transistor Q51 for inputting an internal write control signal IWE (low level active) to the gate, inverters IV1 and IV2, and a capacitor. C
A load control circuit 5 for generating a load control signal LC which maintains a low level when the power is turned on in the write state and becomes a high level when the power is first read out and which maintains the high level. By providing the load control signal LC, the load transistors Q41 and Q42 of the load circuit 4 are provided.
Is controlled so that when the load control signal LC is at a low level, it is in a non-conductive state, and when it is at a high level, it is in a conductive state. Generation of such a load control signal LC can be easily realized by appropriately setting the sizes of the transistor Q51 and the transistors forming the inverters IV1 and IV2. The capacitors C1 and C2 are inserted for level stabilization.

Next, the operation of this embodiment will be described.
FIG. 2 is a waveform diagram of signals around the load control circuit 5 for explaining the operation of this embodiment.

The internal write control signal IWE is in phase with the external write control signal WE. When the power is turned on while the write control signal WE is at a low level, the internal write control signal IWE is turned on.
Since WE remains at the low level, the output signal of the load control circuit 5, that is, the load control signal LC is at the low level. Therefore, the pair of transistors Q41 and Q42 for inputting this control signal LC to the gate are the write control signals. WE and the internal write control signal IWE are in the non-conduction state (T
It becomes 1).

Next, when the write control signal WE and the internal write control signal IWE change from the low level to the high level and the first read operation starts, the internal write control signal IWE becomes the high level and the transistor Q51 is turned on. The output of the flip-flop formed by the inverters IV1 and IV2 is inverted, and the load control signal becomes high level.

Therefore, a pair of transistors Q41, Q42
Is turned on, and thereafter, the output signal of the load control circuit 5 and the load control signal LC continue to maintain the high level regardless of the level of the write control signal WE.
1, Q42 is always on (T2).

Therefore, when the write control signal WE is kept at the low level, that is, when the power is turned on in the written state, the transistors Q41 and Q42 are in the non-conducting state until the first reading is started. Within that period (T1),
When the memory cell MC is defective due to the leakage current from the data input / output terminal N1 of the memory cell MC to the abnormal ground potential point, the digit line DL2 is forced to 0V, DL1 in the memory cell MC. When writing is performed by setting Vcc to Vcc, the transistor Q41 is non-conductive, so that there is no current flowing from the transistor Q41 to the ground potential point through the transistor Q3 and the leak resistance Rx that causes the defect. Further, no current flows from the transistor Q42 to the writing circuit 1. Therefore, the current flowing like a direct current is only through the leak resistance Rx, which is the cause of the defect, and the defect analysis becomes easy. An abnormal leak current does not flow in a good memory cell.

Next, when the first read operation is started, the transistors Q41 and Q42 continue to maintain the conductive state regardless of the level of the write control signal WE. That is, the static RAM capable of high-speed operation described in the related art
It becomes the operation of.

On the other hand, when the power is turned on while the write control signal WE remains at the high level, the load control signal LC continues to be at the high level regardless of the write control signal WE. That is, the operation at this time is the same as the operation described in the related art.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, the data buses DB1 and DB2 are
It is applied when a load circuit is also connected,
The transistors Q61 and Q62 of the load circuit 6 connected to the data buses DB1 and DB2 also have the load control signal LC.
It is controlled by. Since the basic operation and effect are the same as those in the first embodiment, they will be omitted.

[0020]

As described above, the present invention is provided with a load control circuit which generates a load control signal which becomes the first level when the power is turned on in the write state and the second level when the first read operation is performed. By controlling the transistor of the load circuit by the load control signal so that it is turned off when the load control signal is at the first level and turned on when the load control signal is at the second level, the transistor of the load circuit is turned off. At this time, when the data input / output terminal of the memory cell is forcibly set to the high level and the low level and the current flowing through the data input / output terminal is measured, this current is only the leak current, so that failure analysis and the like become easy. There is an effect.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform diagram of signals around a load control circuit for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional semiconductor memory device.

[Explanation of symbols]

1 Write Circuit 2 Read Circuit 3 Data Transfer Circuit 4, 4a Load Circuit 5 Load Control Circuit 6 Load Circuit C1, C2 Capacitor DB1, DB2 Data Bus DL1, DL2 Digit Lines IV1, IV2 Inverters Q1 to Q4, Q31, Q32, Q41, Q42, Q5
1, Q61, Q62 Transistors R1, R2 Load resistance WL Word line

Claims (2)

[Claims] 1. A first and a second, both sources of which are connected to a first power supply potential point and whose drain and gate are cross-connected to each other.
And a high-resistance transistor whose one end is connected to the drains of the first and second transistors, respectively, and the connection point is used as a data input / output terminal, and the other end is connected to the second power supply potential point. A plurality of memory cells each having a first load resistance and a second load resistance and arranged in a matrix in a row direction and a column direction, and a plurality of words for selecting these memory cells in a predetermined unit in the row direction at a selection level. Lines and,
A plurality of digit lines provided corresponding to a predetermined unit of memory cells in the column direction of the plurality of memory cells and transmitting read data and write data of these corresponding memory cells, and a gate are connected to the corresponding word lines. When the word line is at the selected level, a plurality of switching transistors for bringing the memory cell into the selected state by electrically connecting the corresponding data input / output terminals and digit lines of the memory cell, and the selected memory cell. A data bus for transmitting write data to and reading data from the memory cell, and a data transfer circuit for selecting a predetermined one of the plurality of digit lines and connecting it to the data bus. Write for controlling transmission of write data to the memory cell and read data from the memory cell And road and readout circuit, in connected in correspondence with each of the respective digit line comprises a transistor for load semiconductor memory device having a load circuit comprising a load circuit connected to these digit lines,
A load control circuit is provided that generates a load control signal that maintains a first level when the power is turned on in the written state and a second level when the first read state occurs and which maintains the second level. The load control signal causes the load transistor of the load circuit to receive the first load control signal.
The semiconductor memory device is controlled so as to be in a non-conducting state at a level of 2 and a conductive state at a second level. 2. The semiconductor memory device according to claim 1, wherein the load control circuit is formed of a flip-flop circuit.