JPS61137295A - Semiconductor memory integrated circuit - Google Patents

Abstract

PURPOSE:To shorten inspection time and to obtain high reliability by connecting one or more word lines through a minimum potential power supply line and an ohm element and connecting one or more emitters which are respective storage units through the series connection of a maximum potential power supply line and the ohm element or that of the ohm element and a diode. CONSTITUTION:A storage circuit based upon a flip flop circuit obtained by crossing and coupling the bases and collectors of two bipolar transistor (IRs) constitutes one unit, plural storage units C are arranged almost straight so as to form a string by connecting the ends of the load elements of the collector side of a common word line WTi and plural strings are arranged almost in parallel to form the matrix of the storage units C. The word line WTi which is the high potential side end of the storage units C is connected to a minimum potential power supply VEE with high resistance RTi which may not interrupt the usual operation and a word bottom line WBi which is the low potential side end is connected to a maximum potential power supply VCC with high resistance RBi which may not interrupt the usual operation. If a current leakage is generated in any one of TRs constituting the storage unit C, the leakage can be directly observed between the external terminals VCC and VEE.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor memory integrated circuits.

[Conventional technology]

Semiconductor memory integrated circuit (hereinafter referred to as Memo IJIC)
The degree of integration is becoming more and more important, and the reliability is also required to be higher and higher.

Generally, when testing a memory IJIc, it is checked that normal operation is performed between one bit and all other bits, and this is done for all pits, so the number of tests for an N-bit memory is proportional to N2. . Therefore, as the scale of the memory IC increases, the time required for inspection increases rapidly, and the efficiency of using expensive measuring equipment deteriorates. For this reason, it is desired to shorten the inspection time.

On the other hand, since testing of memory ICs is generally performed using external terminals, especially in memory ICs whose basic storage unit is a flip-flop circuit made of bipolar transistors, there may be some leakage or other problems in the elements that make up the storage unit. Even if there is deterioration, it often appears to be operating normally. Over time, "some deterioration" becomes "major deterioration"), and there is a danger that it may cause malfunction. Therefore, in order to achieve high reliability, it is necessary to detect and eliminate such memorandums with "slightly deteriorated" elements.

[Problem that the invention seeks to solve]

However, conventionally, memory ICs that satisfy the above requirements have been developed.
has not been realized. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory integrated circuit which can shorten the testing time of the semiconductor memory integrated circuit and provide high reliability.

[Failure to solve the problem]

In the semiconductor memory integrated circuit of the present invention, one unit is a memory circuit based on a flip-flop circuit in which the bases and collectors of two bipolar transistors are cross-coupled with each other, and this memory unit connects the end of a load element on the collector side. A semiconductor memory integrated circuit including a matrix of storage units connected to a common word line and arranged in a substantially straight line to form a plurality of columns, the plurality of which are arranged substantially parallel to each other, One or more word lines are connected to the lowest potential power line via an ohmic element, and one or more of the emitters of the memory units are connected to the highest potential power line and an ohmic element, or an ohmic element and a diode. are connected in series.

[Effect]

FIG. 1 is a circuit diagram showing the basic configuration of the memory IJIC of the present invention, which is a 64×64 4096-bit bipolar memory with 1 output.

One prefecture is a memory circuit based on a flip-flop circuit in which the bases and collectors of two bipolar transistors are cross-coupled with each other, and this memory unit C connects the end of the load element on the collector side to a common word line WTl. A plurality of them are connected and arranged in a substantially straight line to form a column, and several 4i columns are arranged in substantially parallel to form a matrix of storage units C. In Fig. 1, WBl is word bottom &, DL+DRI is digit line%, Qw+ is word driver transistor, ■Ll v ■R1e Engineering H1
is a constant current source.

Here WT, , J). The subscript i of 3rd grade is 1-O2...
・, means 63.

Then, the word line WT, which is the high potential side end of the memory unit C,
is a high-resistance TI that does not disturb normal operation and is connected to the lowest potential power supply ■.The word bottom line WBl, which is the end on the low-potential side, is also a high-resistance Ru that does not disturb normal operation.
+ is connected to the highest potential power supply VCC.

Unfortunately, if there is a leak in even one of the transistors that make up the memory unit C, the external terminal ■. Leakage can be directly prevented between C and terminal V. Leakage often occurs between the emitter and base or emitter and collector of transistors.

Highest potential power supply V. C and the lowest potential power supply■]i,. A peripheral circuit that is not suitable for normal operation is connected between the terminal and the terminal, but current does not normally flow in this peripheral circuit until the diode forward voltage (hereinafter referred to as ■2) is approximately 0.7V. There is. Therefore, the terminal ■. Between C and terminals VF and E, ■2
If a very low voltage is applied, only leakage from the memory element can be observed.

Furthermore, as shown by the dotted line in FIG.
By connecting to TT, the number of resistive elements can be reduced.

In this case, the leakage of the memory unit C will be observed by applying a voltage (for example, 1.OV) higher than the F1 stage, so it is necessary to prevent current from flowing in the peripheral circuits up to the VF6 stage (approximately 14 V). There is.

〔Example〕

FIG. 2 is a circuit diagram showing one embodiment of the present invention.

This embodiment is a bipolar memory with 4096 bits and 1 output.The basic circuit is the same as that shown in Fig. 1 used for explanation, and the resistor R
It is the same as the conventional one except for Tl t "Bi.

The matrix configuration of memory unit C is 64×64, and the holding current for memory unit 01 is 10 μA1. Therefore, the current for 1 word is 640 μA.

In this embodiment, 20 μA is applied to the resistor RBl so that the holding current does not change significantly due to fluctuations in the power supply voltage. Therefore, the constant current source IH in the circuit diagram is set to 660μA, and the resistor RB is set to 150Ω.
shall be.

In this embodiment, in order to make the potential of the word line WTl fall steeply, the word line discharge circuit is arranged so that the word line Hw
T, and the word bottom line WB1.

Here, the resistance RTl on the word, 13'w T, side is:
A resistor 1 is connected between the word line WTI line in this word line number circuit and the lowest potential power source Vya. Resistor RD2
Reuse the series connection of 1.

The peripheral circuit is the same as before, and the voltage between the power supply terminals is one step of vF (
Current does not flow below approximately n, 7 V').

Figure 3 (a) shows the voltage between terminal VCC and terminal ■ F, F.
-Characteristics under current conditions are shown. The normal operating range is 4.0V to 5.5V. FIG. 3(b) shows an enlarged view of the vicinity of Ov.

The case where there is no leak in the storage unit C is shown by a solid line, and the case where there is a leak is shown by a dotted line. In the case of the dotted line, it is not known whether it is between the emitter-pace or between the emitter-collector of the transistor, but it can be seen that there is a leak in the transistor of one of the memory units C.

〔Effect of the invention〕

As described above in detail, in the semiconductor memory integrated circuit of the present invention, the total leakage of each element constituting a storage unit can be directly observed from the external terminal. That is,
If there is a leak in even one bit, the leak can be observed from the outside, so it can be immediately determined that the product is defective. Therefore,
According to the present invention, the inspection time can be significantly reduced compared to the conventional method of inspecting each bit one by one. Furthermore, since the magnitude of leakage is directly determined, it is possible to eliminate elements that are "slightly deteriorated" which is undesirable in terms of reliability, and it is possible to improve the reliability of the product.

[Brief explanation of drawings]

FIG. 1 is a basic diagram of a semiconductor memory integrated circuit according to the present invention. C... Memory unit, D... Word line discharge circuit %DROIDR63, DLo, DL63...
・Digital line, ■D. ,■Ho. lH63g ■LOg ■L63 + ■ROH1H6
1+'...- Constant current source, Qwo. QW63...Word driver transistor, 几B. , RB63゜RDIOg “D20 +”TO
+ ”TO3t ”TT”'”'Resistance s TTo +
TT 63... Decoupled diode, v
cc...Group, highest potential power supply line and its external terminals VE
.・・・・・・Lowest potential power line and its external terminal, WB
o, WB 63...Ward bottom a, W
TO, WT63...Word line. cough 3 diagram

Claims (1)

[Claims] One unit is a memory circuit based on a flip-flop circuit in which the bases and collectors of two bipolar transistors are cross-coupled with each other. In a semiconductor memory integrated circuit including a matrix of memory units arranged in a straight line to form a column, the plurality of columns being arranged substantially parallel to each other, one or more of the word lines is a lowest potential power supply line. and are connected through an ohmic element,
A semiconductor memory integrated circuit characterized in that one or more of the emitters of the memory unit is coupled to the highest potential power supply line by an ohmic element or a series connection of an ohmic element and a diode.