JPS601720B2 - semiconductor memory - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides a structure of a semiconductor memory that can measure the operating margin of a memory chip at a power supply voltage different from the power supply voltage and obtain a semiconductor memory with stable operation. It is related to.

[Background of the invention]

Conventionally, a common method for determining whether a semiconductor circuit chip is good or bad is to change the power supply voltage and measure the so-called operating margin for the power supply voltage, which is the range of power supply voltage within which the circuit chip can operate normally. It is widely used to measure

For example, in a static semiconductor memory that has a memory array consisting of a large number of flip-flop type memory cells, if a power supply voltage that is varied by a predetermined value from the specified value is applied, and a memory cell that malfunctions under that condition is discovered. The memory chip can be regarded as a defective product with a low operating margin and removed. However, due to some kind of noise contamination in the semiconductor memory mentioned above,
The reality is that memory cells with low operational stability, where information is easily destroyed, cannot be effectively discovered using the above methods alone, and are often discovered only after pulse response testing. Ta.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory whose operational stability can be easily checked during a functional test.

[Summary of the invention]

The present invention is based on an information retention current that is constantly passed through each memory cell in a static semiconductor memory. This was done in view of the fact that changing the value of is effective in determining the stability of motion.

The feature is that the current value for information retention is set to a predetermined value necessary for normal operation when no external signal is given, and when the signal is given from the outside, it responds to the low signal. This is because we have provided a means for determining the value. [Embodiments of the Invention] Examples of the present invention will be described below with reference to the drawings.

In the drawing, a memory cell 20 is constituted by a flip-flop circuit consisting of two multi-emitter transistors whose collectors and bases are cross-connected to each other, and a resistor. Such memory cells are arranged vertically and horizontally to form a cell array, and each row is connected to two data lines 21 and 32. Each data line is connected to a reference potential generation circuit 23.
is connected to the emitter of a transistor whose base potential is fixed. On the other hand, an upper word line 29 and a lower word line 30 are provided for each row of the cell array, and the upper word line 29 is set at a predetermined potential depending on whether it is selected or not.
On the other hand, a current limiting circuit 33 is connected to the lower word line. A potential signal output from the internal power supply potential generation circuit 24 is connected to the base of the transistor of the current limiting circuit 33, and the information holding current in this memory cell row is controlled to a predetermined value by this potential signal. Note that similar current limiting circuits are provided in other rows (not shown) in the cell array, and the current for holding information is controlled for each memory cell row. With the above structure, a current for information retention flows almost equally through each memory cell, and the information of each bit is retained as long as the power supply voltage is connected.

However, it is unavoidable in manufacturing that defective bits will occur stochastically, such as in memory cells where a specified information retention current is not distributed due to some defect. These defective bits include defects that cause trouble during product inspection, such as bits that operate normally during inspection but whose information is extremely susceptible to destruction due to the introduction of some kind of noise. An effective way to identify such defects is to vary the information retention current and check the operating margin for it. Here, 25 and 26 are high potential common terminals, 27
is a low-potential common terminal, during which a power supply voltage is applied from outside the chip.

Internal power supply voltage generation circuit 24 generates a potential signal whose potential difference with low potential common terminal 27 is compensated for fluctuations in power supply voltage and remains substantially constant. Therefore, simply changing the external power supply voltage will hardly change the information retention current flowing through each memory cell, making it impossible to confirm the operating margin of the memory cell with respect to the information retention current.
Therefore, in this embodiment, a pad 34 is provided on the aluminum wiring of the output portion of the internal power supply potential generation circuit 24 to apply a voltage from the outside using a needle or the like. If such a pad is used, a specified external voltage can be applied to the pad to which the high potential and low potential common terminal bins are connected, and the output potential of the internal power supply potential generation circuit 24 can be applied to the pad 34. By checking the operation of the memory cell by forcing a change from , it is possible to check the operational margin of the memory cell against changes in the information holding current. Moreover, this confirmation can be carried out by sequentially contacting the circuits with the wafer after the circuits are formed on the wafer, before the memory chips are packaged, making it possible to quickly and efficiently extract defective memory chips. . [Effects of the Invention] As described above, according to the present invention, a configuration is provided in which semiconductor memories with stable operation can be easily selected.

Further, although the description has been made using a bipolar memory, the present concept can be applied to any static type memory in which an information retention current is passed through the memory cell to store information.

[Brief explanation of drawings]

The drawing is a circuit diagram showing an embodiment of the present invention. 20...Memory cell, 24...Internal power supply potential generation circuit, 33...Fin flow restriction circuit, 34...Pad.

Claims (1)

[Claims] 1 A flip-flop type memory cell, and when a certain signal is not applied from outside the chip, an information retention current of a predetermined value necessary for normal operation is supplied to the memory cell, and when the certain signal is applied from outside the chip, A semiconductor memory characterized in that it is provided with means for changing an information holding current to a value other than the predetermined value in accordance with the signal.