JPS6190399A - Input circuit part of mos type memory ic - Google Patents

Abstract

PURPOSE:To detect easily whether a terminal bonding of respective memory chips which are commonly connected is good or bad by providing/incorporating an input current test circuit which is controlled to be conductive or nonconductive in accordance with an external control signal. CONSTITUTION:A signal (0) is impressed on a chip selector terminal 13 of a subject chip 101, etc., out of memory chips 101-10n to which an input terminal 11 is commonly connected, and a signal (1) is impressed on the terminal 13 of another chip. Then only the input current test circuit 12 provided and incorporated in the chip 101 becomes conductive, and circuits of the other chips stay nonconductive as they are. Whether the connection of the terminal 11 of the chip 101 is good or bad is decided by a voltmeter 14 or ammeter 15 in terms of a DC current from the circuit 12 of the chip 101, and whether the input terminal bonding of each memory chip which are commonly connected is good or bad can be easily detected.32: input gate, 34: input protection.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit (IC).
The present invention relates to an input circuit section of a MOS type memory integrated circuit applied to each memory chip of a memory module housed in a four-channel memory module.

[Technical background of the invention]

Recently, memo IJIc in the application system of memory IC
For the purpose of improving the packaging density of a memory module (for example, a 64K x 1 bit configuration) in which a plurality of memory chips 27' (for example, a 64K
KX4 pit configuration) has been developed. Such a memory module (hybrid memory) is composed of a plurality of memory chip halves each having the same configuration as shown in FIG.
are housed in one 9-bit memory chip, and some of the signal terminals (address terminals, read/write control terminals) of each memory chip'f11 to 1n are commonly connected between chips. The corresponding external input terminals (address terminals, read/write terminals) of the package
It is connected to the. Also, each memory chip 7°11~1n
Signal terminals (for example, data input terminals, data output terminals, chip selection terminals, etc.) used independently for each package are individually connected to the corresponding external terminals (data input terminal D
I0~DIj, 7'-ta output terminal DOo """Oj,
chip selection terminal csO-C8N, etc.).

FIG. 4 shows a part of a conventional MO3 type memory chip, and protects input dirt circuits 32 such as in/output terminals that receive signal input from input terminals 3 for each valley input terminal. Therefore, normally a protection resistor 33 is inserted in series in the input signal path, and an input protection circuit 34 is provided between the input signal path and the ground terminal.

[Problems with background technology]

By the way, in the manufacturing process of memory modules as mentioned above, it is necessary to detect and replace defective chips.
As part of the test process, it is necessary to check whether the wire ending connection between each terminal group of the memo IJ ffz1 to 1n and the notebook external terminal is well established (dangling open state). be. In this case, for the signal terminals used independently on each chip, a DC voltmeter is connected to the corresponding external terminal.
By connecting a DC ammeter, it is possible to determine whether or not the Dending connection is good or not based on whether or not current flows through the terminal. On the other hand, regarding input terminals that are commonly connected between chips, if one (or multiple) chip's input terminal has poor binding and the remaining chips' input terminals have good binding, Since current flows through the input protection circuit 34 through a good input terminal, it is difficult to detect the presence or absence of a defective chip and to detect a defective chip. Therefore, in order to analyze the failure mode of the chip input terminal, a considerable amount of effort is required, including a visual check using a microscope, etc., and it has been impossible to automate the analysis. In addition, it is possible to detect defective chips by performing a functional test on the chip.
Ching! It was difficult to determine whether it was a malfunction of the device itself or a faulty terminal connection as described above.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it detects whether the electrical connection between the MO8 type memory chip constant terminal and the external terminal for the external terminal is defective (open state) or the chip function is defective. It can be identified that predetermined terminals of multiple memory chips are commonly connected and housed in one package.
A defective chip 7 in which the electrical connection between the external terminal of the package and the common connection terminal of the above chip is open when
``Provides an easily detectable input circuit for MO8 type memory integrated circuits.

[Summary of the invention]

Specifically, the input circuit section of the MO8 type memory integrated circuit of the present invention is connected to a predetermined input terminal of the MO8 type memory chip, and connects the input terminal and a predetermined potential end according to a control signal from outside the chip. The present invention is characterized in that it includes an input current test circuit that controls conduction and non-conduction between the two.

Therefore, by controlling the input current test circuit to a conductive state by the above control signal and applying a predetermined DC voltage to the input terminal, the connecting connection between the input terminal and the external terminal of the integrated circuit/main circuit is established. Since the presence or absence of a current path is determined depending on whether the soldering is good or bad, it is possible to easily detect whether the soldering is good or bad.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a part of an IC chip 10 of an MO8 type memory, and 11 is an input terminal (ponding pad).
One of them (for example, for an address signal) is shown as a representative, and 32 is an input dart circuit (for example, an inverter) that detects the input signal from the input terminal 11, and 33 is a circuit that connects the input terminal 11 and the input signal from the input terminal 11. A protection resistor 34 is inserted in series in the input signal path between the input circuit 32 and the input circuit 32.
- This is a human power protection circuit provided between the input terminal of the circuit 320 and the ground terminal.

Furthermore, in the present invention, an input terminal test circuit 12 is added within the chip. This test circuit 12 is an N-channel delsion type (D type) MO8 field effect in which the r-to-source is connected between the input terminal (input node of the protection resistor 330) 11 and the ground terminal. Transistor (F
ET) Ql Oyohi N channel enhancement type (
The drain and source of the E-type MOS FET Q2 are connected in series, and the output end node of the protective resistor 33 and V. N-channel E W MO8FET between C power supply terminal
The drain and source of Qs are connected, and this FETQs
The dart is connected to the connection point node N of the FET QI and C2. The date of the FETQ2 is connected to the chip selection (C8) terminal (7I?nding node) 13 of the chip.

In addition, in the above-mentioned chip, input current test circuits as described above are individually provided and added to input terminals other than the input terminal 11 among the input terminal group as necessary.

The above-mentioned memory chip becomes a device by connecting the input terminal 11, C8 terminal 13, etc. to the external terminal of the package by wire bonding, and then performing a bonding process.

゛Now, when performing a DC test in the final test of the above device, if the 11# level is applied to the chip select terminal of the external terminals, the input current test circuit 1
Since FET 2 (h) is turned on and FETQs is turned off, it does not have any effect on the input terminal 11 where the above DC test is performed.

If the result of this DC test is defective, the input terminal 11
In order to check whether there is a binding connection failure (open state) of the
When the 0# level is applied, the input current test circuit 12
C2 turns off.

Therefore, V is applied to the external input terminal corresponding to input terminal 11. c.
+v□, by applying a DC voltage higher than (threshold voltage of FETQs), if there is no connection failure in the input terminal 11, a current will flow through the input current test circuit 120FETQs, and if there is a connection failure, the current will not flow. It is possible to detect whether the connection of the input terminal 11 is good or bad.

Furthermore, when the memory chip shown in FIG. 1 is used in a memory monolayer as described above with reference to FIG. 3, input terminals (U -1'/write terminal, The input current test circuit 12 is provided corresponding to each address terminal (address terminal). This kind of memory chip fl
When manufacturing the memory monoyl using OF, in the test process before testing to check for defective bonding connections of the commonly connected input terminals of each chip, it is possible to check each chip one by one. That is, as shown in Fig. 2, for a specific chip 7'ol to be checked, the ε1 terminal is given the "0" level from the external terminal for the chisel, and the remaining chips are For each chip, the °1# level is applied to each terminal from the external terminal. As a result, in each of the remaining chips, each input current test circuit 12 is turned off as described above, so the input current is not affected, but the input terminal (for example, 1) of the particular chip ), when a DC voltage of vcc+vTH3 or more is applied to the input terminal 1, as described above, if the bonding connection of input terminal 1 is good, the input current flows to the input current test circuit 12, and if the binding connection is bad, the input current flows to the input current test circuit 12. does not flow. Therefore, from this, it is possible to sequentially check the quality of the bonding connection for each of the commonly connected psychological input terminals of each chip. Note that 14 is a DC voltmeter, and 15 is a DC ammeter.

〔Effect of the invention〕

As described above, according to the input circuit section of the MO8 type memory integrated circuit of the present invention, it is possible to easily determine whether the binding is good or bad for a predetermined terminal of a memory chip. It is possible to easily detect whether the binding is good or bad for the commonly connected signal terminals for each flicker.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the input circuit section of an MO8 type memory integrated circuit according to the present invention, FIG. 2 is a circuit diagram showing a bonding quality test state of a memory module according to an application example of the present invention, and FIG. FIG. 4 is a configuration explanatory diagram showing an example of a memory module, and FIG. 4 is a configuration explanatory diagram showing an input circuit section of a conventional MO8 type memory integrated circuit. 10.101~lOn...MO8 type memory chip 1
1... Input terminal, 12... Input current test circuit, 13
...Chig selection terminal, 32...Input f-) circuit, 3
3...Resistor, 34...Input protection circuit, Q1~Q3・
...MOS FET. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (2)

[Claims] (1) An input that is connected to a predetermined input terminal in a MOS memory integrated circuit chip, and conduction or non-conduction between the input terminal and a predetermined potential end is controlled in accordance with a control signal from outside the chip. An input circuit section of a MOS type memory integrated circuit, characterized in that it has a current test circuit and is capable of conducting a continuity test between the input terminal and an external terminal of an integrated circuit package. (2) A plurality of the MOS type memory integrated circuit chips are one
A part of the input terminals of each chip is commonly connected to each other, and a control signal is applied individually from the package external terminal to the input current test circuit of each chip. An input circuit section of a MOS type memory integrated circuit according to claim 1, characterized in that: