JPS6350800B2 - - Google Patents
Info
- Publication number
- JPS6350800B2 JPS6350800B2 JP58030289A JP3028983A JPS6350800B2 JP S6350800 B2 JPS6350800 B2 JP S6350800B2 JP 58030289 A JP58030289 A JP 58030289A JP 3028983 A JP3028983 A JP 3028983A JP S6350800 B2 JPS6350800 B2 JP S6350800B2
- Authority
- JP
- Japan
- Prior art keywords
- mosfet
- memory device
- redundant
- redundant bit
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 230000002950 deficient Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/006—Identification
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
【発明の詳細な説明】
本発明は冗長ビツトの検出手段を有するメモリ
ー装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device having redundant bit detection means.
メモリー装置、特にMOS型メモリー装置は高
集積化が進行しそのチツプサイズも増大の一途で
ある。このチツプサイズの増大は製造中に発生す
る欠陥によつてその収率の悪化を持たらすもので
ありコスト的に考えると最適なチツプサイズが存
在しここが高集積化の妨げとなつている。この点
の打開策として登場したのが冗長ビツト構成を有
するメモリー装置である。即ちメモリー装置内部
にある予備メモリー群で欠陥等で動作できなくな
つたメモリー群又はメモリー素子を置き換えて見
かけ上完全品と同等に動作できる能力を有するの
である。しかしながら冗長ビツトによる救済メモ
リー装置にはあくまで欠陥ビツト群を内在させて
いる為にこれによりメモリー装置の信頼度低下が
懸念され、こうした冗長ビツト付メモリー装置の
実用化が進まない一因になつている。 Memory devices, especially MOS type memory devices, are becoming more highly integrated and their chip sizes are also increasing. This increase in chip size deteriorates the yield due to defects occurring during manufacturing, and from a cost standpoint there is an optimum chip size, which is an obstacle to higher integration. A memory device with a redundant bit structure has emerged as a solution to this problem. In other words, it has the ability to replace a memory group or memory element that has become inoperable due to a defect or the like with a spare memory group inside the memory device so that it can operate as if it were a perfect product. However, since the rescue memory device using redundant bits contains a group of defective bits, there is a concern that this will reduce the reliability of the memory device, and this is one reason why such memory devices with redundant bits are not being put into practical use. .
一方、現在は冗長ビツトが使われているか否か
は製品のテストだけでは判明しないし、それを知
る為にはその製品を開封し顕微鏡等で目視チエツ
クしなければならない。これは極めて非効率的で
あり実用的手法とは言えない。 On the other hand, it is currently not possible to determine whether redundant bits are used or not just by testing the product; to find out, it is necessary to open the product and visually check it using a microscope or the like. This is extremely inefficient and cannot be called a practical method.
本発明は冗長ビツト構成のメモリー装置にあつ
て冗長ビツトの使用の有無、さらに欠陥ビツトの
位置を電気的に検出可能にする方法を提供するも
のである。 The present invention provides a method for electrically detecting whether redundant bits are used and the position of defective bits in a memory device having a redundant bit configuration.
本発明によれば通常の動作状態では何らの影響
も与えずにある特殊な条件下に於てのみ外部入力
端子に電流が流れる事により冗長ビツトを使用し
ている事を検知でき、その時のアドレス入力によ
つてその欠陥ビツトの位置をも判定できるのであ
る。 According to the present invention, it is possible to detect the use of redundant bits by causing current to flow to the external input terminal only under certain special conditions, without causing any influence under normal operating conditions, and to detect the use of redundant bits at that time. The position of the defective bit can also be determined based on the input.
以上本発明による冗長ビツト検出回路の動作に
ついて第１図に基づいて説明する。第１図に於て
１は入力端子であり、７及び１６は各々Vcc端
子、出力端子である。5V系のメモリー装置では
Vccは5.5V〜4.5Vで使用され、入力端子は6V〜
−1V程度の範囲で使用される。アドレス入力１
４が冗長ビツトを選択していない時は冗長ビツト
ワード線１０はLOWレベルなのでMOSFET３は
非導通状態であり入力端子１からは何らの電流も
流れない。又、冗長ビツトワード線１０が選択さ
れても入力電圧が−1V〜6Vの範囲では
MOSFETのしきい値が0.8V程であればMOSダ
イオード２〜２″を導通させる事はできない。こ
の様に通常動作モードでは入力端子１はハイイン
ピーダンス状態を維持できる。 The operation of the redundant bit detection circuit according to the present invention will be described above with reference to FIG. In FIG. 1, 1 is an input terminal, and 7 and 16 are a Vcc terminal and an output terminal, respectively. In 5V memory devices
Vcc is used from 5.5V to 4.5V, and the input terminal is from 6V to
Used in a range of around -1V. Address input 1
When the redundant bit word line 4 is not selected, the redundant bit word line 10 is at a low level, so the MOSFET 3 is in a non-conducting state and no current flows from the input terminal 1. Also, even if redundant bit word line 10 is selected, if the input voltage is in the range of -1V to 6V,
If the threshold value of the MOSFET is about 0.8V, the MOS diodes 2 to 2'' cannot be made conductive.In this way, the input terminal 1 can maintain a high impedance state in the normal operation mode.
一方、冗長ビツトの位置を知りたい時には入力
端子１に8V以上例えば10Vの電圧を印加させる。
この状態ではMOSダイオード２〜２″は導通状態
になつている。しかしMOSFET３は依然として
非導通であるので入力端子１は相変らずハイイン
ピーダンスとなつている。もしここで冗長ビツト
が選択されるとワード線１０はHIGHレベル即ち
Vccレベルへ昇圧されてMOSFET４を通して
MOSFET３のゲートを充電する。しかしこの電
位ＡはVccのVT一段分低い電圧なのでブート容
量５によりワード線６よりも遅くHIGHレベルに
なる信号、例えばセンス信号等により昇圧されて
Vccよりも高くＡの電位は約8V程になつて
MOSFET３は導通し入力端子１よりVccに対し
て電流が流れる事になる。そして冗長ワード線１
０が非選択の場合MOSFET３のゲートは充電さ
れないので信号６に無関係にMOSFET３は導通
できず入力端子１から電流が流れる事はない。 On the other hand, when it is desired to know the position of the redundant bit, a voltage of 8V or more, for example 10V, is applied to the input terminal 1.
In this state, MOS diodes 2 to 2'' are in a conductive state. However, since MOSFET 3 is still non-conductive, input terminal 1 remains at high impedance. If the redundant bit is selected here, Word line 10 is at HIGH level, i.e.
Boosted to Vcc level and passed through MOSFET4
Charge the gate of MOSFET3. However, since this potential A is one stage lower than Vcc by V T , it is boosted by a signal that goes HIGH later than the word line 6 due to the boot capacitor 5, such as a sense signal.
The potential of A is higher than Vcc and becomes about 8V.
MOSFET 3 becomes conductive and current flows from input terminal 1 to Vcc. and redundant word line 1
When 0 is not selected, the gate of MOSFET 3 is not charged, so MOSFET 3 cannot conduct regardless of signal 6, and no current flows from input terminal 1.
この様に本発明によれば外部より入力端子の一
部にVccよりも数Ｖ高い電圧を印加し、その端子
に流れる電流を検出しその時のアドレス入力を調
べる事により冗長ビツトの使用有無及びその欠陥
ビツトの位置を検出できる。この電流の検出レベ
ルはMOSFET２，３の大きさを調整できるので
般用のICテスターで充分に検出可能である。又、
基準電位線７がVccでなくVssであつても
MOSFET２の段数を適当に選択する事ができる
ので本発明は可能でありこの時にはブート容量５
はいらずMOSFET４も省く事ができる。又、本
発明の回路ブロツクは第２図の如き実施例にても
おきかえ可能であり節点Ａはブート容量５を介し
て信信１０により制御される。 As described above, according to the present invention, by applying a voltage several volts higher than Vcc to some of the input terminals from the outside, detecting the current flowing through that terminal, and checking the address input at that time, it is possible to determine whether redundant bits are used or not. The position of defective bits can be detected. Since the detection level of this current can be adjusted by adjusting the size of MOSFETs 2 and 3, it can be sufficiently detected with a general IC tester. or,
Even if the reference potential line 7 is Vss instead of Vcc
The present invention is possible because the number of stages of MOSFET2 can be appropriately selected, and in this case the boot capacity is 5.
MOSFET4 can also be omitted. Further, the circuit block of the present invention can be replaced with the embodiment shown in FIG.
以上記述した如く本発明は冗長ビツトを有する
メモリー装置において、簡単に冗長ビツトの使用
の有無、その番地を判定できる。 As described above, in a memory device having redundant bits, the present invention can easily determine whether the redundant bit is used and its address.
第１図、第２図は各々本発明実施例の部分回路
図である。
なお図において、１……入力端子、２〜２″…
…MOSダイオード、３，４……MOSFET、５…
…ブート容量、６……ブートup信号、７……
Vcc、８……メモリアレイ、９……冗長メモリア
レイ、１０……冗長ビツト選択ワード線、１１…
…メモリアレイワード線、１２……入力増幅器、
１３……デコーダー、１４……アドレス入力端
子、１５……出力増幅器、１６……出力端子、１
７……本発明による回路ブロツク、である。
1 and 2 are partial circuit diagrams of embodiments of the present invention. In the figure, 1...input terminal, 2~2''...
...MOS diode, 3, 4...MOSFET, 5...
...Boot capacity, 6...Boot up signal, 7...
Vcc, 8...Memory array, 9...Redundant memory array, 10...Redundant bit selection word line, 11...
...Memory array word line, 12...Input amplifier,
13...Decoder, 14...Address input terminal, 15...Output amplifier, 16...Output terminal, 1
7...Circuit block according to the present invention.
Claims (1)
前記冗長ビツトを選択するワード線が活性化され
ると導通し、非活性状態では非導通となる
MOSFETと、前記MOSFETの一端を基準電圧
端子に接続する手段と、前記MOSFETの他端に
接続された複数のMOSダイオード直列回路と、
前記複数のMOSダイオード直列回路と前記メモ
リー装置の入力端子の１本とを接続する手段とを
有し、前記基準電圧端子に駆動電圧を印加して前
記メモリー装置が動作状態にある時、前記
MOSFETの導通・非導通に応じて前記入力端子
と前記基準電圧端子間に流れる電流の有無により
前記冗長ビツトの使用の有無を検出することを特
徴とする冗長ビツトの検出手段を有するメモリー
装置。1 In a memory device with redundant bits,
When the word line that selects the redundant bit is activated, it becomes conductive, and when it is inactive, it becomes non-conductive.
a MOSFET, means for connecting one end of the MOSFET to a reference voltage terminal, and a plurality of MOS diode series circuits connected to the other end of the MOSFET;
means for connecting the plurality of MOS diode series circuits to one of the input terminals of the memory device, and when the memory device is in an operating state by applying a driving voltage to the reference voltage terminal, the
A memory device having redundant bit detection means, characterized in that the presence or absence of use of the redundant bit is detected by the presence or absence of a current flowing between the input terminal and the reference voltage terminal in accordance with conduction or non-conduction of a MOSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58030289A JPS59157899A (en) | 1983-02-25 | 1983-02-25 | Memory device having detecting means for redundant bit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58030289A JPS59157899A (en) | 1983-02-25 | 1983-02-25 | Memory device having detecting means for redundant bit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59157899A JPS59157899A (en) | 1984-09-07 |
| JPS6350800B2 true JPS6350800B2 (en) | 1988-10-11 |
Family
ID=12299559
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58030289A Granted JPS59157899A (en) | 1983-02-25 | 1983-02-25 | Memory device having detecting means for redundant bit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59157899A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6398297U (en) * | 1986-12-17 | 1988-06-25 |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6214399A (en) * | 1985-07-12 | 1987-01-22 | Fujitsu Ltd | Semiconductor memory device |
| JPH07105157B2 (en) * | 1987-09-10 | 1995-11-13 | 日本電気株式会社 | Redundant memory cell use decision circuit |
| JP2507486B2 (en) * | 1987-10-14 | 1996-06-12 | 日本電気株式会社 | Semiconductor memory device |
| KR100370234B1 (en) * | 1999-09-14 | 2003-01-29 | 삼성전자 주식회사 | Apparatus for detecting faulty cells in semiconductor memory and method therefor |
| KR100837803B1 (en) | 2006-11-13 | 2008-06-13 | 주식회사 하이닉스반도체 | Voltage Detector and Apparatus for Generating Internal Voltage Having the Same |
-
1983
- 1983-02-25 JP JP58030289A patent/JPS59157899A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6398297U (en) * | 1986-12-17 | 1988-06-25 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59157899A (en) | 1984-09-07 |
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