JPS61199655A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61199655A
JPS61199655A JP60040486A JP4048685A JPS61199655A JP S61199655 A JPS61199655 A JP S61199655A JP 60040486 A JP60040486 A JP 60040486A JP 4048685 A JP4048685 A JP 4048685A JP S61199655 A JPS61199655 A JP S61199655A
Authority
JP
Japan
Prior art keywords
semiconductor device
conductive
source
code
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60040486A
Other languages
Japanese (ja)
Inventor
Michio Honma
本間 三智夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60040486A priority Critical patent/JPS61199655A/en
Publication of JPS61199655A publication Critical patent/JPS61199655A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/006Identification

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Quality & Reliability (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To eliminate any human reading of code numbers by a method wherein electrode pads independent of an inner functional part are connected to a gate of an MOS type transistor while a source or drain is connected in parallel with multiple electrode pads to form a part of connecting wiring in the state either electrically conductive or non-conductive. CONSTITUTION:A semiconductor device 1 as ROM or gate array impresses an electrode pad 3 with voltage immediately before starting an inspection to make an MOS type transistor 4 conductive. A semiconductor substrate is supplied with OV and then a source of the MOS type transistor 4 is also supplied with OV through a diffused layer 5. When multiple electrode pads 6a-6d are impressed with voltage, each pad is supplied with current or no current conforming to electrically conductive or non-conductive state of a part of wirings 7a-7d. Through these procedures, numbers may be displayed on codes by electrical conductive or non-conduction while any code number may by automatically known immediately before starting an inspection by means of making the numbers correspond to the code numbers. Besides, any increase in chip dimension of a semiconductor device may be reduced by means of providing only one additional pad for code checking.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に読み出し専用記憶半導
体装置(以下、ROMという。)や論理半導体装置(以
下、ゲートアレイという。)等の半導体装置に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor devices, and particularly to semiconductor devices such as read-only memory semiconductor devices (hereinafter referred to as ROM) and logic semiconductor devices (hereinafter referred to as gate arrays). Regarding.

〔従来の技術〕[Conventional technology]

従来、ROMやゲートアレイ#i製造工程中で、それぞ
れ記憶内容や論理内容をいろいろ変えて製造され、それ
ぞれの記憶内容や論理内容に1対l対応してコード番号
と呼ばれる番号が付けられていた。
Conventionally, during the manufacturing process of ROMs and gate arrays #i, they were manufactured with various storage contents and logical contents, and numbers called code numbers were assigned in one-to-one correspondence to each storage contents and logical contents. .

一方、これらROMやゲートlアレイの検査はコード番
号とl対l対応した検査パターンを検査装置にヂ読み出
して検査していた。この為、コード番号を検査前に識別
する必要があり、従来は人かコード番号を読み取るか、
専用に用意されたチェックパターンをチェ、りしてコー
ド番号を識別していた。
On the other hand, these ROMs and gate l arrays are tested by reading test patterns corresponding to code numbers and l to l into an inspection device. For this reason, it is necessary to identify the code number before testing, and conventionally it was necessary to identify the code number by a person or by reading the code number.
The code number was identified by checking a specially prepared check pattern.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところが、人がコード番号を読み取る場合は、番号の読
み間違いや、番号を読み取る工数がかかるという問題が
あり、専用のチェックパターンをチェックしてコード番
号を読み取る場合は、専用のチェックパターンを作るチ
ップ面積が必要となり、半導体装置のチップ寸法の増大
を招くとともに、チェ、クパターンをチェ、りする為の
機構を検査装置に設けなければならず、検査装置のコス
トも増大させるという問題があった。
However, when humans read the code numbers, there are problems such as misreading the numbers and the amount of man-hours required to read the numbers.If you want to read the code numbers by checking a special check pattern, it is necessary to use a chip that creates a special check pattern. This increases the area required, leading to an increase in the chip size of the semiconductor device, and requires a mechanism to be installed in the inspection equipment to check and remove the check pattern, resulting in an increase in the cost of the inspection equipment. .

従って、本発明の目的は、かかる人によるコード番号の
読み取りを無くし、かつ、新しく専用のチックパターン
を設ける為の半導体装置のチップ寸法の増加を少なくし
、かつ検査装置にチェックパターンをチェックする為の
機構を設けなくてもすむようにした半導体装置を提供す
ることにある。
Therefore, it is an object of the present invention to eliminate the need for such people to read code numbers, to reduce the increase in the chip size of semiconductor devices due to the provision of new dedicated tick patterns, and to enable inspection equipment to check the check patterns. An object of the present invention is to provide a semiconductor device that does not require the provision of a mechanism.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置は、ROM−jたけゲート/ノアレ
イの内部機能部とは独立した電極パッドを設゛け、該電
極パッドをMOS型トランジスタのゲートと接続し、該
MOS型トランジスタのソースあるいはドレインを半導
体基板と接続し、他方のソースあるいはドレインを前記
半導体装置の複数の電極パッドと並列に接続し、その接
続配線の一部が電気的に導通か不導通かいずれかの状態
に形成されることからなっている。
The semiconductor device of the present invention is provided with an electrode pad that is independent of the internal functional part of the ROM-J take gate/no array, connects the electrode pad to the gate of a MOS transistor, and connects the source or drain of the MOS transistor. is connected to the semiconductor substrate, the other source or drain is connected in parallel to the plurality of electrode pads of the semiconductor device, and a part of the connection wiring is formed to be either electrically conductive or non-conductive. It consists of things.

1作 用〕 この為、検査装置で検査開始直前に、MOS型トランジ
スタのゲートと接続している電極パッドに電圧を印加し
、MOS型トランジスタを導通状態KL、半導体基板と
半導体装置の複数の電極パッドに、それぞれソース、ド
レインとしての電圧を印加し、その電流を測定し、ソー
スあるいはドレインと電極パッドの電気的導通をチェッ
クし、その導通か不導通かによってコード番号を知るこ
とができる。また、半導体装置の検査時には、MOS型
トランジスタのケートには電圧を印加せずに非導通状態
にしておくことにより、検査時にコード番号チェック用
に使用した回路はすべて非導通状態になるので、コード
番号チェック用の回路の影響を無視できる。
1. For this reason, just before the inspection starts with the inspection equipment, a voltage is applied to the electrode pad connected to the gate of the MOS transistor, and the MOS transistor is brought into the conductive state KL, and the multiple electrodes of the semiconductor substrate and the semiconductor device are turned on. The code number can be determined by applying source and drain voltages to the pads, measuring the current, checking electrical continuity between the source or drain and the electrode pad, and determining whether the source or drain is electrically conductive or non-conductive. Also, when testing semiconductor devices, by not applying voltage to the gate of the MOS transistor and leaving it in a non-conducting state, all the circuits used to check the code number during the test will be in a non-conducting state. The influence of the number checking circuit can be ignored.

さらに、このように検査時に使用する電極パ。Furthermore, the electrode pads used during examinations in this way.

ドをコードチェック用の電極パッドとして共用する為に
、新しくコードチェック用の電極パッドを設ける量が著
しく減少し、半導体装置のチップ寸法の増加を少なくす
ることができる。その上、電極パッドからの電気的チェ
ックでコード番号を知ることができる為、通常の検査装
置の機能をそのまま使用してコード番号を識別すること
ができる為、コード番号をチェックする為の機構を新し
く検査装置に追加しなくとも良くなる。
Since the pad is shared as an electrode pad for code checking, the amount of new electrode pads for code checking can be significantly reduced, and an increase in chip size of the semiconductor device can be suppressed. Furthermore, since the code number can be determined by electrical check from the electrode pad, the code number can be identified using the functions of normal inspection equipment. There is no need to add anything new to the inspection equipment.

〔実施例〕〔Example〕

以下、図面を用いて本発明の実施例について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図は、本発明の一実施例の要部を示す模式的平面図
である。半導体装置1において、内部機能部2とは独立
した電極パッド3は、MOS型トランジスタ4のゲート
と接続されている。そのMOS型トランジスタ4のソー
スは半導体基板と拡散層5を通して接続され、ドレイン
は半導体装置の複数の電極パッド6a〜6dと並列に接
続ちれる。その接続配線の一部7a〜7dが電気的に導
通か不導通かのいずれかの状態に形成される。
FIG. 1 is a schematic plan view showing essential parts of an embodiment of the present invention. In the semiconductor device 1 , an electrode pad 3 independent of the internal functional section 2 is connected to the gate of a MOS transistor 4 . The source of the MOS transistor 4 is connected to the semiconductor substrate through the diffusion layer 5, and the drain is connected in parallel to a plurality of electrode pads 6a to 6d of the semiconductor device. Some of the connection wirings 7a to 7d are formed to be electrically conductive or non-conductive.

第2図(a)〜(C)は、前記導通、不導通の状態の形
成方法を説明するための説明図であり、第2図(a)社
、金属配線8が断線か否かで不導通、導通の状態を形成
する図、第2図(b)は層間膜のスルーホール9で金属
配線8と拡散層10を接続させるか否かで導通、不導通
の状態を形成する図、第2図(C)は拡散層10の有無
で導通、不導通の状態を形成する図である。
FIGS. 2(a) to 2(C) are explanatory diagrams for explaining the method of forming the conductive and non-conductive states. FIG. 2(b) is a diagram showing the formation of conduction and non-conduction states, and FIG. FIG. 2(C) is a diagram illustrating whether a conductive or non-conductive state is formed depending on the presence or absence of the diffusion layer 10.

1(、OMまたはゲートアレイとしての半導体装置ラン
ジスタ4のソースを□vにする。複数の電極パッド6a
〜6dに電圧を印加すると配線の一部7a〜7dの電気
的導通か不導通の状態により、それぞれ電流が流れたり
、流れなかったりする。
1 (, the source of the semiconductor device transistor 4 as an OM or gate array is set to □v. A plurality of electrode pads 6a
When a voltage is applied to the wirings 7a to 6d, current may or may not flow depending on whether the wirings 7a to 7d are electrically conductive or nonconductive.

このt流が流れる状態を′1”、流れない状態を0#と
すると、第2図(a) 、 (b) 、 (C)はそれ
ぞれ”0110”、”0101”、−1010’と2進
数で表わすことができる。10進数ではそれぞれ′6#
″5” ′10″′ を表わす@このように、電気的導
通、不導通で数を表示し、これをコード番号と対応する
ようKすれば、検査開始直前にコード番号を自動的に知
ることができる。また、コードチェ、り用には、1個の
余分のパッドを設けるだけでよく、半導体装置のチップ
寸法の増加を少なくできる。さらに、検査装置の機能を
そのまま使用してコード番号を識別できる為、新らたに
チェックパターンをチェックする為の機構を設けなくて
もすむ。
Assuming that the state in which this t flow is flowing is '1' and the state in which it is not flowing is 0#, Fig. 2 (a), (b), and (C) are binary numbers "0110", "0101", and -1010', respectively. It can be expressed as '6#' in decimal number respectively.
``5'' represents ``10''' @ In this way, if you display the number in terms of electrical continuity or non-continuity and set it to correspond to the code number, you can automatically know the code number just before starting the test. In addition, for code checking, it is only necessary to provide one extra pad, which reduces the increase in the chip size of the semiconductor device.Furthermore, the code number can be determined by using the functions of the inspection equipment as is. Since it can be identified, there is no need to newly provide a mechanism for checking the check pattern.

以上のように、通常の検査時に使用する電極パッドを共
用し、検査開始直前にコードチェックバとにより、コー
ドチェックパターン部が検査に影替を与えないようにで
きる。
As described above, by sharing the electrode pads used during normal inspection and using the code check bar immediately before the start of the inspection, it is possible to prevent the code check pattern portion from affecting the inspection.

なお、上記実施例においては、複数の電極バットとして
4個の場合を取り上けたけれども、本発明はこれに限定
される事なく一般に複数の電極バ、ドに対して適応され
る。
Although the above embodiment deals with a case where there are four electrode bats, the present invention is not limited thereto and is generally applicable to a plurality of electrode bats.

〔発明の効果〕〔Effect of the invention〕

以上、詳細説明したとおり、本発明によれば、上記手段
により、八によるコード番号の読み取りを無くシ、かつ
、新しく専用のチェ、クパターンを設ける為の半導体装
置のチップ寸法の増加を少くシ、さらに検査装置にチェ
ックパターンをチェックする為の機構を設けなくてもす
むようにした半導体装置が得られる。
As described above in detail, according to the present invention, the above means eliminates the need to read the code number by 8, and reduces the increase in chip size of a semiconductor device due to the provision of a new dedicated check pattern. Furthermore, it is possible to obtain a semiconductor device in which it is not necessary to provide a mechanism for checking the check pattern in the inspection device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の要部を示す模式的平面図、
第2図(a) 、 (b) 、 (C)はその配を部で
電気的に導通、不導通を形成する方法の説明図である。 7a〜7d・・・・・・配線の一部、8・・・・・・金
属配線、9°°゛°°°スルーホール、10・・・・・
・拡散層。 /生 代理人 弁理士  内 原   Hl  1゜\1、 (久) Cb)
FIG. 1 is a schematic plan view showing the main parts of an embodiment of the present invention;
FIGS. 2(a), 2(b), and 2(c) are explanatory diagrams of a method for forming electrical conduction or non-conduction at certain portions of the arrangement. 7a to 7d... Part of wiring, 8... Metal wiring, 9°°゛°°° through hole, 10...
・Diffusion layer. / Living Agent Patent Attorney Uchihara Hl 1゜\1, (ku) Cb)

Claims (4)

【特許請求の範囲】[Claims] (1)半導体装置において、内部機能部とは独立した電
極パッドを設け、該電極パッドをMOS型トランジスタ
のゲートと接続し、該MOS型トランジスタのソースあ
るいはドレインを半導体基板と接続し、他方のソースあ
るいはドレインを前記半導体装置の複数の電極パッドと
並列に接続し、その接続配線の一部が電気的に導通か不
導通かいずれかの状態に形成されていることを特徴とす
る半導体装置。
(1) In a semiconductor device, an electrode pad is provided independent of the internal functional part, the electrode pad is connected to the gate of a MOS transistor, the source or drain of the MOS transistor is connected to the semiconductor substrate, and the other source is connected to the gate of the MOS transistor. Alternatively, a semiconductor device characterized in that a drain is connected in parallel to a plurality of electrode pads of the semiconductor device, and a part of the connection wiring is formed to be either electrically conductive or non-conductive.
(2)電極パッドとソースあるいはドレインの接続配線
の一部が金属配線の断線か否かで電気的導通の有無の状
態が形成されていることからなる特許請求の範囲第(1
)項記載の半導体装置。
(2) Claim No. 1 in which a state of electrical continuity is formed depending on whether a part of the connection wiring between the electrode pad and the source or drain is disconnected or not.
) The semiconductor device described in item 2.
(3)電極パッドとソースあるいはドレインの接続配線
の一部が層間膜のスルーホールの開口の有無で電気的導
通の有無の状態が形成されていることからなる特許請求
の範囲第(1)項記載の半導体装置。
(3) Claim (1) in which a part of the connection wiring between the electrode pad and the source or drain is electrically connected depending on the presence or absence of a through hole in the interlayer film. The semiconductor device described.
(4)電極パッドとソースあるいはドレインの接続配線
の一部が拡散層配線の有無で電気的導通の有無の状態が
形成されていることからなる特許請求の範囲第(1)項
記載の半導体装置。
(4) A semiconductor device according to claim (1), wherein a part of the connection wiring between the electrode pad and the source or drain is electrically conductive depending on the presence or absence of a diffusion layer wiring. .
JP60040486A 1985-03-01 1985-03-01 Semiconductor device Pending JPS61199655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60040486A JPS61199655A (en) 1985-03-01 1985-03-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60040486A JPS61199655A (en) 1985-03-01 1985-03-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61199655A true JPS61199655A (en) 1986-09-04

Family

ID=12581921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60040486A Pending JPS61199655A (en) 1985-03-01 1985-03-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61199655A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9159654B2 (en) 2011-09-01 2015-10-13 Mitsubishi Electric Corporation Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5772362A (en) * 1980-10-23 1982-05-06 Nec Corp Semiconductor device
JPS583256A (en) * 1981-06-30 1983-01-10 Fujitsu Ltd Lsi chip

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5772362A (en) * 1980-10-23 1982-05-06 Nec Corp Semiconductor device
JPS583256A (en) * 1981-06-30 1983-01-10 Fujitsu Ltd Lsi chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9159654B2 (en) 2011-09-01 2015-10-13 Mitsubishi Electric Corporation Semiconductor device

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