JPS583256A - Lsi chip - Google Patents

Lsi chip

Info

Publication number
JPS583256A
JPS583256A JP56101902A JP10190281A JPS583256A JP S583256 A JPS583256 A JP S583256A JP 56101902 A JP56101902 A JP 56101902A JP 10190281 A JP10190281 A JP 10190281A JP S583256 A JPS583256 A JP S583256A
Authority
JP
Japan
Prior art keywords
identification code
chip
lsi chip
external terminal
present
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56101902A
Other languages
Japanese (ja)
Inventor
Kazuya Kobayashi
小林　和弥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56101902A priority Critical patent/JPS583256A/en
Publication of JPS583256A publication Critical patent/JPS583256A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H01L2223/5444—Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To enable to automat the testing step of an LSI chip by providing external terminals for an IC structure identifying code pattern and an identification code output in the chip. CONSTITUTION:An identification code pattern representing the logic structure of an IC is formed in an LSI chip, and an external terminal 3 (4 designates an external terminal for a general signal) for reading externally the identification code is provided. In this manner, the testing step of the chip can be automated.

Description

【発明の詳細な説明】 本発明は１．ＩＩチップに関する。従来、マスタ・スラ
イスＬＳＩなどは、その製造期間がフルカスタムＬ８Ｉ
に比較して短いため、論理紋針に広く使用されていａｏ
Ｌかしながら、その品柚数は逆にカスタムＬ８Ｉに比較
して多くなり、製造工程、試験工程の管理を抜雑化させ
ている。例えは、試験過程においても、その■０チクプ
の回路喬号によりてテスト・プログラムパターンが異な
り、それをそのＧＩＮ人手により指示することは時間を
無駄にするばかりか、誤操作を招きやすい・本発明は上
記間組点を解決し、試験工程の蕾埋勢を容易にすること
を目的とし、そしてそのため本発明によるＬ８Ｉチップ
はＩＯチップ内部に当該ＩＯの論理構造を示す識別コー
ドを固定パターンとして回路的に潜在してもうけるとと
もに、該曽在緻別コードを外部から絖出し可能とする手
段をそなえたことを特徴とする。すなわち本発明は、Ｌ
ＳＩチップ内部に回路を組立てるときに、その工０の論
理構造を示す識別コードをＲＯＭのように通常の配線パ
ターンプロセスにて潜在させ、試験時には、それを外部
からテスターにて自動的に絖取り、抜続するテストパタ
ー７の績械的処理等を可能にするようにしたものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention consists of 1. Regarding the II chip. Traditionally, the manufacturing period for master slice LSIs was fully custom L8I.
It is widely used for logical pattern needles because it is shorter than ao.
However, on the contrary, the number of products is larger than that of the custom L8I, and the management of the manufacturing process and testing process has become sloppy. For example, even in the testing process, the test program pattern differs depending on the circuit code of the circuit, and manually instructing it is not only a waste of time, but also tends to lead to operational errors.The present invention The purpose of the present invention is to solve the above-mentioned problems and to facilitate the testing process, and for this reason, the L8I chip according to the present invention has an identification code indicating the logical structure of the IO as a fixed pattern inside the IO chip. The present invention is characterized in that it has a means for making a latent profit and making it possible to derive the existing elaboration code from the outside. That is, the present invention provides L
When assembling a circuit inside an SI chip, an identification code indicating the logical structure of the process is hidden in a normal wiring pattern process like a ROM, and during testing, it is automatically removed by a tester from the outside. , it is possible to mechanically process the successive test putters 7, etc.

以下、本発明を図面により説明する。第１図は本発明に
よる第ｌの実施例のＬＳＩチップの構成を示す図であり
、図中ｌはＬＳＩチップ、２は縁側コードパターン、３
は識別コード出力用外部端子（Ｉ八、ＩＤ、　、ＩＤ、
）、４は一般信号用外部端子である。この給１図の実施
例は、識別コードパターン情報を直接、専用の外部端子
に出力する例である。Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a diagram showing the configuration of an LSI chip according to a first embodiment of the present invention, in which l is an LSI chip, 2 is an edge code pattern, and 3
is an external terminal for outputting identification code (I8, ID, , ID,
), 4 are external terminals for general signals. The embodiment shown in Figure 1 is an example in which identification code pattern information is directly output to a dedicated external terminal.

第２図は本発明による嬉２の実施例のＬＳＩチップの構
成を示す図であり、図中、１０はＬＳＩチップ、１１は
識別コードパターン、１２はデコーダ（ｎｈ、ｃ）、１
３はセレクタ（８ＥＬ）、１４は選択アドレス信号入力
用外部端子（５ＡＩ３１１４〜ＳＡりＤり、１５は選択
信号出力用外部端子（ＳＯＵＴ、　）である。FIG. 2 is a diagram showing the configuration of an LSI chip according to the second embodiment of the present invention, in which 10 is an LSI chip, 11 is an identification code pattern, 12 is a decoder (nh, c), 1
3 is a selector (8EL), 14 is an external terminal for inputting a selection address signal (5AI3114-SA), and 15 is an external terminal for outputting a selection signal (SOUT).

この第２囚の実施例は外部端子５ＯＵＴ、　Ｉｆ、に、
選択アドレス信号５ＡＤＤ、〜８ＡＤＤ、にょって指示
されたゲートの状態か出力されるようにしたものである
。例えは、選択アドレス（ＳＡＤＤ）−０（７）とき識
別コード情報Ｉ　Ｄ、’　１　’　、選択アドレス（Ｓ
ＡＤＤ）−１のとき魚別コード情報ＩＤ、％Ｉ１１選択
アドレス（８ＡＤＤ）−２のとき識別コード情報ＩＤ。This second prisoner embodiment has external terminal 5OUT, If,
The state of the gate designated by the selection address signals 5ADD, .about.8ADD is output. For example, when the selection address (SADD) - 0 (7), the identification code information ID, '1', the selection address (S
ADD)-1 is the fish-specific code information ID, %I11 selection address (8ADD)-2 is the identification code information ID.

１０′かそれぞれ出力され、その他の選択アドレス（８
ＡＤＤ）−３〜７に対しては他の一般信号ゲートの出力
情報が出力されるよう制御が行なわれる。10' are output respectively, and other selected addresses (8
ADD)-3 to -7 are controlled so that the output information of other general signal gates is output.

嬉２図の実施例の場合は現在性なわれているＬＳＩテス
ト十法の１つであるアドレススキャンシステムの一槙と
して組込んだ例であり、もともとのスキャン系に必要と
！Ｊ−るＩ１０端子のるで処理でさ、識別コード用の特
別な端子は必豐としない。The example shown in Figure 2 is an example of an address scan system that is incorporated as one of the ten currently available LSI test methods, and is not necessary for the original scan system. Since the J-RU I10 terminal is processed, a special terminal for the identification code is not required.

第３図は本発明による第３の実施例のＬＳＩチップの構
成を示す図であり、図中、２０はＬＳＩチップ、２１は
識別コードパターン、２２はセレ２　フタ（ＳＥＬ）、
２３は識別コード出力用または一般信号入出力用外部端
子、２４は一般信号入出力外部端子、２５は識別コード
続出制御信号（ＩＤ〜ｋＬＥＡＤ）入力端子である。こ
の第３ｇ４の実施机は識別コード悄＠ｉを一般信号入出
力外部端子を使用し゛ＣＣ出出例であり、ｖｌえばＩＤ
−ＲＥＡＤか１１＃のとき識別コード悄＠（ＩＤ、　〜
ＩＤ、；″″１＃、１１１１０′）が続出され、ＩＤ−
ＲＥＡｌ）が１０ｇのとき一般佃号の入出力が行なわれ
るようにされる。FIG. 3 is a diagram showing the configuration of an LSI chip according to a third embodiment of the present invention. In the figure, 20 is an LSI chip, 21 is an identification code pattern, 22 is a selector 2 lid (SEL),
23 is an external terminal for outputting an identification code or for inputting and outputting a general signal, 24 is an external terminal for inputting and outputting a general signal, and 25 is an input terminal for an identification code successive control signal (ID to kLEAD). This 3rd g4 implementation machine uses the general signal input/output external terminal for the identification code @i, and is an example of CC output.
-When READ or 11#, the identification code 悄@(ID, ~
ID, ;″″1#, 11110′) are displayed one after another, and ID-
When REA1) is 10g, input/output of a general code is performed.

以上１明し１こように本発明によれば、ＬＳＩチップの
内部−塩構造を示す識別コードを同定パターンとして回
路的に柵柱してもうけるとともに、この識別コードを外
部から絖出し可能な構成としたので、試験工程の自動化
等が可能となり、その効果は極めて大きい。As described above, according to the present invention, an identification code indicating the internal salt structure of an LSI chip is provided as an identification pattern as a fence post in a circuit, and this identification code can be read out from the outside. This makes it possible to automate the testing process, and the effects are extremely large.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の第１の実施例の構成を示す図、第２図
は本発明の第２の実施例の構成を示す図、第３図は本発
明の第３の実施例の構成を示す図である。図中、ｌ、１
０．２０はＬＳＩチップ、２．１１゜２１は識別コード
パターンである。 耳１１２１ 躊３ｎ ＩＩＩ−１１４０FIG. 1 is a diagram showing the configuration of a first embodiment of the invention, FIG. 2 is a diagram showing the configuration of a second embodiment of the invention, and FIG. 3 is a diagram showing the configuration of a third embodiment of the invention. FIG. In the figure, l, 1
0.20 is an LSI chip, and 2.11°21 is an identification code pattern. Ear 1121 Hei 3n III-1140

Claims (1)

【特許請求の範囲】[Claims] ■０チップ内部に当該ＩＯの論理構造を示す識別フード
を固定パターンとして回路的に潜在してもうけるととも
に、該潜在識別コードを外部から胱出し可能とする手段
をそなえたことを特徴とするＬ８１チップ。(1) An L81 chip characterized by having an identification hood showing the logical structure of the IO as a fixed pattern hidden in the circuit inside the 0 chip, and having a means for making the latent identification code externally accessible. .
JP56101902A 1981-06-30 1981-06-30 Lsi chip Pending JPS583256A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56101902A JPS583256A (en) 1981-06-30 1981-06-30 Lsi chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56101902A JPS583256A (en) 1981-06-30 1981-06-30 Lsi chip

Publications (1)

Publication Number Publication Date
JPS583256A true JPS583256A (en) 1983-01-10

Family

ID=14312839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56101902A Pending JPS583256A (en) 1981-06-30 1981-06-30 Lsi chip

Country Status (1)

Country Link
JP (1) JPS583256A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60211955A (en) * 1984-04-06 1985-10-24 Nec Corp Integrated circuit
JPS61199655A (en) * 1985-03-01 1986-09-04 Nec Corp Semiconductor device
US5079725A (en) * 1989-11-17 1992-01-07 Ibm Corporation Chip identification method for use with scan design systems and scan testing techniques
JPH04353060A (en) * 1991-05-29 1992-12-08 Oi Seisakusho Co Ltd Pedal operated type parking brake device
FR2875623A1 (en) * 2004-09-23 2006-03-24 St Microelectronics Sa GENERATING AN IDENTIFIER OF AN INTEGRATED CIRCUIT
FR2875624A1 (en) * 2004-09-23 2006-03-24 St Microelectronics Sa DETERMINISTIC GENERATION OF AN IDENTIFIER NUMBER OF AN INTEGRATED CIRCUIT

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5650526A (en) * 1979-10-02 1981-05-07 Mitsubishi Electric Corp Semiconductor device
JPS5772362A (en) * 1980-10-23 1982-05-06 Nec Corp Semiconductor device
JPS5793519A (en) * 1980-12-02 1982-06-10 Nec Corp Semiconductor device
JPS5793520A (en) * 1980-12-02 1982-06-10 Nec Corp Semiconductor device
JPS57115855A (en) * 1981-01-12 1982-07-19 Hitachi Ltd Large scale semiconductor integrated circuit device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5650526A (en) * 1979-10-02 1981-05-07 Mitsubishi Electric Corp Semiconductor device
JPS5772362A (en) * 1980-10-23 1982-05-06 Nec Corp Semiconductor device
JPS5793519A (en) * 1980-12-02 1982-06-10 Nec Corp Semiconductor device
JPS5793520A (en) * 1980-12-02 1982-06-10 Nec Corp Semiconductor device
JPS57115855A (en) * 1981-01-12 1982-07-19 Hitachi Ltd Large scale semiconductor integrated circuit device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60211955A (en) * 1984-04-06 1985-10-24 Nec Corp Integrated circuit
JPS61199655A (en) * 1985-03-01 1986-09-04 Nec Corp Semiconductor device
US5079725A (en) * 1989-11-17 1992-01-07 Ibm Corporation Chip identification method for use with scan design systems and scan testing techniques
JPH04353060A (en) * 1991-05-29 1992-12-08 Oi Seisakusho Co Ltd Pedal operated type parking brake device
FR2875623A1 (en) * 2004-09-23 2006-03-24 St Microelectronics Sa GENERATING AN IDENTIFIER OF AN INTEGRATED CIRCUIT
FR2875624A1 (en) * 2004-09-23 2006-03-24 St Microelectronics Sa DETERMINISTIC GENERATION OF AN IDENTIFIER NUMBER OF AN INTEGRATED CIRCUIT
WO2006032823A3 (en) * 2004-09-23 2006-12-07 St Microelectronics Sa Generating an integrated circuit identifier
US7871832B2 (en) 2004-09-23 2011-01-18 Stmicroelectronics S.A. Generating an integrated circuit identifier
US8330158B2 (en) 2004-09-23 2012-12-11 Stmicroelectronics S.A. Generating an integrated circuit identifier

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