JPS60211955A - Integrated circuit - Google Patents

Abstract

PURPOSE:To enable to perform a test according to the respective difference of circuits by a method wherein the partial differences of a master slice circuit and so forth are encoded and the references are memorized in an LSI, the code of one of the circuits is outputted at the testing time of the circuits and the code is read out by an LSI tester. CONSTITUTION:The address data of an address bus 33 are inputted in an address decoder 31 and when the testing signal, which is sent from a testing terminal 19, is one of low level, an arbitrary address of a main ROM29 is assigned according to the address data. When the testing signal, which is sent from the testing terminal 19, is one of high level, an arbitrary address of a testing ROM30 is assigned. The data of the assigned address of the main ROM 29 or the testing ROM30 are read out of ROM damping output terminals 11-18 through a ROM readout circuit 28. The data on an aluminum master slice circuit of input terminals 20-23 and output terminals 24-27 are written in the testing ROM30 as a data of ''0'' or ''1''. The data written in this testing ROM30 are outputted from ROM damping output terminals 11-18 at the testing time of the aluminum master slice circuit.

Description

[Detailed Description of the Invention] (Technical Field) The present invention can be used for different purposes by changing only a part of the circuit, such as the presence or absence of a pull-down resistor, CMOS buffer output, and open drain output. similar LS
Regarding I (large-scale integrated circuits), especially 1-step φ microcomputers with a master slice function,
This invention relates to a circuit for testing SI.

(Background of the Invention) R, OM, RAM, input device and output device, R
A one-chip system further includes a CPU that receives input from an input device, manipulates data in RAM, and outputs the results to an output device according to programs and programs stored in the OM.
Microcomputers are used in home appliances such as watches, cameras,
It is also widely used in consumer fields such as games.

By the way, in the input circuit, an input circuit without a pull-down resistor is used for input from other ICs, and an input circuit with a pull-down resistor is used for direct input from the switch. In addition, regarding the output circuit, LED, which uses high voltage) LIAC.

Open-drain output is used when directly driving a reed relay, etc., and 0MO8 output is used when a high voltage is not required for output, such as when inputting to another IC. As described above, various input/output circuits are required depending on the application circuit.

In order to accommodate these various applications, some circuits have been conventionally changed using aluminum O master slices, such as the presence or absence of a pull-down resistor, open drain output, and 0MO8 output.

This aluminum master slice will be explained a little using Figure 1. Figure 1 (a) is a circuit diagram of the input circuit with pull-down resistor 7, and Figure 1 (b) is a circuit diagram of the input circuit with pull-down resistor 7. FIG. 2 is a circuit diagram of an input circuit without a That is, in FIG. 1 (al), the pull down resistor 7 is connected to the input terminal 1 and the inverter 6.
It is connected to the gate of the first
In Figure (b), the pull-down resistor 7 is not connected to the input terminal 1 and the gate of the inverter 6 because no aluminum wiring is formed. Note that four diodes 4 and one resistor 5 represent an input protection circuit.

Further, FIG. 2(a) is a circuit diagram of a CMOB output circuit, and FIG. 2(b) is a circuit diagram of an N-channel open drain output circuit. In FIG. 2(a), the drain of the N-channel MOS transistor 9 and the drain of the P-channel MOS transistor 8 are connected to the output terminal 10 by aluminum wiring, whereas the
In Figure (b), the drain of the N-channel MOS transistor 9 is connected to the output terminal 1°, but the drain of the P-channel MOS transistor 8 is not connected because no aluminum wiring is formed.

The changes in (a) and (b) in Figures 1 and 2 are based on LSI
This can be done by changing the mask of the aluminum wiring in one place, and the other circuits may be exactly the same.

However, in an L-chip micro converter, the number of combinations of aluminum master slices for input/output terminals, etc. may exceed several dozen types. For this reason, %LSI
Test programs must be prepared for each aluminum master slice combination.

(Objective of the Invention) An object of the present invention is to provide an LSI having a test circuit that can be tested using the same test program even if some of the circuits, such as a master slice, are of different types.

(Structure of the Invention) The LSI according to the present invention encodes differences in some circuits such as a master slice and stores them in the LSI, outputs the code at the time of testing, and reads the code by an LSI tester. It is characterized by performing tests according to the differences in each circuit.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention. In FIG. 3, the address decoder 31 inputs the address data of the address path 33, and when the TEST signal from the T:IT terminal 19 is at a low level, an arbitrary address of the main ROM 29 is input according to the address data. Specify. When the TEST signal from the TEf9T terminal 19 is at the no-i level, an arbitrary address in the test ROM 30 is designated.

The data at the specified address in the main ROM 29 or test ROM 30 is read out through the ROM reading circuit 28.
It is read from the OM dump output terminals 11 to 18.

The LSI 34 shown in FIG. 3 further has four signal input terminals 20 to 23 and four signal output terminals 24 to 27. In particular, the input terminals 20, 22 and 23 are pull-down resistor cloths, and the input terminals 21 and 23 are pull-down resistor cloths. is an input terminal for pull-down resistor heat, output terminal 24 is an N-channel open drain output, and output terminals 25, 26, and 27 are output terminals for 0MO8 output. These input terminals 20~
23 and the aluminum Φ master slice data of output terminals 24 to 27 are written in the test ROM 30 as o, 1 data. The data of this test 140M30 is output to the ROM dump output terminals 11-18 during testing. The relationship between the output data of the ROM dump output terminals 11 to 18 and the aluminum master slice at that time is shown in FIG. In FIG. 4, the data of the aluminum master slice of one terminal is represented as data of 1 and 7 of the test ROM.

If there is a pull-down resistor, the corresponding test R
OM data should be 1, O if there is no pull-down resistor
It is. Similarly, in the case of 0MO8 output, the test ROM data is 1, and in the case of open drain, it is 0.

The test program of the LSI tester (not shown) that tests this LSI starts with the RO of FIG. 3 at the start of the test.
It is designed to read the aluminum fist master fist slice data outputted to the M dump output terminals 11 to 18 as shown in Fig. 4, and perform tests according to each aluminum Φ master slice using that data. This allows for a large number of aluminum master m-slice varieties.
It can be executed with one test program.

In the above embodiment, the aluminum master slices were all related to input/output terminals, but the CPU
It is also conceivable to use an aluminum master slice to switch parts not related to input/output terminals, such as switching the clock speed. Further, the function may be switched not depending on the aluminum master slice but also on a contact mask or the like.

[Brief explanation of the drawing]

Figure 1 (a) is a circuit diagram of an input circuit with a pull-down resistor, Figure 1 (b) is a circuit diagram of an input circuit without a pull-down resistor, and Figure 2 (a) is a circuit diagram of an output circuit with 0MO8 output. 2(b) is a circuit diagram of an output circuit for N-channel open drain output, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is a diagram of an embodiment of the same embodiment as FIG. FIG. 2 is a diagram showing the correspondence between aluminum master m-slice and test) ROM data. 1.20~23...Input terminal, 2...
Positive power supply, 3... Negative power supply, 4...
...Protection diode, 5...Protection resistor, 6...
...Inverter, 7...Pull-down resistor,
8...P channel MOS transistor, 9.
...N-channel MOS transistor, 1o. 24-27...Output terminal, 11-18...
...ROM dump output terminal, 19...TENT
Terminal, 28...ROM read circuit, 29...
...Main ROM, 30...Test ROM
, 3i...address decoder, 33...
...Address Φ bus, 34...LSI, Figure 1 (phantom) Figure 1 (10) Ward 2 (a-'') Figure 2 (b)

Claims (1)

[Claims] An integrated circuit characterized in that the configuration of the circuit is coded and stored internally, and the code is read out at the time of testing so that tests can be performed according to each circuit.