JPH0897365A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To make it possible to monitor a large number of signals from inside an IC to be monitored in simple structure under control without increasing its output terminals. CONSTITUTION: Output signals of an internal circuit are derived to an output terminal 2a by way of a switch 3a-0. An internal monitor signal is shared by way of switches 3a-1 to 3a-n respectively and further derived to the output terminal 2a by way of a switch 3a-0'. On one hand, a clock CK is counted by a counter 6 where this count output signal is decoded by a decoder 7 so as to provide an output 0-n. If each of the switches is selectively ON-controlled based on the decoded output, it will be possible to monitor easily a large number of internal signals with a single output terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device capable of outputting an internal signal to be monitored in addition to an output signal of an internal circuit without increasing the number of terminals to improve a fault detection rate. The present invention relates to an integrated circuit device.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit device,
In order to improve the failure detection rate, it becomes necessary to monitor signals at many monitoring points inside the circuit. There are various methods for monitoring in this case, but JP-A-63-2794
As disclosed in Japanese Patent Publication No. 89, a method of directly deriving a signal at an internal monitor location to an output terminal, or an internal flip-flop circuit, a latch circuit, etc. are connected in series to form a shift register. There is a method of operating as a scan path so that the contents of can be directly read from the outside, and a cross-check method of compressing all the internal signals and deriving them to an output terminal.

Furthermore, as disclosed in Japanese Patent Laid-Open No. 62-087877, a method of generating parity of an internal signal and deriving its output to an output terminal, and Japanese Patent Laid-Open No. 64-030255.
As disclosed in the publication, there is a method in which an input switching circuit and an output switching circuit are provided inside and each output of the internal circuit is selectively led to an output terminal by these switching circuits.

[0004]

In the method of directly deriving an internal signal to the outside, it is necessary to provide terminals corresponding to the number of internal signals to be monitored, and there is a fatal defect that the number of terminals increases. In the scan path method, it is necessary to provide wiring for configuring the scan path in advance, switching circuits for scan path operation, and switching circuits such as clock switching for scan path are also required. It has the drawback of lowering the degree of integration, and in addition, the test pattern needs to be specially prepared for the scan test.

The cross-check method is not preferable because it requires a signal compression circuit, which further increases the circuit scale.
Further, the parity check method has a drawback that it cannot be applied when the number of monitor points is an even number, and it has a drawback that it is impossible to specify a failure point.

Therefore, the present invention has been made to solve the drawbacks of the prior art, and its object is to suppress the increase in the number of output terminals and to monitor many internal monitor signals. Another object of the present invention is to provide a semiconductor integrated circuit device having a simple structure that enables identification of a failure location.

[0007]

According to the present invention, an output terminal for deriving a signal to the outside and an internal first to nth signal (n is an integer of 2 or more) to be monitored are respectively dealt with. First to nth switching elements for commonly deriving corresponding signals to the output terminals, counting means for counting an external clock, and the first to nth switches according to the count output. A semiconductor integrated circuit device including a control means for selectively turning on an element is obtained.

Further, according to the present invention, an output signal switch element for deriving an output signal of an internal circuit to the output terminal, and an alternative internal by the first to nth switch elements to the output terminal. An internal monitor signal switch element for deriving a monitor signal to the output terminal is further included, and the control means selectively turns on the output signal switch element and the internal monitor signal switch element. A semiconductor integrated circuit device characterized by being configured is obtained.

[0009]

A plurality of switch elements are provided corresponding to a plurality of internal signals to be monitored, and the outputs of these switch elements are connected to a common output terminal. And, these switch elements are selectively turned on, but in this case,
A clock is externally input to the counter to count the clock, and the switch element is selectively turned on according to the count output.

By doing so, only one output terminal is required for a large number of signals to be monitored, and only one clock input terminal need be provided for ON control of each switch element. The configuration also becomes a simple one in which a counter and a switch element are added.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
C device 100 has a large number of input / output terminals (indicated by squares)
Is provided. The output signals of the internal circuit (not shown) (two in this example) are the switches 3a-0, 3b-0 formed of transfer gates and the buffers 4a, 4b.
Via output terminals 2a and 2b, respectively.

2n lines to be monitored (n is an integer of 2 or more)
Of the internal monitor signals of n are switches 3a-1 to 3a
-N are commonly connected through the common switch 3
It can be led out to the output terminal 2a via a-0 '(assuming it is via the buffer 4a).

The remaining n of the internal monitor signals are commonly connected through the switches 3b-1 to 3b-n, respectively, and can be led out to the output terminal 2b through the common switch 3b-0 '( Via the buffer 4b).

A counter 6 and a decoder 7 for decoding the count output of the counter 6 are provided to turn on and off the respective switches. The counter 6 operates by the clock signal CK and the reset signal RS applied from the input terminals 2c and 2d via the buffers 4c and 4d, respectively.

The decoder 7 is adapted to obtain n + 1 decode outputs 0 to n, the decode output 0 controls the switches 3a-0 and 3b-0, and the decode output 1 is the switches 3a-1 and 3b-. Control 1 and decode output 2
Controls the switches 3a-2 and 3b-2, and the decode output n controls the switches 3a-n and 3b-n. The inverted output 0'of the decoded output 0 is obtained by the inverter 8, and the inverted output 0'is formed by the switches 3a-0 'and 3b-.
It controls 0 '.

FIG. 2 is a time chart of each part showing the operation of the circuit of FIG. Note that each switch is under low enable control. When the counter 6 is in the reset state, the output 0 of the decoder 7 is at a low level, so only the switches 3a-0 and 3b-0 are turned on and the switches 3a-0 'and 3b-0' are turned off. The output signal and the output terminals 4a and 4b are led to the normal operation.

When the clock CK is supplied to the counter 6, the output 0 of the decoder 7 becomes high level and the switch 3
a-0, 3b-0 are turned off, and the switches 3a-0 ',
3b-0 'is turned on. Therefore, the output terminals 2a and 2b
In place of the output signal, the internal monitor signal can be selectively derived.

The counter 6 continues counting the clock CK, and the count content is "1" → "2" → "3" ....
If the decode outputs 1 to n of the decoder 7 are sequentially changed to the low level each time it is sequentially changed to "n", the switches 3a-1 to 3a-n are sequentially turned on alternately. In addition, the switches 3b-1 to 3b-n are sequentially turned on alternately, and one of each of the n internal monitor signals is sequentially output to each of the output terminals 2a and 2b to be monitored. It will be.

The switch element is preferably a transfer gate in terms of IC, but it is obvious that another electronic switch element may be used.

[0021]

As described above, according to the present invention, a large number of internal monitor signals can be monitored without increasing the number of IC terminals by a very simple hardware structure, and the location of a failure can be easily identified. There is an effect.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention.

FIG. 2 is a waveform chart of each part showing the operation of the block of FIG.

[Explanation of symbols]

 2a, 2b output terminal 3a-0, 3b-0 output signal switch 3a-0 ', 3b-0' internal monitor signal switch 3a-1 to 3b-n, 3b-1 to 3b-n switch 4a to 4d buffer 6 Counter 7 Decoder 8 Inverter

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 21/66 Y 7735-4M

Claims (3)

[Claims] 1. An output terminal for deriving a signal to the outside, and an output terminal provided corresponding to an internal first to nth signal (n is an integer of 2 or more) to be monitored. To the n-th switch element for commonly deriving to, a count means for counting the external clock, and a control for selectively turning on the first-nth switch element according to the count output. And a semiconductor integrated circuit device. 2. An output signal switch element for deriving an output signal of an internal circuit to the output terminal, and an alternative internal monitor signal from the first to nth switch elements to the output terminal. An internal monitor signal switch element for deriving the output signal to the control circuit, and the control means is configured to selectively turn on the output signal switch element and the internal monitor signal switch element. The semiconductor integrated circuit device according to claim 1, which is characterized in that. 3. The control means has a decoder for decoding the count output, and each of the first to n-th switch elements, the output signal switch element, and the internal monitor signal switch element is decoded by the decoder output. The control device according to claim 1 or 2, wherein the control device is configured to control.
13. The semiconductor integrated circuit device according to claim 1.