JPH03208134A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the throughput of a DC test by providing a switching element which selects one signal among respective input signals and output it to a buffer circuit based on an external control signal on a selection circuit. CONSTITUTION:When the switching element Tr in the selection circuit 6 selects an H-level signal VH, an output circuit 1 comes to a state where it outputs the H-level signal through the buffer circuit 5 without operating an internal circuit. When the element Tr selects an L-level signal VL, the circuit 1 comes to a state where it outputs the L-level signal through the circuit 5 without operating the internal circuit. When the input signal Vin is selected, the signal Vin inputted from the internal circuit is outputted from the circuit 1.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor integrated circuit that outputs an output signal from an internal circuit to an external path via an output circuit, one objective is to improve the throughput of DC testing, and the internal circuit of the integrated circuit is An output circuit that outputs an input signal outputted from the circuit as a binary voltage signal of H level and level 2 to an external circuit via a buffer circuit, the input terminal of the output circuit and the buffer circuit. ! : A selection circuit is interposed between {j, the input signal input from the human input terminal, an H level signal, and an L level signal to be supplied to the selection circuit, and the selection (rjl fJ, The device is configured to include a switching element that selects one of the signals based on an external control signal and outputs the selected signal to the buffer circuit.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit that outputs an output signal from an internal circuit to an external circuit via an output circuit.

In the testing process of semiconductor integrated circuits, the H level or L level output voltage output from the output terminal is checked.
Although the C test is being conducted, there is a demand for shortening the time required for the DC test in order to improve the throughput of the inspection process.

[Conventional technology]

Conventionally, in DC testing of semiconductor integrated circuits, the output signal is output from each output terminal via the output circuit by operating the internal circuit, and the output signal voltage of H level or L level output from each output terminal is It is checked whether it is a predetermined value.

[Problem to be solved by the invention]

In the above DC test, if the output signal of a multi-bit counter is output from multiple output terminals via an output circuit, check the output signal voltage at H level and L level of each output terminal. This requires a large amount of testing time. That is, for example, if a 4-bit counter is n
To check all the H level and L level output signal voltages of each output terminal when the stages are connected in series and the 4-bit output signal of the final stage counter is output from the output terminal via the output circuit, It is necessary to sequentially count each counter until each output terminal changes from L level to H level, so it is necessary to sequentially input input signals of the (2')" pattern to the first stage counter. For this reason, there were problems in that it was extremely complicated to prepare a huge number of test patterns for operating internal circuits for DC tests, and the time required for DC tests was increased, reducing throughput. .

An object of the present invention is to provide a semiconductor integrated circuit that can improve the throughput of DC testing.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention. That is, the output circuit 1 outputs the input signal Vin output from the internal circuit of the integrated circuit as a binary voltage signal of H level and L level to the external circuit via the buffer circuit 5.
A selection circuit 6 is interposed between the input terminal Tin of the output circuit l and the buffer circuit 5, and the selection circuit 6 receives the input signal Vin input from the input terminal Tin, the H level signal V}I, and the selection circuit 6. , L level signal VL are supplied to the selection circuit 6, and the selection circuit 6 includes a switching element Tr that selects one of the signals from among the signals based on the external control signal Sin and outputs the selected signal to the Banofa circuit 5. It is equipped.

(Function) When the HL/bell signal V}l is selected by the switching element Tr in the selection circuit 6, the output circuit 1 enters a state in which it outputs an H level signal without operating the internal circuit.
When the L level signal VL is selected by the switching element Tr, the output circuit 1 becomes L without operating the internal circuit.
When the level signal is output and the input signal Vin is selected, the input signal Vin is input manually from the internal circuit.
is output from the output circuit 1.

〔Example〕

Embodiments embodying this invention will be described below with reference to FIGS. 2 to 5. As shown in FIG. 2, a large number of output circuits 1 provided in a semiconductor integrated circuit each output an input signal Vin manually inputted from an internal circuit as an output signal Vout, and each output circuit 1 has a common device. Three pairs of control signals are each input from the multiplexer 2, and the demultiplexer 2 is configured to input H level and L level voltage signals as external control signals to input terminals Sl and S2.

The configuration of the demultiplexer 2 will be explained according to FIG. 3. The demultiplexer 2 has five inverters 3a to 3e.
and three NAND circuits 4a to 4C, the input terminals Sl and S2 are connected to inverters 3a and 3b as well as NAND circuits 4b and 4c, and the inverter 3
The output terminal of a is connected to NAND circuits 4a and 4c, and the output signal of inverter 3b is connected to NAND circuits 4a and 4b. In addition, each NAND circuit 4a, 4b, 4c
Output signals XO, XI, X2 outputted from the circuit 1 and complementary output signals YO, Yl, Y2 obtained by inverting each output signal XO, XI, X2 by inverters 3c to 3e are outputted to the output circuit 1. When the external control signals Sin are inputted to the input terminals SL and S2 in the combination shown in FIG. 4, the output signal level Xout of each output signal XO, XI, and X2 is outputted in the combination shown in FIG. Note that in the figure, "l" indicates H level, and "0" indicates L level.

The configuration of the output circuit 1 will be explained with reference to FIG. 5. The output circuit 1 is composed of a buffer circuit 5 composed of two stages of inverters, and a selection circuit 6 connected to the previous stage of the buffer circuit 5. , an output signal Vout is output from the output terminal of the buffer circuit 5.

The selection circuit 6 is composed of switching transistors Trl to Tr3, each of which is composed of a P-channel MOS transistor and an N-channel MOS transistor, and the input side of the first transistor Trl is connected to an internal circuit and receives an input signal Vin. , the input side of the second transistor Tr2 is connected to the power supply Vcc via a resistor Rl, the input side of the third transistor Tr3 is connected to the ground G via a resistor R2, and the output side of each transistor Trl to Tr3 is Both are connected to the buffer circuit 5.

Complementary output signals Xo and Yo are output from the demultiplexer 2 to the gate of the first transistor Trl, and when the output signal Xo is at L level, the first transistor Trl is turned on and the input signal Vin from the internal circuit is buffered. It is output to circuit 5.

Complementary output signals Xl and Yl are outputted from the demultiplexer 2 to the gate of the second transistor Tr2, and when the output signal X1 is at L level, the first transistor Tr2 is turned on, and the buffer circuit 5 is supplied with H level from the power supply Vcc. signal is output.

Complementary output signals X2 and Y2 are outputted from the demultiplexer 2 to the gate of the third transistor Tr3, and when the output signal X2 is at L level, the first transistor Tr3 is turned on and an L level signal is sent to the buffer circuit 5. Output.

Now, in the output circuit 1 of the semiconductor integrated circuit configured as described above, when checking the H level output voltage of the output signal Vout, the input terminal S1 of the demultiplexer 2 is inputted with an H level, and the input terminal S2 is inputted with an L level. When an input signal is input, only the output signal X1 becomes L level among the output signals XO, XI, and X2, so the transistor Tr2 in each output circuit 1 is turned on and the buffer circuit 5 is
Since a high level signal is input and an H level output signal Vout is output from the output terminal of the buffer circuit 5, if the voltage value of this output signal Vout is measured, the output of each output circuit 1 when the H level is output is You can check whether the voltage is appropriate.

On the other hand, when checking the L level output voltage of the output signal Vout of each output circuit 1, when inputting an H level input signal to the human input terminal S2 of the demultiplexer 2 and an L level input signal to the same terminal S1 from the outside, each output signal XO . Therefore, this output signal V
By measuring the voltage value of out, it is possible to check whether the output voltage of each output circuit 1 when outputting L level is appropriate.

On the other hand, after the DC test is completed, if L-level input signals are input to both input terminals Sl and S2 of the demultiplexer 2, only the output signal XO of each output signal XO, XI, and X2 becomes L level. Therefore, the transistor Tri
is turned on, the input signal Vin from the internal circuit is output to the buffer circuit 5, and the output signal Vo is output from the buffer circuit 5.
Output as ut.

As described above, in this semiconductor integrated circuit, the pair of input terminals S of the demultiplexer 2 can be connected without operating the internal circuit.
By inputting an H level signal to one of L and S2 and an L level signal to the other, it is possible to simultaneously output H level or L level output signals to the output terminals of multiple output circuits l, so that the internal circuits can be operated. It is no longer necessary to provide a test pattern for causing the output circuit 1 to output an H level or L level output signal, and there is no need to operate the internal circuit based on that test pattern, improving the throughput of DC tests. be able to.

〔Effect of the invention〕

As described in detail above, the present invention provides a semiconductor integrated circuit that can improve the throughput of DC tests since it is possible to output an H level or L level output signal from the output circuit without operating the internal circuit. Demonstrates excellent effects that can be achieved.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a circuit diagram showing a demultiplexer of one embodiment, and Fig. 4 is the operation of the demultiplexer. FIG. 5 is a circuit diagram showing an output circuit of an embodiment. In the figure, l is the output circuit, 5 is the buffer circuit, and 6'! The selection circuit T'n is an input terminal, V'n is an input voltage, VH is an H level signal, and VL is an L level. Tr is a switching element (transistor) and Sin is an external control signal.

Claims (1)

[Scope of Claims] 1. An output circuit (
1), a selection circuit (6) is interposed between the input terminal (Tin) of the output circuit (1) and the buffer circuit (5), and the selection circuit (6) is connected to the input terminal (Tin) of the output circuit (1). An input signal (Vin), an H level signal (VH), and an L level signal (VL) input from the input terminal (Tin) are supplied to the selection circuit (6) based on the external control signal (Sin). A semiconductor integrated circuit comprising a switching element (Tr) that selects one of the signals and outputs the selected signal to the buffer circuit (5).