JPH02311012A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the deterioration in the duty ratio of an input clock signal by providing a duty variable circuit varying the duty ratio of an input clock signal and providing at least one clock terminal in one and same substrate to the output of the variable circuit. CONSTITUTION:An external clock signal is inputted from an input terminal 2 of a semiconductor chip 1 and inputted to a duty variable circuit 4 via a buffer 3. The variable circuit 4 outputs a clock signal CL2 with a different duty with respective to that of the inputted clock signal CL1 depending on selector signals S1, S2 from selector signal terminals 5, 6. The clock signal CL1 from the buffer 3 and the clock signal CL2 from the circuit 4 are inputted to the clock terminal of the internal circuit provided in the chip 1. Thus, a waveform resulting from correcting the duty cycle of the clock signal is supplied to the circuit operated by a 1/2 clock signal thereby preventing the deterioration in the duty ratio of the clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit that operates in synchronization with a clock signal.

[Conventional technology]

As shown in FIG. 7, a conventional semiconductor integrated circuit includes a semiconductor chip 1. An external clock signal input from an input terminal 2 provided in the circuit is input to each internal buffer 15 from its output via an input buffer 3, and is supplied to a clock terminal of an internal circuit. In addition, when outputting the clock signal to the outside of the semiconductor chip 1, it is supplied from the output of the input buffer 3 to the input of the output buffer 14, and the clock signal is supplied to the output terminal 14.
It was outputting from.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit described above, a clock signal is supplied to each circuit through an input buffer and an internal buffer, so the rise time and fall time of the input buffer and internal buffer signals may be designed to be different, or
There is a drawback that manufacturing variations, especially when the threshold values of MOSFETs become unbalanced, further increase the difference between the rise time and fall time of the input clock signal, and the duty ratio of the clock signal deteriorates.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention includes a variable duty circuit that can vary the duty of an input clock signal by an external selector signal, and at least one clock provided on the same substrate to which the output of the variable duty circuit is connected. It has a terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention.

As shown in FIG. 1, an external clock signal input from an input terminal 2 provided on a semiconductor chip 1 is input to a variable duty circuit 4 via an input buffer 3. As will be described later, the variable duty circuit 4 outputs a clock signal CL2 having a different duty with respect to the clock signal CL input according to the values of the selector signal Sl and S2 from the selector signal terminal 5.6. The clock signal CL from the input buffer 3 and the clock signal CL2 from the variable duty circuit 4 are input to clock terminals of internal circuits provided in the semiconductor chip 1, respectively.

FIG. 2 is a detailed block diagram of the variable duty circuit shown in FIG. 1.

As shown in FIG. 2, the signal directly input from the input terminal 11 to the multiplexer 10 is referred to as a clock signal D1, and the clock signal D1 from the input terminal 11 is used as the clock signal input to the multiplexer 10 via the delay buffer 7. A signal D2 is a signal in which the clock signal D1 from the input terminal 11 and the clock signal D2 output from the delay buffer 7 are input to the multiplexer 10 via the OR circuit 8, and a clock signal D3 is the clock signal from the input terminal 11. D
I and the clock signal D2 output from the delay buffer 7 are AN
A signal input to multiplexer 10 via D circuit 9 is used as clock signal D4, and selector terminals 5 and 6 of multiplexer 10 are used as external terminals.

FIG. 3 is a waveform diagram of a clock signal for explaining the operation of the variable duty circuit of FIG. 2.

As shown in FIG. 3, these are the waveforms of the clock signals D2, D3, and D4 when the signal input to the input terminal 11 is the clock signal D1 with a duty of 50%.

FIG. 4 is a diagram showing the correlation between the clock signal of the variable duty circuit of FIG. 2 and the truth value of the selector signal.

As shown in FIG. 4, by associating the truth values of the selector signals S, .

Next, FIG. 5 is a block diagram of a second embodiment of the present invention.

As shown in FIG. 5, in the second embodiment, a clock signal is supplied from an input terminal 2 via an input buffer 3, one of which is supplied as a clock signal CLI to the internal circuit of the semiconductor chip 1b, and the other is supplied to a variable duty circuit. 4 and its output is sent to the output terminal 1 of the semiconductor chip 1b via the output buffer 13.
Connected to 4.

FIG. 6 is a block diagram of a clock signal supply system formed using the second embodiment of FIG. 5.

As shown in FIG. 6, the output terminal 14 of the semiconductor chip 1b
By outputting the output clock signal of the variable duty circuit at the same time, it is possible to provide a semiconductor integrated circuit that can output a lock signal with a good duty ratio, so that a lock signal supply system as shown in FIG. 6 can be constructed.

〔Effect of the invention〕

As explained above, the semiconductor integrated circuit of the present invention has a built-in circuit that changes the duty of an input clock signal using a selector signal from an external terminal, and the output of this circuit is transmitted to a part of the circuit in the semiconductor chip, or By supplying the clock signal to the clock terminals of all circuits, it is possible to supply a waveform with the duty of the clock signal corrected to circuits that operate in half clock mode, so even if the duty of the input clock signal is bad, the clock signal remains normal. This has the effect of improving the reliability of the operation.

Brief Description of the Drawings Fig. 1 is a block diagram of the first embodiment of the present invention, Fig. 2 is a detailed block diagram of the variable duty circuit shown in Fig. 1, and Fig. 3 is an operation of the variable duty circuit shown in Fig. 2. FIG. 4 is a diagram showing the correlation between the clock signal of the variable duty circuit of FIG. 2 and the truth value of the selector signal, and FIG. 5 is a diagram of the second embodiment of the present invention. 6 is a block diagram of a clock signal supply system formed using the second embodiment of FIG. 5, and FIG. 7 is a block diagram of an example of a conventional semiconductor integrated circuit.

1.1. ~1d...Semiconductor chip, 2...Input terminal, 3...Input buffer, 4...Duty variable circuit, 5.6...Selector signal terminal, 7...Delay buffer, 8...・OR circuit, 9...AND circuit, 10...
・Multiplexer, 11...Input terminal, 12...Output terminal, 13...Output buffer, 14...Output terminal, 15...Internal buffer, CL, , C12...Clock signal, DI~ D4...Clock signal, S,, S2
...Selector signal.

Claims (1)

[Claims] It is characterized by having a variable duty circuit that can vary the duty of an input clock signal by an external selector signal, and at least one clock terminal provided within the same board to which the output of the variable duty circuit is connected. semiconductor integrated circuits.