JPH0355617A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To prevent a state where the noise signal is outputted from an output terminal and to prevent the malfunction of an external device by separating the output terminal from a common power supply and a Gnd in a period when the output signal of an output buffer is changed. CONSTITUTION:The output terminals 8 - 10 change at one time when 1st input signals 3 - 5 change. A 3rd input signal 7 turns off an N channel MOSTR 18 and a p channel MOSTR 17 in a period when the outputs of the terminals 8 - 10 are changed. Therefore the output of an output buffer 15 is separated from an output terminal 11 in a period when the output signals of the output buffers 12 - 14 connected to the same power supply and the same Gnd are changed simultaneously. Thus it is possible prevent such a state where the noise signals produced via the power supply and the Gnd at the change of the output of buffers 12 - 14 are outputted via the terminal 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to an output buffer circuit. [Prior Art] Conventionally, this type of output buffer circuit is connected to a common power supply 1 and Gnd2 as shown in FIG.
4, 5, and 8 were output to output terminals 8, 9, 10, and 11 through output buffers 12, 13, 14, and 15. [Problem to be solved by the invention] The conventional output buffer circuit described above has a common power supply, Gnd
Therefore, when the output signals of many output buffer circuits change at the same time, a large current usually flows temporarily in the power supply and Gnd. In an output buffer circuit using a CMOS circuit, when the output signal changes, a large current flows as a tributary current, and the potential of the power supply and Gnd changes, causing noise 2 shown in Figure 4.
1 may occur. Therefore, when the number of output buffer circuits that change simultaneously increases or when the speed increases, the noise 2l becomes noticeable, and there is a drawback that devices supplied with noise-containing signals malfunction. [Means for Solving the Problems] The semiconductor integrated circuit of the present invention has a group of output buffers having a plurality of output change timings and a common power source, Gnd, in which the other output terminals are connected to the power source at one output change timing. Gn
It has a means to separate it from d. [Example] Next, the present invention will be explained with reference to the drawings. FIG. 1 shows an output circuit according to an embodiment of the present invention. Output buffer 1
2, 13, 14.15 are connected to power supply 1, Gnd2,
The output buffers 12, 13, and 14 each receive the first input signal 3.
, 4.5 are input. Also, a second
, and the output of the output buffer 15 is connected to the output terminal 11 through a P-channel MOS transistor 17 and an N-channel MOS transistor 18. Also, the third input signal 7 is a P-channel MOS}
It is input to transistor 17 and inverter 16. This will be explained with reference to Figure 2, which is an input/output waveform diagram of Figure 1.
As the first input signals 3, 4.5 change, the output terminals 8, 9.10 change simultaneously.

The third input signal 7 turns off the N-channel MOS transistor 18 and the P-channel MOS transistor 17 during the period when the outputs of the output terminals 8, 9, and 10 change. , therefore the output buffers 12,1 connected to the same power supply, Gnd
During the period when the output signals of 3.14 change simultaneously, the output of the output buffer l5 is disconnected from the output terminal 11. Therefore, noise signals generated when the outputs of the output buffers 12, 13, and 14 change through the power supply and Gnd are prevented from being output from the output terminal 1l. FIG. 5 is an output circuit diagram of another embodiment of the present invention. Output buffers 12, 13, and 14 are connected to power supplies 1 and Gnd2, and receive first input signals 3, 4, and 5, respectively, and output terminals 8. ,9.10 is connected. The second input signal 6 is input to an output buffer of the clocked inverter type composed of a P-channel MOS transistor 17.19 and an N-channel MOS transistor 18.19.

The third input signal 7 is a P-channel MOS} transistor 1
7, is input to the inverter 16.

Therefore, as in the first embodiment, the third input signal 7 is sent to the output terminal 8.
, 9. The period during which the output signals of 10 change N-channel MO
S} transistor 18, P channel MOS} transistor 17 is turned off. As in the first embodiment, noise signals are prevented by turning off the N-channel MOS transistor 8 and the P-channel MOS transistor 17.

〔Effect of the invention〕

As explained above, in the present invention, the output terminals are connected to a common power supply during periods when the output signals of other output buffers change. By separating it from Gnd, noise signals are prevented from being output from the output terminal, and malfunctions of external devices are prevented.

[Brief explanation of drawings]

Fig. 1 is an output circuit diagram of the first embodiment of the present invention, Fig. 2 is an input/output waveform diagram of Fig. 1, Fig. 3 is a conventional output circuit diagram, and Fig. 4 is a conventional output circuit diagram.
The figure is an output waveform diagram of Figure 3, and Figure 5 is an output circuit diagram of the second embodiment. l...Power supply, 2...Gnd, 3, 4.
5...First input signal, 6...Second input signal, 7...Third input signal, 8, 9, 1
0.11...Output terminal, 12, 13, 14.1
5... Output huffer, 16... Inverter. 17, 19...P channel MOS transistor, 18, 20...N channel MOS transistor, 21...Noise.

Claims (1)

[Claims] A semiconductor circuit characterized in that, in a group of output buffers having multiple output change timings and connected to a common power supply, other output terminals are isolated from the power supply at the time of one output change timing.