KR100336556B1 - Clock delay control circuit - Google Patents

Clock delay control circuit Download PDF

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KR100336556B1
KR100336556B1 KR1019970071269A KR19970071269A KR100336556B1 KR 100336556 B1 KR100336556 B1 KR 100336556B1 KR 1019970071269 A KR1019970071269 A KR 1019970071269A KR 19970071269 A KR19970071269 A KR 19970071269A KR 100336556 B1 KR100336556 B1 KR 100336556B1
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clock signal
delay
control circuit
output
delayed
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KR1019970071269A
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Korean (ko)
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KR19990051854A (en
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김연화
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs

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  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

PURPOSE: A clock signal controlling circuit is provided to control delay times of clock signals transferred to device blocks by selectively outputting clock signals of different delay times. CONSTITUTION: A plurality of delay parts(D1-D3) are connected in series to an input terminal of a clock signal(CLK). A plurality of tri-state buffers(B11-B14) have control terminals connected to a register(15) and are connected to the input terminal and output terminals of the delay parts, respectively. Output terminals of the tri-state buffers are connected to input terminals(I1-I4) of a plurality of multiplexers(16-19), respectively. Output terminals of the multiplexers(16-19) are connected to a plurality of device blocks(20-23).

Description

클럭신호 제어회로{Clock delay control circuit}Clock signal control circuit

본 발명은 클럭신호 제어회로에 관한 것으로, 하나의 클럭신호를 다수개의 디바이스 블록으로 전달할 때 디바이스 블록의 특성에 따라 각각 다른 지연시간을 갖도록 하는 클럭신호 제어회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal control circuit, and more particularly, to a clock signal control circuit having different delay times according to characteristics of a device block when one clock signal is transmitted to a plurality of device blocks.

클럭신호는 디지탈 논리회로의 필수적인 신호로서 모든 구성요소의 동작 타이밍의 기준이 되는 신호이다. 그러나 모든 구성요소가 하나의 클럭신호에 동기되어 동작하는 것은 아니다. 어떤 구성요소들은 기준이 되는 클럭신호를 다소 지연시켜서 사용해야 하는 경우가 있으며, 때로는 기준이 되는 클럭신호보다 앞선 위상을갖는 클럭신호를 필요로할 때도 있다. 앞선 위상의 클럭신호 역시 기준 클럭신호를 지연시켜서 만들어낸다.The clock signal is an essential signal of the digital logic circuit and serves as a reference for the operation timing of all components. However, not all components operate in synchronization with one clock signal. Some components may need to delay the reference clock signal to some extent, and sometimes require a clock signal having a phase ahead of the reference clock signal. The clock signal of the preceding phase is also produced by delaying the reference clock signal.

클럭신호를 지연시키기 위한 지연수단으로는 시모스 인버터가 가장 일반적으로 사용된다. 시모스 인버터는 전원전압과 접지 사이에 피모스 트랜지스터와 엔모스 트랜지스터를 직렬 연결하여 구성한다. 이 시모스 인버터의 피모스 트랜지스터와 엔모스 트랜지스터의 전류구동능력을 조절하면 입력신호와 출력신호 사이에 적절한 시간지연을 발생시킬 수 있다. 또 이와 같은 시모스 인버터를 다단으로 연결하여 지연시간의 크기를 증가시킬 수도 있다.The CMOS inverter is most commonly used as a delay means for delaying a clock signal. The CMOS inverter is configured by connecting a PMOS transistor and an NMOS transistor in series between a power supply voltage and a ground. By adjusting the current driving capability of the PMOS transistors and the NMOS transistors of the CMOS inverter, an appropriate time delay can be generated between the input signal and the output signal. In addition, the size of the delay time may be increased by connecting the CMOS inverter in multiple stages.

도 1은 지연수단에 의해 지연된 클럭신호 또는 본래의 클럭신호를 입력받아 동작하는 다수개의 디바이스 블록들을 나타내었다. 도 1에 나타낸 바와 같이 디바이스 블록(1)에는 지연수단인 버퍼(B1)를 통하여 소정 시간동안 지연된 클럭신호(CLK)가 입력된다. 또 다른 디바이스 블록(2)에도 지연수단인 버퍼(B1)를 통하여 소정 시간동안 지연된 클럭신호(CLK)가 입력된다. 이와 달리 나머지 세개의 디바이스 블록(3∼5)에는 아무런 지연수단도 경유하지 않는 본래의 클럭신호(CLK)가 그대로 입력된다.1 illustrates a plurality of device blocks that operate by receiving a delayed clock signal or an original clock signal by a delay means. As shown in FIG. 1, the clock signal CLK delayed for a predetermined time is input to the device block 1 through the buffer B1 as a delay means. The clock signal CLK delayed for a predetermined time is also input to the other device block 2 through the buffer B1 as a delay means. On the other hand, the original clock signal CLK without any delay means is input to the remaining three device blocks 3 to 5 as they are.

그러나 이와 같은 종래의 클럭신호 지연방법은 지연수단의 지연시간이 고정되어 있기 때문에 필요에 따라 지연시간을 가변시킬수 없다. 만약 기존의 회로에 새로운 지연시간을 갖는 지연수단을 부가할 필요가 있을 때에는 새로운 설계 및 제조과정이 요구된다.However, in such a conventional clock signal delay method, since the delay time of the delay means is fixed, the delay time cannot be changed as necessary. If it is necessary to add a delay means having a new delay time to an existing circuit, a new design and manufacturing process is required.

따라서 본 발명은 다수개의 지연수단을 구비하고 각각의 지연수단에서 출력되는 서로 다른 지연시간을 갖는 다수개의 클럭신호를 선택수단을 이용하여 선택적으로 출력시켜서 필요한 디바이스 블록에 전달되도록 함으로써 각각의 디바이스 블록에 전달되는 클럭신호의 지연시간을 필요에 따라 적절히 제어할 수 있는 클럭신호 제어회로를 제공하는데 그 목적이 있다.Accordingly, the present invention includes a plurality of delay means and a plurality of clock signals having different delay times outputted from the respective delay means are selectively outputted by using the selection means to be delivered to the required device blocks. It is an object of the present invention to provide a clock signal control circuit capable of appropriately controlling the delay time of a transmitted clock signal.

도 1은 종래의 클럭신호 전달경로를 나타낸 블록도.1 is a block diagram showing a conventional clock signal transmission path.

도 2는 본 발명에 따른 클럭신호 제어회로를 나타낸 블록도.2 is a block diagram showing a clock signal control circuit according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

B1, B2 : 버퍼 B11∼B14 : 트라이스테이트 버퍼B1, B2: Buffers B11 to B14: Tri-State Buffers

1∼5, 20∼23 : 디바이스 블록 D1∼D3 : 지연부1 to 5, 20 to 23: device blocks D1 to D3: delay unit

15 : 레지스터 S0∼S41 : 선택신호15: registers S0 to S41: selection signal

이와 같은 목적의 본 발명은 클럭신호를 입력받아 이를 지연시켜서 출력하는 지연수단과; 소정의 선택신호가 입력되고, 상기 클럭신호와 상기 지연수단에 의해 지연된 클럭신호를 입력받아 상기 선택신호에 따라 상기 클럭신호와 상기 지연된 클럭신호 가운데 하나를 선택하여 출력하는 선택수단을 포함하여 이루어진다.The present invention for this purpose includes a delay means for receiving a clock signal and delaying and outputting it; And a selection means for receiving a predetermined selection signal, receiving the clock signal and the clock signal delayed by the delay means, and selecting one of the clock signal and the delayed clock signal according to the selection signal.

이와같이 이루어진 본 발명의 바람직한 실시예를 도 2를 참조하여 설명하면 다음과 같다. 도 2는 본 발명에 따른 클럭신호 제어회로를 나타낸 블록도이다. 도 2에 나타낸 바와 같이 클럭신호(CLK)가 직렬 연결된 세 개의 지연부(D1∼D3)를 거치면서 서로 다른 세 개의 지연된 클럭신호가 만들어진다. 본래의 클럭신호(CLK)를 포함하면 사용가능한 클럭신호는 모두 네개이다. 첫 번째 지연부(D1)에서 출력된 지연된 클럭신호는 다음 지연부(D2)를 통하여 출력되면서 더욱 지연된 클럭신호가 된다. 지연부(D2)에서 출력된 클럭신호는 또 다른 지연부(D3)에 의해 더욱 지연된 클럭신호가 된다. 따라서 최초의 클럭신호(CLK)가 각각의 지연부(D1∼D3)를 거치면서 더욱 지연된 클럭신호가 되는 것이다.When explaining the preferred embodiment of the present invention made as described above with reference to FIG. 2 is a block diagram illustrating a clock signal control circuit according to the present invention. As shown in FIG. 2, three different delayed clock signals are generated while the clock signals CLK are connected to three delay units D1 to D3 connected in series. Including the original clock signal CLK, there are four clock signals available. The delayed clock signal output from the first delay unit D1 is output through the next delay unit D2 to become a delayed clock signal. The clock signal output from the delay unit D2 becomes a clock signal further delayed by another delay unit D3. Therefore, the first clock signal CLK becomes a clock signal which is further delayed through the respective delay units D1 to D3.

최초의 클럭신호(CLK)를 포함하여 각각의 지연부(D1∼D3)에서 출력되는 지연된 클럭신호들은 각각 트라이스테이트 버퍼(B11∼B14)를 통하여 다음단으로 전달된다. 각각의 트라이스테이트 버퍼(B11∼B14)는 소정의 선택신호(S0)(S1)에 의해 제어되는 레지스터(15)로부터 출력되는 제어신호에 의해 온·오프된다. 따라서 만약 레지스터(15)에서 R1, R2만이 논리값 1의 신호가 되고, 나머지 R3, R4는 논리값 0의 신호가 된다면 트라이스테이트 버퍼(B11)(B12)만이 턴 온되어 클럭신호(CLK)와 지연부(D1)의 출력신호만이 다음단으로 전달된다.Delayed clock signals output from the respective delay units D1 to D3 including the first clock signal CLK are transferred to the next stage through the tristate buffers B11 to B14, respectively. Each of the tri-state buffers B11 to B14 is turned on and off by a control signal output from the register 15 controlled by the predetermined selection signal S0 (S1). Therefore, if only R1 and R2 become the logic value 1 signal in the register 15, and the remaining R3 and R4 become the signal of the logic value 0, only the tri-state buffers B11 and B12 are turned on so that the clock signal CLK Only the output signal of the delay unit D1 is transferred to the next stage.

각각의 트라이스테이트 버퍼(B11∼B14)에서 출력되는 지연된 클럭신호들(실제로 트라이스테이트 버퍼 B11에서 출력되는 신호는 지연된 클럭신호가 아니라 본래의 클럭신호이다)은 네 개의 멀티플렉서(16∼19)에 각각 입력된다. 각각의 멀티플렉서는 모두 네 개의 입력단자를 갖고있어 네개의 트라이스테이트 버퍼(B11∼B14)에서 출력되는 지연된 클럭신호들이 입력된다. 각각의 멀티플렉서(16∼19)는 서로 다른 조합의 선택신호(S10∼S41)에 의해 출력신호가 결정된다. 멀티플렉서(16)에는 한 쌍의 선택신호(S10)(S11)가 입력되고, 멀티플렉서(17)에는 역시 한 쌍의 선택신호(S20)(S21)가 입력되며, 멀티플렉서(18)에는 한 쌍의 선택신호(S30)(S31)가 입력되고, 멀티플렉서(19)에는 한 쌍의 선택신호(S40)(S41)가 입력된다. 따라서 각각의 멀티플렉서에 입력되는 선택신호를 적절히 제어하면 입력된 네 개의 지연된 클럭신호 가운데 하나를 선택하여 출력시킬수 있다.Delayed clock signals output from the respective tristate buffers B11 to B14 (actually, signals output from the tristate buffer B11 are not the delayed clock signals but the original clock signals) are respectively provided to the four multiplexers 16 to 19. Is entered. Each multiplexer has four input terminals so that delayed clock signals output from four tri-state buffers B11 to B14 are input. In each of the multiplexers 16 to 19, the output signals are determined by different combinations of selection signals S10 to S41. A pair of selection signals S10 and S11 are input to the multiplexer 16, a pair of selection signals S20 and S21 are also input to the multiplexer 17, and a pair of selections are input to the multiplexer 18. Signals S30 and S31 are input, and a pair of selection signals S40 and S41 are input to the multiplexer 19. Therefore, if the selection signal input to each multiplexer is properly controlled, one of the four delayed clock signals inputted can be selected and output.

각각의 멀티플렉서(16∼19)에서 출력되는 임의의 지연된 클럭신호는 다수개의 디바이스 블록(20∼23)에 전달된다. 멀티플렉서(16)에서 출력되는 지연된 클럭신호는 디바이스 블록(20)에 전달되며, 멀티플렉서(17)에서 출력되는 지연된 클럭신호는 디바이스 블록(21)에 전달되며, 멀티플렉서(18)에서 출력되는 지연된 클럭신호는 디바이스 블록(22)에 전달되며, 멀티플렉서(19)에서 출력되는 지연된 클럭신호는 디바이스 블록(23)에 입력된다. 각각의 디바이스 블록에 다른 지연시간을 갖는 클럭신호를 공급하고자 할 때에는 멀티플렉서의 선택신호를 다르게 조합하여 다른 클럭신호를 선택할 수 있다.Any delayed clock signal output from each multiplexer 16-19 is delivered to a plurality of device blocks 20-23. The delayed clock signal output from the multiplexer 16 is transmitted to the device block 20, and the delayed clock signal output from the multiplexer 17 is transmitted to the device block 21 and the delayed clock signal output from the multiplexer 18. Is transmitted to the device block 22, and the delayed clock signal output from the multiplexer 19 is input to the device block 23. When a clock signal having a different delay time is supplied to each device block, different clock signals may be selected by different combinations of the selection signals of the multiplexer.

따라서 본 발명은 다수개의 지연수단을 구비하고 각각의 지연수단에서 출력되는 서로 다른 지연시간을 갖는 다수개의 클럭신호를 선택수단을 이용하여 선택적으로 출력시켜서 필요한 디바이스 블록에 전달되도록 함으로써 각각의 디바이스 블록에 전달되는 클럭신호의 지연시간을 필요에 따라 적절히 제어할 수 있는 클럭신호 제어회로를 제공한다.Accordingly, the present invention includes a plurality of delay means and a plurality of clock signals having different delay times outputted from the respective delay means are selectively outputted by using the selection means to be delivered to the required device blocks. Provided is a clock signal control circuit capable of appropriately controlling the delay time of a transmitted clock signal as necessary.

Claims (1)

클럭신호(CLK)입력단에 다수개의 지연부(D1∼D3)를 직렬연결하고, 상기 클럭신호(CLK)입력단과 상기 다수개의 지연부(D1∼D3)의 출력단에 각각 제어단이 레지스터(15)에 연결된 다수개의 트라이스테이트 버퍼(B11∼B14)를 연결하고, 상기 다수개의 트라이스테이트 버퍼(B11∼B14)의 출력단은 다수개의 멀티플렉서(16∼19)의 입력단(I1∼I4)에 연결하고, 상기 다수개의 멀티플렉서(16∼19)의 출력단은 각각 다수개의 디바이스 블록(20∼23)에 연결구성 된 것이 특징인 클럭신호 제어회로.A plurality of delay units D1 to D3 are connected in series with the clock signal CLK input terminal, and a control terminal is provided at the output terminal of the clock signal CLK input terminal and the plurality of delay units D1 to D3, respectively. A plurality of tristate buffers B11 to B14 connected to the plurality of tristate buffers B11 to B14, and an output terminal of the plurality of tristate buffers B11 to B14 is connected to input terminals I1 to I4 of the multiplexers 16 to 19, respectively. A clock signal control circuit, characterized in that the output terminals of the multiplexers 16 to 19 are connected to a plurality of device blocks 20 to 23, respectively.
KR1019970071269A 1997-12-20 1997-12-20 Clock delay control circuit KR100336556B1 (en)

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KR100336556B1 true KR100336556B1 (en) 2002-08-28

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KR1019970071269A KR100336556B1 (en) 1997-12-20 1997-12-20 Clock delay control circuit

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Publication number Priority date Publication date Assignee Title
US6578155B1 (en) * 2000-03-16 2003-06-10 International Business Machines Corporation Data processing system with adjustable clocks for partitioned synchronous interfaces

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04268811A (en) * 1991-02-22 1992-09-24 Yokogawa Hewlett Packard Ltd Timing generator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04268811A (en) * 1991-02-22 1992-09-24 Yokogawa Hewlett Packard Ltd Timing generator

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