JPH0194721A - Output circuit device - Google Patents

Abstract

PURPOSE:To suppress the quick change of a transient current at the time of an output buffer action and to reduce a power source noise by driving a second inverter with a first inverter output and driving a third inverter with a signal delayed by a delaying signal. CONSTITUTION:A signal inputted from a terminal IN is inverted by an inverter 1 and enters an inverter 7. The output of the inverter 7 smoothly changes the potential of a bonding pad 5. The signal is inputted through a delaying circuit 9 composed of the output transfer gate of the inverter 1 to an inverter 8, delayed to the inverter 7 and an action is started. Consequently, an external load connected to the pad 5 is driven by two inverters 7 and 8, the quick change of the transient current is suppressed and the power source noise can be reduced. The number of transistors to be used is reduced, and the occupied area and the cost can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit of an LSI having a CMO5 configuration.

[Conventional technology]

FIG. 3 is a circuit diagram showing a conventional output circuit device disclosed in, for example, Japanese Unexamined Patent Publication No. 62-88617.
4 is a high state buffer), 5 is a bonding pad for outputting a signal from the LSI internal circuit to the outside of the LSI, and 6 is an LSI including this conventional example. 1G.

Chrysanthemum is a p-channel ivMO8) transistor for output, 11゜ is an n-channel transistor for output, and C is NAND.
The gate C is a NOR gate. To configure 2 and 8 inverters, two transistors are required per inverter;
Four transistors are required to form each R gate. Therefore, 16 transistors are required to construct the output circuit device of FIG.

Next, the operation will be explained. Consider a case where a signal having a waveform as shown in FIG. 4 is input to the input terminal IN. Input signal goes from Low (Vss) to High (Vdd)
When the transition occurs, the signal input to the input terminal IN is inverted by the inverter 1 and output to the bonding pads 5, j5, and the outside of LsI.

On the other hand, the above input signal is input to the inverter 8, and after a delay by the inverter 8, the potential of the node 8A is changed from High to Low (Fig. 4 ■). After the potential of 8B is delayed by inverter 1 and inverter 2, it becomes Lo
It changes from w to High (Fig. 4 ■). Therefore, N.A.
The output 1 of the ND gate 41 and the output of the NOR gate 41 are respectively shown as 4A in FIG. NAND gate C%
The outputs of the NOR gates 6 are connected to p-channel transistors and n-channel transistors, respectively, and during the period indicated by 4A in FIG. OF
F%n channel μ transistor d is in ON state)
The load external to the LSI connected to this output circuit device through the bonding pad 6 is amended by the n-channel transistor 11 and 41, and the potential of the bonding pad 6 also drops suddenly. In the period indicated by 4B, both the p-channel lV transistor 43 and the n-channel transistor d are turned off, and the tristate buffer 4 enters a high impedance state.

Since the load outside the LSI is driven only by the n-channel transistor H, the potential drop is gradual.

When the input signal transitions from High to Low, p channel/L/- during the 4C period by a similar process.
) Due to the fungistor 10 and chrysanthemum, the load is driven only by the hull channel transistor 10 during 4D.

From the above, the change in the potential of the bonding pad 5 is as shown in FIG. 4 (■).

Therefore, rapid changes in transient current during operation of the output circuit device can be suppressed, and power supply noise can be reduced.

[Problem that the invention seeks to solve]

In the conventional example shown in Fig. 4, the number of transistors used in the tristate e-buffer is large (16 in the conventional example above).
This increases the area occupied on the chip, which is disadvantageous when a large number of output circuits are required.

The present invention has been made to solve the above problems, and it reduces power supply noise caused by overshading and undershoot of the output potential, reduces the number of transistors required to configure the output circuit, and reduces the number of transistors required to configure the output circuit. The object of the present invention is to obtain an output circuit device that occupies a small area.

[Means for solving problems]

The output circuit device according to the present invention drives a second inverter with the output of the first inverter, and drives the third inverter with a signal obtained by delaying the output of the first inverter by a delay circuit. A means is provided for suppressing sudden changes in transient current during output buffer operation.

[Effect]

The delay circuit according to the present invention can shift the operation timing of the inverter, suppress sudden changes in transient current during output buffer operation, and reduce power supply noise.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 and 7.8 are CMOS inverters, and 9 is a transfer gate that operates as a delay circuit. Reference numerals 70 and 80 are p-channel/I/MOS transistors for output, and n and 81 are n-channel transistors for output.

Book! ! When a signal as shown in FIG. 2 is input to the winding example (FIG. 1), this signal is inverted by the inverter 1 and input to the inverter.

The output of the inverter 7 is connected to the bonding pad 6, and the position t of the bonding pad 5 begins to change slowly (periods 2A and 2C in FIG. 2), and the output of the inverter 1 is connected to the delay circuit 9. The signal is input to the inverter 8 via the inverter 8, and the inverter 8 starts operating together with the inverter 7.

After inverter 8 operates, bonding pad 6
The external load of the LSI connected to this output circuit device through the inverter 7.8 is driven by the two inverters 7 and 8 (see FIG. 2B).

2D period). Therefore, the potential of the bonding pad 6 changes gradually at first, as shown in FIG. 2, and rapid changes in transient current can be suppressed.

In the above embodiment, a transfer circuit is used as a delay circuit.
Although a gate was used, the output of inverter 7 and inverter 8
The inputs of the circuit may be connected through a series resistor, and this may be used as a delay circuit.

〔Effect of the invention〕

As described above, according to the present invention, an output circuit device that suppresses sudden changes in transient current when an output buffer operates and reduces power supply noise can be realized using a smaller number of transistors (in the above embodiment) than in the past. 8), it is possible to keep the cost of an LSI that requires J many output circuits low.

[Brief explanation of the drawing]

Fig. 1 is a specific circuit diagram of one embodiment of the present invention, Fig. 2
, ■ are input/output characteristic diagrams of the output circuit device shown in FIG. 1, FIG. 3 is a specific circuit diagram of a conventional example, and FIGS. FIG. 3 is a diagram showing signal waveforms. 1, 2.3.7.8. ... Inverter, 4... Tri-state buffer, 5... Bonding pad, 6... LSI, 9... Delay circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) A first inverter whose input is a signal output from the LSI internal circuit to the outside, a second inverter whose input is the output of the first inverter, and whose input is connected to the output of the first inverter. 1. An output circuit device comprising: a delay circuit configured to provide a delay circuit; and an output buffer comprising a third inverter having an input connected to an output of the delay circuit. (2) The output circuit device according to claim 1, wherein the operation timings of the second inverter and the third inverter are different from each other.