WO2016112780A1 - Multi-chip packaging structure and electronic device - Google Patents

Multi-chip packaging structure and electronic device Download PDF

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Publication number
WO2016112780A1
WO2016112780A1 PCT/CN2015/099532 CN2015099532W WO2016112780A1 WO 2016112780 A1 WO2016112780 A1 WO 2016112780A1 CN 2015099532 W CN2015099532 W CN 2015099532W WO 2016112780 A1 WO2016112780 A1 WO 2016112780A1
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Prior art keywords
chip
signal
package structure
ground
structure according
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PCT/CN2015/099532
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French (fr)
Chinese (zh)
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刘雪春
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深圳信炜科技有限公司
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60Protection against electrostatic charges or discharges, e.g. Faraday shields
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Definitions

  • the invention relates to a multi-chip package structure and an electronic device.
  • electronic devices such as mobile phones, tablet computers, etc.
  • electronic devices are usually provided with a plurality of functional chips.
  • each functional chip is generally packaged separately, resulting in occupying a large volume of the electronic device and causing high cost of the electronic device.
  • the present invention provides a multi-chip package structure and an electronic device having a multi-chip package structure.
  • the present invention provides the following technical solutions:
  • a multi-chip package structure comprising:
  • a first chip including a ground terminal
  • a second chip including a signal transmission end, the signal transmission end is connected to the ground end, the signal transmission end outputs a first signal to the ground end, and the first signal is used as a ground signal of the first chip Wherein the first signal is a varying signal.
  • the voltage of the first chip varies with the change of the ground signal.
  • the voltage of the first chip increases as the voltage of the ground signal increases, and decreases as the voltage of the ground signal decreases.
  • the first chip further includes a power terminal, and the power terminal receives the second signal.
  • the voltage of the second signal is greater than the voltage of the first signal, and the second signal
  • the voltage difference of the first signal is the operating voltage of the first chip.
  • the power terminal is connected to the second chip, and the second chip provides a solution
  • the second signal is a changed signal.
  • the second chip further includes a ground end, the ground end of the second chip is connected to a device ground end of an electronic device, or the ground end of the second chip and the electronic device where the multi-chip package structure is located The device is grounded or a constant voltage is applied to the ground of the second chip.
  • the multi-chip package structure further includes a signal electrode made of a conductive material, and the signal electrode is disposed at least around the first chip.
  • the signal electrode is loaded with a third signal, the third signal being a varying signal.
  • the third signal is the same as the first signal.
  • the signal electrode is connected to a ground end of the first chip and a signal transmission end of the second chip.
  • the third signal changes synchronously with the first signal, and the magnitude of the change and the direction of the change are the same.
  • the third signal changes as the first signal changes.
  • the third signal increases as the first signal increases and decreases as the first signal decreases.
  • the magnitude of the amplitude change of the third signal is the same as the magnitude of the amplitude change of the first signal.
  • the multi-chip package structure includes a heat sink, the heat sink is made of a conductive material, the heat sink is used for heat dissipation, and is also used as the signal electrode.
  • the first chip and the second chip are both disposed on the heat sink, wherein a conductive layer is disposed between the first chip and the heat sink, and the second chip and the heat sink An insulating layer is provided between them.
  • the heat sink is connected to the ground end of the first chip through the conductive layer
  • the conductive layer is made of a conductive paste
  • the insulating layer is made of an insulating paste.
  • the multi-chip package structure further includes a substrate, the first chip and the second chip are disposed on the substrate, and the signal electrode is disposed on the substrate.
  • the signal electrode surrounds the first chip.
  • the signal electrode further surrounds the second chip.
  • the signal electrode is an entire layer of electrodes disposed between the first chip and the substrate, and is stacked with the first chip and the substrate, and the edge of the signal electrode is beyond the vertical stacking direction The edge of the first chip.
  • the first chip and the second chip are disposed on the same side or opposite sides of the substrate.
  • the first chip is a sensing chip
  • the second chip is a control chip
  • the first chip is a fingerprint sensing chip or a touch sensing chip.
  • the first chip includes a sensor board for capacitively coupling to a target object, the first chip performing a sensing operation by providing an excitation signal to the sensor board to drive the sensor board Obtaining predetermined information of the target object, wherein the excitation signal changes as the first signal changes.
  • the excitation signal increases as the first signal increases, and decreases as the first signal decreases.
  • the invention further provides a multi-chip package structure, comprising:
  • a first chip comprising a ground end for loading a varying signal
  • the second chip includes a ground terminal for loading a constant signal.
  • the second chip includes a signal transmission end, and the signal transmission end is connected to a ground end of the first chip for outputting the changed signal to a ground end of the first chip.
  • the present invention provides an electronic device comprising the multi-chip package structure of any of the above.
  • the invention further provides an electronic device comprising a multi-chip package structure and a device ground, the multi-chip package structure comprising:
  • a first chip comprising a ground end for loading a varying signal
  • the second chip includes a ground end connected to the ground end of the device.
  • the second chip includes a signal transmission end, and the signal transmission end is connected to a ground end of the first chip, and is configured to output the changed signal to the first chip. Ground terminal.
  • the electronic device comprises a power supply
  • the power supply comprises a positive pole and a negative pole
  • the negative pole is a ground end of the device.
  • the multi-chip package structure of the electronic device of the present invention not only integrates the first chip and the second chip, but also the ground terminal of the first chip is loaded with a varying voltage, thereby improving the performance and usability of the electronic device including the multi-chip package structure.
  • FIG. 1 is a schematic structural view of a preferred embodiment of an electronic device according to the present invention.
  • FIG. 2 is a partial perspective structural view of a multi-chip package structure with a QFN package.
  • FIG. 3 is a cross-sectional structural view of the multi-chip package structure shown in FIG. 2 taken along line III-III.
  • FIG. 4 is a partial perspective structural view of a multi-chip package structure in a package mode of BGA.
  • FIG. 5 is a cross-sectional structural view of the multi-chip package structure shown in FIG. 4 taken along line V-V.
  • signal of change means that the signal does not always maintain the same potential with the extension of time.
  • a “constant signal” means that the potential of the signal remains or remains substantially constant over time. Since the signal will always be more or less interfered by other signals, causing the signal to fluctuate, the constant signal is actually substantially constant.
  • connection includes various conditions including direct connection, indirect connection, coupling, and the like, and unless the invention specifically indicates one of the cases, it includes various cases.
  • the invention provides a multi-chip package structure, which integrates two or more chips in one package, and can also integrate some other components, such as capacitors, thereby saving the volume of the electronic device and reducing the manufacturing cost of the electronic device. .
  • the inventors have found through extensive research that a plurality of chips in a multi-chip package structure are generally common, and the ground voltage is a constant voltage, generally 0V.
  • the ground voltage is a constant voltage, generally 0V.
  • the ground voltage remains the same, which will affect the performance or accuracy of the chip, and even limit the design of the chip.
  • a parasitic capacitance is formed between the grounding end of the fingerprint sensing chip and the capacitive sensing plate. If the excitation signal of the capacitive sensing plate is changed, and the ground voltage of the grounding terminal remains unchanged, then The change in charge and discharge power of the parasitic capacitance affects the sensing accuracy of the fingerprint sensing chip. Therefore, from the above, it is known that it is necessary to provide a correspondingly varying ground voltage to some chips.
  • FIG. 1 is a schematic structural diagram of a preferred embodiment of an electronic device according to the present invention.
  • the electronic device 100 is, for example, a mobile phone, a tablet computer, a GPS navigation system, a television, and the like.
  • the electronic device 100 includes a multi-chip package structure 10 and a power supply 30.
  • the power supply 30 includes a positive electrode a for loading a first voltage and a negative electrode b for loading a second voltage, wherein the first voltage is greater than the second voltage.
  • the voltage difference between the first voltage and the second voltage is a power supply voltage at which the electronic device 100 operates normally.
  • the second voltage is a constant voltage, preferably 0V.
  • the negative electrode b is used as a device ground of the electronic device 100, and the second voltage is a ground voltage.
  • the multi-chip package structure 10 includes a first chip 11 and a second chip 12.
  • the first chip 11 and the second chip 12 are integrated in the same package structure.
  • the first chip 11 includes a ground terminal 11a for loading a varying voltage signal.
  • the second chip 12 includes a ground end 12a for loading a constant Voltage signal.
  • the ground terminal 12a is connected to the ground end of the device, and receives a ground voltage of the device ground, that is, a second voltage.
  • the second chip 12 further includes a signal transmission terminal T.
  • the signal transmitting end T is connected to the grounding end 11a, and the signal transmitting end T outputs a first signal to the grounding end 11a, and the first signal is used as a ground signal of the first chip 11, Wherein the first signal is a changed signal.
  • the first signal is a square wave signal. More preferably, the first signal is a periodically varying square wave signal.
  • the present invention is not limited thereto, and the first signal may also be other suitable signals, such as a sine wave signal.
  • the voltage of the first chip 11 varies with the change of the first signal. Wherein, the voltage of the first chip 11 increases with the increase of the voltage of the ground signal, and decreases with the decrease of the voltage of the ground signal.
  • the first chip 11 further includes a power terminal 11b, and the power terminal 11b receives a second signal. At the same time, the voltage of the second signal is greater than the voltage of the first signal, and the second signal is The voltage difference of the first signal is the power supply voltage at which the first chip 11 operates normally.
  • the power terminal 11b is connected to the second chip 12, and the second chip 12 provides the second signal, and the second signal is a changed signal.
  • the power terminal 11b can also be introduced from the outside of the package.
  • a communication interface (not labeled) is further disposed between the first chip 11 and the second chip 12 for information communication.
  • the multi-chip package structure 10 further includes a signal electrode made of a conductive material, and the signal electrode is disposed at least around the first chip 11.
  • the signal electrode is used to load an electrical signal and does not output a signal to other components, and is not used for signal detection.
  • the signal electrode is loaded with a third signal, which is a varying signal.
  • the third signal is the same as the first signal.
  • the signal electrode is connected to the ground end 11a of the first chip 11 and the signal transmission end T of the second chip 12.
  • the third signal changes synchronously with the first signal, and the magnitude changes direction is the same.
  • the magnitude of the amplitude change of the third signal is different from the first The magnitude of the amplitude change of a signal corresponds to the same.
  • the third signal is a signal that varies with the change of the first signal.
  • the third signal increases as the first signal increases, and decreases as the first signal decreases.
  • the signal electrode is connected to the second chip 12, and the second chip 12 supplies the third signal to the signal electrode.
  • the third signal is different from the first signal but remains unchanged relative to the first signal.
  • the magnitude of the amplitude change of the third signal is the same as the magnitude of the amplitude change of the first signal.
  • the package of the chip is not limited to these two packages, and may be other package methods. It should be noted that the multi-chip package structure 10 may not be filled with a material, may be filled with an epoxy resin material, or may be filled with other materials.
  • FIG. 2 is a partial perspective structural view of a multi-chip package structure with a QFN package.
  • 3 is a cross-sectional structural view of the multi-chip package structure shown in FIG. 2 taken along line III-III.
  • the multi-chip package structure 10 further includes a heat sink 13, a lead 14, and a lead 15.
  • the first chip 11 and the second chip 12 are respectively connected to the leads 14 through the leads 15 .
  • the pin 14 is disposed on the periphery of the heat sink 13.
  • the heat sink 13 is made of a conductive material for heat dissipation and is also used as the signal electrode. Thereby, material saving and volume saving.
  • the first chip 11 and the second chip 12 are disposed on the heat sink 13 , wherein a conductive layer 16 is disposed between the first chip 11 and the heat sink 13 , and the second chip 12 is disposed.
  • An insulating layer 17 is disposed between the heat sink 13.
  • the heat sink 13 is connected to the ground end 11a of the first chip 11 through the conductive layer 16.
  • the substrate of the first chip 11 is preferably a silicon substrate, and the ground terminal 11a is electrically connected to the heat sink 13 through a silicon substrate.
  • the conductive layer 16 is made of a conductive paste
  • the insulating layer 17 is made of an insulating paste.
  • the grounding end 11a can further pass through a wire 18 and the heat sink 13.
  • FIG. 4 is a partial perspective structural view of a multi-chip package structure with a BGA package.
  • FIG. 5 is a cross-sectional structural view of the multi-chip package structure shown in FIG. 4 taken along line V-V.
  • the multi-chip package structure 10 further includes a substrate 19, a lead 14, a lead 15, the lead 14, the first chip 11 and the second chip 12 are disposed on the substrate 19, The above signal electrodes are provided on the substrate 19.
  • the first chip 11 and the second chip 12 are disposed to be connected to the leads 14 through leads 15.
  • the substrate 19 is an insulating substrate.
  • the first chip 11 and the second chip 12 are respectively disposed on the substrate 19 through an insulating paste 17.
  • the signal electrodes are indicated by the reference numeral "20" in FIGS. 4 and 5.
  • the signal electrode 20 surrounds the first chip 11.
  • the signal electrode 20 further surrounds the second chip 12.
  • the signal electrode 20 is a whole layer of electrodes disposed between the first chip 11 and the substrate 19 and stacked on the second chip 11 and the substrate 19. The edge of the signal electrode 20 extends beyond the edge of the first chip 11 in the vertical stacking direction.
  • the signal electrode 20 is connected to the signal transmission end T and the ground end 11a, respectively, and receives the first signal.
  • first chip 11 and the second chip 12 are disposed on the same side or opposite sides of the substrate 19.
  • first chip 11 and the second chip 12 are disposed on opposite sides of the substrate 19, the first chip 11 and the second chip 12 are preferably stacked and arranged by the lining
  • the bottom 19 is spaced.
  • the substrate 19 is an insulating substrate.
  • the first chip 11 is a sensing chip
  • the second chip 12 is a control chip.
  • the first chip 11 and the second chip 12 may also be other functional chips.
  • the technical content of the present invention may be easily made according to the teachings of the present invention. Reasonably applicable For other functional chips.
  • the sensing chip is, for example, a fingerprint sensing chip or a touch sensing chip.
  • the fingerprint sensing chip or the touch sensing chip preferably adopts a capacitive sensing technology, and more preferably, a self-capacitance sensing technology.
  • the fingerprint sensing chip includes a sensor board, and the sensor board includes a plurality of capacitive sensing plates for capacitively coupling to a target object, the fingerprint sensing The chip performs a sensing operation by providing an excitation signal to the sensor board to drive the sensor board to obtain predetermined information of the target object.
  • the fingerprint sensing chip obtains predetermined information of the target object by measuring a change in capacitance between the sensor board and the target object.
  • the target object is a finger.
  • the predetermined information is, for example, fingerprint information.
  • the excitation signal changes with the change of the first signal of the ground terminal 11a to reduce the charge and discharge power between the ground terminal 11a and the sensor board.
  • the excitation signal increases as the first signal increases, and decreases as the first signal decreases. Thereby, the influence of the parasitic capacitance between the ground terminal 11a of the fingerprint sensing chip and the capacitive sensing plate on the sensing accuracy is reduced.
  • the signal electrode is used to generate an electric field with the target object, so that the electric field line between the capacitive sensing plate located at the edge and the target object is relatively uniform, thereby obtaining more realistic predetermined information.
  • the multi-chip package structure 10 of the present invention only the first chip 11 and the second chip 12 are taken as an example for description. However, the present invention does not limit the number of chips.
  • the multi-chip package structure 10 may further include other chips such as a third chip and a fourth chip.
  • the signal electrodes can also be connected to other chips to receive third signals from other chips.
  • the multi-chip package structure 10 of the electronic device 100 of the present invention not only integrates a plurality of chips, but also selects the grounding terminal 11a to load a varying voltage according to the structural characteristics of the chip itself, thereby improving the performance and usability of the multi-chip package structure 10. .

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

A multi-chip packaging structure and an electronic device comprising said multi-chip packaging structure. The multi-chip packaging structure (10) comprises a first chip (11) and a second chip (12), the first chip (11) comprising a ground end (11a), and the second chip (12) comprising a signal transmission end (T), the signal transmission end (T) being in communication with the ground end (11a); the signal transmission end (T) outputs a first signal to the ground end (11a), the first signal acting as a ground signal of the first chip (11), and the first signal being a varying signal. The electronic device (100) comprises the multi-chip packaging structure (10).

Description

多芯片封装结构以及电子设备Multi-chip package structure and electronic equipment
本申请要求2015年1月13日提交中国专利局、申请号为201510015685.1、发明名称为“多芯片封装结构以及电子设备”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。This application claims the priority of the Chinese Patent Application, filed on Jan. 13, 2015, which is hereby incorporated by reference.
技术领域Technical field
本发明涉及一种多芯片封装结构以及电子设备。The invention relates to a multi-chip package structure and an electronic device.
背景技术Background technique
目前,电子设备(如:手机、平板电脑等)中通常会设置有多种功能芯片,然,各功能芯片一般独立封装,导致占用电子设备较大的体积、以及造成电子设备的成本较高。At present, electronic devices (such as mobile phones, tablet computers, etc.) are usually provided with a plurality of functional chips. However, each functional chip is generally packaged separately, resulting in occupying a large volume of the electronic device and causing high cost of the electronic device.
发明内容Summary of the invention
为解决上述技术问题,本发明提供一种多芯片封装结构以及具有多芯片封装结构的电子设备。To solve the above technical problems, the present invention provides a multi-chip package structure and an electronic device having a multi-chip package structure.
为实现上述目的,本发明提供如下技术方案:To achieve the above object, the present invention provides the following technical solutions:
一种多芯片封装结构,包括:A multi-chip package structure comprising:
第一芯片,包括接地端;和a first chip, including a ground terminal; and
第二芯片,包括信号传输端,所述信号传输端与所述接地端连接,所述信号传输端输出第一信号给所述接地端,所述第一信号作为所述第一芯片的地信号,其中,所述第一信号为变化的信号。a second chip, including a signal transmission end, the signal transmission end is connected to the ground end, the signal transmission end outputs a first signal to the ground end, and the first signal is used as a ground signal of the first chip Wherein the first signal is a varying signal.
优选地,所述第一芯片的电压均随所述地信号的变化而变化。Preferably, the voltage of the first chip varies with the change of the ground signal.
优选地,所述第一芯片的电压均随所述地信号的电压的升高而升高,随所述地信号的电压的降低而降低。Preferably, the voltage of the first chip increases as the voltage of the ground signal increases, and decreases as the voltage of the ground signal decreases.
优选地,所述第一芯片进一步包括电源端,所述电源端接收第二信号,在同一时刻,所述第二信号的电压均大于所述第一信号的电压,所述第二信号与所述第一信号的电压差为所述第一芯片的工作电压。Preferably, the first chip further includes a power terminal, and the power terminal receives the second signal. At the same time, the voltage of the second signal is greater than the voltage of the first signal, and the second signal The voltage difference of the first signal is the operating voltage of the first chip.
优选地,所述电源端与所述第二芯片连接,所述第二芯片提供所 述第二信号,所述第二信号为变化的信号。Preferably, the power terminal is connected to the second chip, and the second chip provides a solution The second signal is a changed signal.
优选地,所述第二芯片进一步包括接地端,所述第二芯片的接地端连接一电子设备的设备地端,或者所述第二芯片的接地端与所述多芯片封装结构所在的电子设备的设备地端连接,或者所述第二芯片的接地端施加有一恒定电压。Preferably, the second chip further includes a ground end, the ground end of the second chip is connected to a device ground end of an electronic device, or the ground end of the second chip and the electronic device where the multi-chip package structure is located The device is grounded or a constant voltage is applied to the ground of the second chip.
优选地,所述多芯片封装结构进一步包括信号电极,所述信号电极由导电材料制成,所述信号电极至少设置在所述第一芯片周围。Preferably, the multi-chip package structure further includes a signal electrode made of a conductive material, and the signal electrode is disposed at least around the first chip.
优选地,所述信号电极加载有第三信号,所述第三信号为变化的信号。Preferably, the signal electrode is loaded with a third signal, the third signal being a varying signal.
优选地,所述第三信号与所述第一信号相同。Preferably, the third signal is the same as the first signal.
优选地,所述信号电极与所述第一芯片的接地端和第二芯片的信号传输端连接。Preferably, the signal electrode is connected to a ground end of the first chip and a signal transmission end of the second chip.
优选地,所述第三信号与所述第一信号同步变化,且变化的大小及变化的方向相同。Preferably, the third signal changes synchronously with the first signal, and the magnitude of the change and the direction of the change are the same.
优选地,所述第三信号随所述第一信号的变化而变化。Preferably, the third signal changes as the first signal changes.
优选地,所述第三信号随所述第一信号的升高而升高、随所述第一信号的降低而降低。Preferably, the third signal increases as the first signal increases and decreases as the first signal decreases.
优选地,所述第三信号的幅度变化大小与所述第一信号的幅度变化大小对应相同。Preferably, the magnitude of the amplitude change of the third signal is the same as the magnitude of the amplitude change of the first signal.
优选地,所述多芯片封装结构包括散热片,所述散热片由导电材料制成,所述散热片用于散热,还用于作为所述信号电极。Preferably, the multi-chip package structure includes a heat sink, the heat sink is made of a conductive material, the heat sink is used for heat dissipation, and is also used as the signal electrode.
优选地,所述第一芯片与所述第二芯片均设置在所述散热片上,其中,所述第一芯片与所述散热片之间设置导电层,所述第二芯片与所述散热片之间设置绝缘层。Preferably, the first chip and the second chip are both disposed on the heat sink, wherein a conductive layer is disposed between the first chip and the heat sink, and the second chip and the heat sink An insulating layer is provided between them.
优选地,所述散热片与所述第一芯片的接地端通过所述导电层连接Preferably, the heat sink is connected to the ground end of the first chip through the conductive layer
优选地,所述导电层由导电胶制成,所述绝缘层由绝缘胶制成。Preferably, the conductive layer is made of a conductive paste, and the insulating layer is made of an insulating paste.
优选地,所述多芯片封装结构进一步包括衬底,所述第一芯片与所述第二芯片设置在所述衬底上,所述衬底上设置所述信号电极。 Preferably, the multi-chip package structure further includes a substrate, the first chip and the second chip are disposed on the substrate, and the signal electrode is disposed on the substrate.
优选地,所述信号电极环绕第一芯片。Preferably, the signal electrode surrounds the first chip.
优选地,所述信号电极进一步环绕第二芯片。Preferably, the signal electrode further surrounds the second chip.
优选地,所述信号电极为一整层电极,设置在第一芯片与所述衬底之间,与所述第一芯片和衬底层叠设置,沿垂直层叠方向,所述信号电极的边缘超出所述第一芯片的边缘。Preferably, the signal electrode is an entire layer of electrodes disposed between the first chip and the substrate, and is stacked with the first chip and the substrate, and the edge of the signal electrode is beyond the vertical stacking direction The edge of the first chip.
优选地,所述第一芯片与所述第二芯片设置在所述衬底的同一侧或相对两侧。Preferably, the first chip and the second chip are disposed on the same side or opposite sides of the substrate.
优选地,所述第一芯片为感测芯片,所述第二芯片为控制芯片。Preferably, the first chip is a sensing chip, and the second chip is a control chip.
优选地,所述第一芯片为指纹感测芯片或触控感测芯片。Preferably, the first chip is a fingerprint sensing chip or a touch sensing chip.
优选地,所述第一芯片包括传感器板,所述传感器板用于以电容方式耦合到目标物体,所述第一芯片通过提供激励信号给所述传感器板以驱动所述传感器板执行感测操作,以获得所述目标物体的预定信息,其中,所述激励信号随所述第一信号的变化而变化。Preferably, the first chip includes a sensor board for capacitively coupling to a target object, the first chip performing a sensing operation by providing an excitation signal to the sensor board to drive the sensor board Obtaining predetermined information of the target object, wherein the excitation signal changes as the first signal changes.
优选地,所述激励信号随所述第一信号的升高而升高、随所述第一信号的降低而降低。Preferably, the excitation signal increases as the first signal increases, and decreases as the first signal decreases.
本发明又提供一种多芯片封装结构,包括:The invention further provides a multi-chip package structure, comprising:
第一芯片,包括接地端,所述接地端用于加载变化的信号;和a first chip comprising a ground end for loading a varying signal; and
第二芯片,包括接地端,所述接地端用于加载恒定的信号。The second chip includes a ground terminal for loading a constant signal.
优选地,所述第二芯片包括信号传输端,所述信号传输端与所述第一芯片的接地端连接,用于输出所述变化的信号给所述第一芯片的接地端。Preferably, the second chip includes a signal transmission end, and the signal transmission end is connected to a ground end of the first chip for outputting the changed signal to a ground end of the first chip.
本发明提供一种电子设备,所述电子设备包括如上所述任一项所述的多芯片封装结构。The present invention provides an electronic device comprising the multi-chip package structure of any of the above.
本发明又提供一种电子设备,包括一多芯片封装结构和设备地端,所述多芯片封装结构包括:The invention further provides an electronic device comprising a multi-chip package structure and a device ground, the multi-chip package structure comprising:
第一芯片,包括接地端,所述接地端用于加载变化的信号;和a first chip comprising a ground end for loading a varying signal; and
第二芯片,包括接地端,所述接地端与所述设备地端连接。The second chip includes a ground end connected to the ground end of the device.
优选地,所述第二芯片包括信号传输端,所述信号传输端与所述第一芯片的接地端连接,用于输出所述变化的信号给所述第一芯片的 接地端。Preferably, the second chip includes a signal transmission end, and the signal transmission end is connected to a ground end of the first chip, and is configured to output the changed signal to the first chip. Ground terminal.
优选地,所述电子设备包括供电电源,所述供电电源包括正极与负极,所述负极为所述设备地端。Preferably, the electronic device comprises a power supply, the power supply comprises a positive pole and a negative pole, and the negative pole is a ground end of the device.
本发明电子设备的多芯片封装结构不仅集成有第一芯片和第二芯片,而且第一芯片的接地端加载变化的电压,从而提高包括多芯片封装结构的电子设备的工作性能以及可用性。The multi-chip package structure of the electronic device of the present invention not only integrates the first chip and the second chip, but also the ground terminal of the first chip is loaded with a varying voltage, thereby improving the performance and usability of the electronic device including the multi-chip package structure.
附图说明DRAWINGS
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.
图1为本发明电子设备较佳实施方式的结构示意图。FIG. 1 is a schematic structural view of a preferred embodiment of an electronic device according to the present invention.
图2为封装方式为QFN的多芯片封装结构的部分立体结构示意图。2 is a partial perspective structural view of a multi-chip package structure with a QFN package.
图3为图2所示多芯片封装结构沿III-III线的剖面结构示意图。3 is a cross-sectional structural view of the multi-chip package structure shown in FIG. 2 taken along line III-III.
图4为封装方式为BGA的多芯片封装结构的部分立体结构示意图。4 is a partial perspective structural view of a multi-chip package structure in a package mode of BGA.
图5为图4所示多芯片封装结构沿V-V线的剖面结构示意图。FIG. 5 is a cross-sectional structural view of the multi-chip package structure shown in FIG. 4 taken along line V-V.
具体实施方式detailed description
需要说明的是,下述“变化的信号”是指:随着时间的延伸,所述信号并不一直保持同一电位。相对地,“恒定的信号”是指:随着时间的延伸,所述信号的电位保持或基本保持不变。因为信号总会或多或少受到其它信号干扰,从而导致信号有波动,因此,所述恒定的信号实际上是基本保持电位不变。It should be noted that the following "signal of change" means that the signal does not always maintain the same potential with the extension of time. In contrast, a "constant signal" means that the potential of the signal remains or remains substantially constant over time. Since the signal will always be more or less interfered by other signals, causing the signal to fluctuate, the constant signal is actually substantially constant.
技术术语“连接”包括直接连接、间接连接、耦接等各种情况,除非本发明有特别指明为其中一种情况,否则包括各种情况。The technical term "connected" includes various conditions including direct connection, indirect connection, coupling, and the like, and unless the invention specifically indicates one of the cases, it includes various cases.
下面将结合本发明实施例中的附图,对本发明实施例中的技术方 案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。The technical party in the embodiment of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention. The present invention is clearly and completely described, and it is obvious that the described embodiments are only a part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
本发明提供一种多芯片封装结构,就是在一个封装内集成两颗和两颗以上芯片,还可以集成一些其他元器件,比如电容等,从而节省电子设备的体积,并降低电子设备的制造成本。The invention provides a multi-chip package structure, which integrates two or more chips in one package, and can also integrate some other components, such as capacitors, thereby saving the volume of the electronic device and reducing the manufacturing cost of the electronic device. .
进一步地,发明人通过大量研究发现,多芯片封装结构中的多颗芯片通常共地,地电压为恒定的电压,一般为0V。在一些封装结构中,存在地平面,则芯片地可以连接到这个地平面。然,对于某些芯片而言,其接地电压保持不变,会影响芯片的工作性能或者精度,甚至会限制芯片的设计。以指纹感测芯片为例,指纹感测芯片的接地端与电容感测极板之间形成寄生电容,若电容感测极板的激励信号是变化的,而接地端的地电压保持不变,则寄生电容的充放电电量变化会影响指纹感测芯片的感测精度。因此,由上述内容可知,对应提供相应变化的地电压给某些芯片是很必要的。Further, the inventors have found through extensive research that a plurality of chips in a multi-chip package structure are generally common, and the ground voltage is a constant voltage, generally 0V. In some package structures, there is a ground plane where the chip ground can be connected. However, for some chips, the ground voltage remains the same, which will affect the performance or accuracy of the chip, and even limit the design of the chip. Taking the fingerprint sensing chip as an example, a parasitic capacitance is formed between the grounding end of the fingerprint sensing chip and the capacitive sensing plate. If the excitation signal of the capacitive sensing plate is changed, and the ground voltage of the grounding terminal remains unchanged, then The change in charge and discharge power of the parasitic capacitance affects the sensing accuracy of the fingerprint sensing chip. Therefore, from the above, it is known that it is necessary to provide a correspondingly varying ground voltage to some chips.
请参阅图1,图1为本发明电子设备较佳实施方式的结构示意图。所述电子设备100如为手机、平板电脑、GPS导航系统、电视等设备。所述电子设备100包括多芯片封装结构10和供电电源30。所述供电电源30包括正极a与负极b,所述正极a用于加载第一电压,所述负极b用于加载第二电压,其中,第一电压大于第二电压。所述第一电压与所述第二电压之间的电压差为所述电子设备100正常工作的电源电压。所述第二电压为恒定电压,优选为0V。所述负极b用作所述电子设备100的设备地端,所述第二电压为地电压。Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a preferred embodiment of an electronic device according to the present invention. The electronic device 100 is, for example, a mobile phone, a tablet computer, a GPS navigation system, a television, and the like. The electronic device 100 includes a multi-chip package structure 10 and a power supply 30. The power supply 30 includes a positive electrode a for loading a first voltage and a negative electrode b for loading a second voltage, wherein the first voltage is greater than the second voltage. The voltage difference between the first voltage and the second voltage is a power supply voltage at which the electronic device 100 operates normally. The second voltage is a constant voltage, preferably 0V. The negative electrode b is used as a device ground of the electronic device 100, and the second voltage is a ground voltage.
所述多芯片封装结构10包括第一芯片11和第二芯片12。第一芯片11和第二芯片12集成在同一封装结构中。The multi-chip package structure 10 includes a first chip 11 and a second chip 12. The first chip 11 and the second chip 12 are integrated in the same package structure.
所述第一芯片11包括接地端11a,所述接地端11a用于加载变化的电压信号。The first chip 11 includes a ground terminal 11a for loading a varying voltage signal.
所述第二芯片12包括接地端12a,所述接地端12a用于加载恒定 的电压信号。优选地,所述接地端12a与所述设备地端连接,接收所述设备地端的地电压,即第二电压。The second chip 12 includes a ground end 12a for loading a constant Voltage signal. Preferably, the ground terminal 12a is connected to the ground end of the device, and receives a ground voltage of the device ground, that is, a second voltage.
所述第二芯片12进一步包括信号传输端T。优选地,所述信号传输端T与所述接地端11a连接,所述信号传输端T输出第一信号给所述接地端11a,所述第一信号作为所述第一芯片11的地信号,其中,所述第一信号为变化的信号。优选地,所述第一信号为方波信号。更优选地,所述第一信号为周期性变化的方波信号。然,本发明对此并不做限制,所述第一信号也可为其它合适的信号,如正弦波信号等。The second chip 12 further includes a signal transmission terminal T. Preferably, the signal transmitting end T is connected to the grounding end 11a, and the signal transmitting end T outputs a first signal to the grounding end 11a, and the first signal is used as a ground signal of the first chip 11, Wherein the first signal is a changed signal. Preferably, the first signal is a square wave signal. More preferably, the first signal is a periodically varying square wave signal. However, the present invention is not limited thereto, and the first signal may also be other suitable signals, such as a sine wave signal.
所述第一芯片11的电压均随所述第一信号的变化而变化。其中,所述第一芯片11的电压均随所述地信号的电压的升高而升高,随所述地信号的电压的降低而降低。The voltage of the first chip 11 varies with the change of the first signal. Wherein, the voltage of the first chip 11 increases with the increase of the voltage of the ground signal, and decreases with the decrease of the voltage of the ground signal.
所述第一芯片11进一步包括电源端11b,所述电源端11b接收第二信号,在同一时刻,所述第二信号的电压大于所述第一信号的电压,所述第二信号与所述第一信号的电压差为所述第一芯片11正常工作的电源电压。The first chip 11 further includes a power terminal 11b, and the power terminal 11b receives a second signal. At the same time, the voltage of the second signal is greater than the voltage of the first signal, and the second signal is The voltage difference of the first signal is the power supply voltage at which the first chip 11 operates normally.
所述电源端11b与所述第二芯片12连接,所述第二芯片12提供所述第二信号,所述第二信号为变化的信号。所述电源端11b也可以从封装外部引入。另外,所述第一芯片11与所述第二芯片12之间还设置有通信接口(未标示),以进行信息通信。The power terminal 11b is connected to the second chip 12, and the second chip 12 provides the second signal, and the second signal is a changed signal. The power terminal 11b can also be introduced from the outside of the package. In addition, a communication interface (not labeled) is further disposed between the first chip 11 and the second chip 12 for information communication.
优选地,所述多芯片封装结构10进一步包括信号电极,所述信号电极由导电材料制成,所述信号电极至少设置在所述第一芯片11周围。优选地,所述信号电极用于加载电信号,而并不输出信号给其它元件,不用作信号检测。Preferably, the multi-chip package structure 10 further includes a signal electrode made of a conductive material, and the signal electrode is disposed at least around the first chip 11. Preferably, the signal electrode is used to load an electrical signal and does not output a signal to other components, and is not used for signal detection.
所述信号电极加载有第三信号,所述第三信号为变化的信号。The signal electrode is loaded with a third signal, which is a varying signal.
在一实施方式中,所述第三信号与所述第一信号相同。优选地,所述信号电极与所述第一芯片11的接地端11a和第二芯片12的信号传输端T连接。In an embodiment, the third signal is the same as the first signal. Preferably, the signal electrode is connected to the ground end 11a of the first chip 11 and the signal transmission end T of the second chip 12.
在另一实施方式中,所述第三信号与所述第一信号同步变化,且大小变化方向相同。优选地,所述第三信号的幅度变化大小与所述第 一信号的幅度变化大小对应相同。In another embodiment, the third signal changes synchronously with the first signal, and the magnitude changes direction is the same. Preferably, the magnitude of the amplitude change of the third signal is different from the first The magnitude of the amplitude change of a signal corresponds to the same.
在又一实施方式中,所述第三信号随所述第一信号的变化而变化的信号。其中,所述第三信号随所述第一信号的升高而升高、随所述第一信号的降低而降低。如,所述信号电极与第二芯片12连接,所述第二芯片12提供所述第三信号给所述信号电极。所述第三信号与所述第一信号不同,但相对第一信号保持不变。优选地,所述第三信号的幅度变化大小与所述第一信号的幅度变化大小对应相同。In still another embodiment, the third signal is a signal that varies with the change of the first signal. Wherein the third signal increases as the first signal increases, and decreases as the first signal decreases. For example, the signal electrode is connected to the second chip 12, and the second chip 12 supplies the third signal to the signal electrode. The third signal is different from the first signal but remains unchanged relative to the first signal. Preferably, the magnitude of the amplitude change of the third signal is the same as the magnitude of the amplitude change of the first signal.
根据芯片的封装方式不同,下面就封装方式分别为方形扁平无引脚封装(Quad Flat No-lead Package,简称QFN)与球栅阵列封装(Ball Grid Array Package,简称BGA)进行说明。然,芯片的封装并不局限于这两种封装方式,也可以为其它封装方式。需要说明的是,所述多芯片封装结构10可以不填充材料,也可以填充环氧树脂材料,还可以填充其它材料。Depending on the package method of the chip, the following packages are described as a Quad Flat No-lead Package (QFN) and a Ball Grid Array Package (BGA). However, the package of the chip is not limited to these two packages, and may be other package methods. It should be noted that the multi-chip package structure 10 may not be filled with a material, may be filled with an epoxy resin material, or may be filled with other materials.
封装方式QFNPackage method QFN
请一并参阅图2与图3,图2为封装方式为QFN的多芯片封装结构的部分立体结构示意图。图3为图2所示多芯片封装结构沿III-III线的剖面结构示意图。所述多芯片封装结构10进一步包括散热片13、引脚14、引线15。所述第一芯片11和第二芯片12分别通过引线15与引脚14对应连接。所述引脚14设置在所述散热片13外围。所述散热片13由导电材料制成,用于散热,还用于作为所述信号电极。从而,节省材料,节省体积。Please refer to FIG. 2 and FIG. 3 together. FIG. 2 is a partial perspective structural view of a multi-chip package structure with a QFN package. 3 is a cross-sectional structural view of the multi-chip package structure shown in FIG. 2 taken along line III-III. The multi-chip package structure 10 further includes a heat sink 13, a lead 14, and a lead 15. The first chip 11 and the second chip 12 are respectively connected to the leads 14 through the leads 15 . The pin 14 is disposed on the periphery of the heat sink 13. The heat sink 13 is made of a conductive material for heat dissipation and is also used as the signal electrode. Thereby, material saving and volume saving.
所述第一芯片11与所述第二芯片12均设置在所述散热片13上,其中,所述第一芯片11与所述散热片13之间设置导电层16,所述第二芯片12与所述散热片13之间设置绝缘层17。在一实施方式中,所述散热片13与所述第一芯片11的接地端11a通过所述导电层16连接。其中,所述第一芯片11的衬底优选为硅衬底,所述接地端11a通过硅衬底与所述散热片13电连接。优选地,所述导电层16由导电胶制成,所述绝缘层17由绝缘胶制成。The first chip 11 and the second chip 12 are disposed on the heat sink 13 , wherein a conductive layer 16 is disposed between the first chip 11 and the heat sink 13 , and the second chip 12 is disposed. An insulating layer 17 is disposed between the heat sink 13. In an embodiment, the heat sink 13 is connected to the ground end 11a of the first chip 11 through the conductive layer 16. The substrate of the first chip 11 is preferably a silicon substrate, and the ground terminal 11a is electrically connected to the heat sink 13 through a silicon substrate. Preferably, the conductive layer 16 is made of a conductive paste, and the insulating layer 17 is made of an insulating paste.
为了提高第一芯片11的接地端11a与所述散热片13的电导通特 性,在另一实施方式中,所述接地端11a可进一步通过一导线18与所述散热片13。In order to improve the electrical conductivity of the ground end 11a of the first chip 11 and the heat sink 13 In another embodiment, the grounding end 11a can further pass through a wire 18 and the heat sink 13.
封装方式BGAPackage method BGA
请一并参阅图4与图5,图4为封装方式为BGA的多芯片封装结构的部分立体结构示意图。图5为图4所示多芯片封装结构沿V-V线的剖面结构示意图。所述多芯片封装结构10进一步包括衬底19、引脚14、引线15,所述引脚14、所述第一芯片11和所述第二芯片12设置在所述衬底19上,所述衬底19上设置上述信号电极。所述第一芯片11和所述第二芯片12设置通过引线15与引脚14连接。优选地,所述衬底19为绝缘衬底。优选地,所述第一芯片11与第二芯片12分别通过绝缘胶17设置在所述衬底19上。Please refer to FIG. 4 and FIG. 5 together. FIG. 4 is a partial perspective structural view of a multi-chip package structure with a BGA package. FIG. 5 is a cross-sectional structural view of the multi-chip package structure shown in FIG. 4 taken along line V-V. The multi-chip package structure 10 further includes a substrate 19, a lead 14, a lead 15, the lead 14, the first chip 11 and the second chip 12 are disposed on the substrate 19, The above signal electrodes are provided on the substrate 19. The first chip 11 and the second chip 12 are disposed to be connected to the leads 14 through leads 15. Preferably, the substrate 19 is an insulating substrate. Preferably, the first chip 11 and the second chip 12 are respectively disposed on the substrate 19 through an insulating paste 17.
其中,为清楚明了,图4与图5中采用标号“20”标示信号电极。优选地,所述信号电极20环绕第一芯片11。Here, for the sake of clarity, the signal electrodes are indicated by the reference numeral "20" in FIGS. 4 and 5. Preferably, the signal electrode 20 surrounds the first chip 11.
在另一实施方式中,所述信号电极20进一步环绕第二芯片12。In another embodiment, the signal electrode 20 further surrounds the second chip 12.
在又一实施方式中,所述信号电极20为一整层电极,设置在第一芯片11与所述衬底19之间,与所述第二芯片11和衬底19层叠设置。沿垂直层叠方向,所述信号电极20的边缘超出所述第一芯片11的边缘。In still another embodiment, the signal electrode 20 is a whole layer of electrodes disposed between the first chip 11 and the substrate 19 and stacked on the second chip 11 and the substrate 19. The edge of the signal electrode 20 extends beyond the edge of the first chip 11 in the vertical stacking direction.
在本实施方式中,所述信号电极20与所述信号传输端T和接地端11a分别连接,接收第一信号。In this embodiment, the signal electrode 20 is connected to the signal transmission end T and the ground end 11a, respectively, and receives the first signal.
进一步地,所述第一芯片11与所述第二芯片12设置在所述衬底19的同一侧或相对两侧。当所述第一芯片11与所述第二芯片12设置在所述衬底19的相对两侧时,所述第一芯片11与所述第二芯片12优选为堆叠设置,并由所述衬底19间隔。其中,所述衬底19为绝缘衬底。Further, the first chip 11 and the second chip 12 are disposed on the same side or opposite sides of the substrate 19. When the first chip 11 and the second chip 12 are disposed on opposite sides of the substrate 19, the first chip 11 and the second chip 12 are preferably stacked and arranged by the lining The bottom 19 is spaced. Wherein, the substrate 19 is an insulating substrate.
在上述各实施方式中,优选地,所述第一芯片11为感测芯片,所述第二芯片12为控制芯片。然,本发明对比并不做限制,所述第一芯片11和第二芯片12也可为其它功能芯片,对于本领域的一般技术人员,其根据本发明的教导可以较易将本发明技术内容合理地适用 于其它功能芯片。In each of the above embodiments, preferably, the first chip 11 is a sensing chip, and the second chip 12 is a control chip. However, the comparison of the present invention is not limited. The first chip 11 and the second chip 12 may also be other functional chips. For those skilled in the art, the technical content of the present invention may be easily made according to the teachings of the present invention. Reasonably applicable For other functional chips.
进一步地,所述感测芯片如为指纹感测芯片或触控感测芯片。具体地,所述指纹感测芯片或触控感测芯片优选采用电容式感测技术,更优选地,采用自电容感测技术。Further, the sensing chip is, for example, a fingerprint sensing chip or a touch sensing chip. Specifically, the fingerprint sensing chip or the touch sensing chip preferably adopts a capacitive sensing technology, and more preferably, a self-capacitance sensing technology.
以指纹感测芯片为例,所述指纹感测芯片包括传感器板,所述传感器板包括多个电容感测极板,所述传感器板用于以电容方式耦合到目标物体,所述指纹感测芯片通过提供激励信号给所述传感器板以驱动所述传感器板执行感测操作,以获得所述目标物体的预定信息。所述指纹感测芯片通过量测传感器板与所述目标物体之间的电容变化来获得目标物体的预定信息。其中,所述目标物体如为手指。所述预定信息如为指纹信息。Taking a fingerprint sensing chip as an example, the fingerprint sensing chip includes a sensor board, and the sensor board includes a plurality of capacitive sensing plates for capacitively coupling to a target object, the fingerprint sensing The chip performs a sensing operation by providing an excitation signal to the sensor board to drive the sensor board to obtain predetermined information of the target object. The fingerprint sensing chip obtains predetermined information of the target object by measuring a change in capacitance between the sensor board and the target object. Wherein, the target object is a finger. The predetermined information is, for example, fingerprint information.
其中,所述激励信号随所述接地端11a的第一信号的变化而变化,以降低所述接地端11a与所述传感器板之间的充放电电量。优选地,所述激励信号随所述第一信号的升高而升高、随所述第一信号的降低而降低。从而,减小指纹感测芯片的接地端11a与电容感测极板之间的寄生电容对感测精度的影响。The excitation signal changes with the change of the first signal of the ground terminal 11a to reduce the charge and discharge power between the ground terminal 11a and the sensor board. Preferably, the excitation signal increases as the first signal increases, and decreases as the first signal decreases. Thereby, the influence of the parasitic capacitance between the ground terminal 11a of the fingerprint sensing chip and the capacitive sensing plate on the sensing accuracy is reduced.
进一步地,所述信号电极则用于与目标物体产生电场,从而使得位于边缘的电容感测极板也与目标物体之间的电场线较为均匀,从而获得较真实的预定信息。Further, the signal electrode is used to generate an electric field with the target object, so that the electric field line between the capacitive sensing plate located at the edge and the target object is relatively uniform, thereby obtaining more realistic predetermined information.
本发明上述多芯片封装结构10中仅以第一芯片11和第二芯片12为例进行说明。然,本发明并不限制芯片的颗数,所述多芯片封装结构10中还可包括第三芯片、第四芯片等其它芯片。另外,所述信号电极也可连接到其它芯片,接收来自其它芯片的第三信号。In the multi-chip package structure 10 of the present invention, only the first chip 11 and the second chip 12 are taken as an example for description. However, the present invention does not limit the number of chips. The multi-chip package structure 10 may further include other chips such as a third chip and a fourth chip. In addition, the signal electrodes can also be connected to other chips to receive third signals from other chips.
由上述内容可知,本发明电子设备100的多芯片封装结构10不仅集成有多颗芯片,而且根据芯片自身结构特点选择接地端11a加载变化的电压,从而提高多芯片封装结构10的工作性能以及可用性。It can be seen from the above that the multi-chip package structure 10 of the electronic device 100 of the present invention not only integrates a plurality of chips, but also selects the grounding terminal 11a to load a varying voltage according to the structural characteristics of the chip itself, thereby improving the performance and usability of the multi-chip package structure 10. .
对所公开的实施例的上述说明,使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的,本文中所定义的一般原理可以在不脱离本发明的 精神或范围的情况下,在其它实施例中实现。因此,本发明将不会被限制于本文所示的这些实施例,而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。 The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Numerous modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be without departing from the invention. In the case of spirit or scope, it is implemented in other embodiments. Therefore, the present invention is not to be limited to the embodiments shown herein, but the scope of the invention is to be accorded

Claims (32)

  1. 一种多芯片封装结构,包括:A multi-chip package structure comprising:
    第一芯片,包括接地端;和a first chip, including a ground terminal; and
    第二芯片,包括信号传输端,所述信号传输端与所述接地端连接,所述信号传输端输出第一信号给所述接地端,所述第一信号作为所述第一芯片的地信号,其中,所述第一信号为变化的信号。a second chip, including a signal transmission end, the signal transmission end is connected to the ground end, the signal transmission end outputs a first signal to the ground end, and the first signal is used as a ground signal of the first chip Wherein the first signal is a varying signal.
  2. 根据权利要求1所述的多芯片封装结构,其特征在于,所述第一芯片的电压均随所述地信号的变化而变化。The multi-chip package structure according to claim 1, wherein the voltage of the first chip changes according to a change of the ground signal.
  3. 根据权利要求2所述的多芯片封装结构,其特征在于,所述第一芯片的电压均随所述地信号的电压的升高而升高,随所述地信号的电压的降低而降低。The multi-chip package structure according to claim 2, wherein the voltage of the first chip increases as the voltage of the ground signal increases, and decreases as the voltage of the ground signal decreases.
  4. 根据权利要求1所述的多芯片封装结构,其特征在于,所述第一芯片进一步包括电源端,所述电源端接收第二信号,在同一时刻,所述第二信号的电压均大于所述第一信号的电压,所述第二信号与所述第一信号的电压差为所述第一芯片的工作电压。The multi-chip package structure according to claim 1, wherein the first chip further comprises a power terminal, and the power terminal receives the second signal, and at the same time, the voltage of the second signal is greater than the The voltage of the first signal, the voltage difference between the second signal and the first signal is the operating voltage of the first chip.
  5. 根据权利要求4所述的多芯片封装结构,其特征在于,所述电源端与所述第二芯片连接,所述第二芯片提供所述第二信号,所述第二信号为变化的信号。The multi-chip package structure according to claim 4, wherein the power terminal is connected to the second chip, the second chip provides the second signal, and the second signal is a changed signal.
  6. 根据权利要求1所述的多芯片封装结构,其特征在于,所述第二芯片进一步包括接地端,所述第二芯片的接地端连接一电子设备的设备地端,或者所述第二芯片的接地端与所述多芯片封装结构所在的电子设备的设备地端连接,或者所述第二芯片的接地端施加有一恒定电压。The multi-chip package structure according to claim 1, wherein the second chip further comprises a ground end, the ground end of the second chip is connected to a device ground of an electronic device, or the second chip The ground terminal is connected to the device ground of the electronic device where the multi-chip package structure is located, or a constant voltage is applied to the ground terminal of the second chip.
  7. 根据权利要求1所述的多芯片封装结构,其特征在于,所述多芯片封装结构进一步包括信号电极,所述信号电极由导电材料制成,所述信号电极至少设置在所述第一芯片周围。The multi-chip package structure according to claim 1, wherein the multi-chip package structure further comprises a signal electrode, the signal electrode is made of a conductive material, and the signal electrode is disposed at least around the first chip .
  8. 根据权利要求7所述的多芯片封装结构,其特征在于,所述信号电极加载有第三信号,所述第三信号为变化的信号。The multi-chip package structure according to claim 7, wherein the signal electrode is loaded with a third signal, and the third signal is a changed signal.
  9. 根据权利要求8所述的多芯片封装结构,其特征在于,所述第三 信号与所述第一信号相同。The multi-chip package structure according to claim 8, wherein said third The signal is the same as the first signal.
  10. 根据权利要求9所述的多芯片封装结构,其特征在于,所述信号电极与所述第一芯片的接地端和第二芯片的信号传输端连接。The multi-chip package structure according to claim 9, wherein the signal electrode is connected to a ground end of the first chip and a signal transmission end of the second chip.
  11. 根据权利要求8所述的多芯片封装结构,其特征在于,所述第三信号与所述第一信号同步变化,且变化的大小及变化的方向相同。The multi-chip package structure according to claim 8, wherein the third signal changes synchronously with the first signal, and the magnitude of the change and the direction of the change are the same.
  12. 根据权利要求8所述的多芯片封装结构,其特征在于,所述第三信号随所述第一信号的变化而变化。The multi-chip package structure of claim 8 wherein said third signal varies as said first signal changes.
  13. 根据权利要求12所述的多芯片封装结构,其特征在于,所述第三信号随所述第一信号的升高而升高、随所述第一信号的降低而降低。The multi-chip package structure according to claim 12, wherein said third signal rises as said first signal rises and decreases as said first signal decreases.
  14. 根据权利要求11或13所述的多芯片封装结构,其特征在于,所述第三信号的幅度变化大小与所述第一信号的幅度变化大小对应相同。The multi-chip package structure according to claim 11 or 13, wherein the magnitude of the amplitude change of the third signal is the same as the magnitude of the amplitude change of the first signal.
  15. 根据权利要求8所述的多芯片封装结构,其特征在于,所述多芯片封装结构包括散热片,所述散热片由导电材料制成,所述散热片用于散热,还用于作为所述信号电极。The multi-chip package structure according to claim 8, wherein the multi-chip package structure comprises a heat sink, the heat sink is made of a conductive material, the heat sink is used for heat dissipation, and is also used as the Signal electrode.
  16. 根据权利要求15所述的多芯片封装结构,其特征在于,所述第一芯片与所述第二芯片均设置在所述散热片上,其中,所述第一芯片与所述散热片之间设置导电层,所述第二芯片与所述散热片之间设置绝缘层。The multi-chip package structure according to claim 15, wherein the first chip and the second chip are both disposed on the heat sink, wherein a setting between the first chip and the heat sink is The conductive layer is provided with an insulating layer between the second chip and the heat sink.
  17. 根据权利要求16所述的多芯片封装结构,其特征在于,所述散热片与所述第一芯片的接地端通过所述导电层连接。The multi-chip package structure according to claim 16, wherein the heat sink is connected to a ground end of the first chip through the conductive layer.
  18. 根据权利要求8所述的多芯片封装结构,其特征在于,所述多芯片封装结构进一步包括衬底,所述第一芯片与所述第二芯片设置在所述衬底上,所述衬底上设置所述信号电极。The multi-chip package structure according to claim 8, wherein the multi-chip package structure further comprises a substrate, the first chip and the second chip are disposed on the substrate, the substrate The signal electrode is disposed on the upper side.
  19. 根据权利要求18所述的多芯片封装结构,其特征在于,所述信号电极环绕第一芯片。The multi-chip package structure according to claim 18, wherein the signal electrode surrounds the first chip.
  20. 根据权利要求19所述的多芯片封装结构,其特征在于,所述信号电极进一步环绕第二芯片。 The multi-chip package structure according to claim 19, wherein the signal electrode further surrounds the second chip.
  21. 根据权利要求18所述的多芯片封装结构,其特征在于,所述信号电极为一整层电极,设置在第一芯片与所述衬底之间,与所述第一芯片和衬底层叠设置,沿垂直层叠方向,所述信号电极的边缘超出所述第一芯片的边缘。The multi-chip package structure according to claim 18, wherein the signal electrode is a whole layer electrode disposed between the first chip and the substrate, and is stacked with the first chip and the substrate The edge of the signal electrode extends beyond the edge of the first chip in a vertical stacking direction.
  22. 根据权利要求18所述的多芯片封装结构,其特征在于,所述第一芯片与所述第二芯片设置在所述衬底的同一侧或相对两侧。The multi-chip package structure according to claim 18, wherein the first chip and the second chip are disposed on the same side or opposite sides of the substrate.
  23. 根据权利要求1所述的多芯片封装结构,其特征在于,所述第一芯片为感测芯片,所述第二芯片为控制芯片。The multi-chip package structure according to claim 1, wherein the first chip is a sensing chip, and the second chip is a control chip.
  24. 根据权利要求23所述的多芯片封装结构,其特征在于,所述第一芯片为指纹感测芯片或触控感测芯片。The multi-chip package structure according to claim 23, wherein the first chip is a fingerprint sensing chip or a touch sensing chip.
  25. 根据权利要求1所述的多芯片封装结构,其特征在于,所述第一芯片包括传感器板,所述传感器板用于以电容方式耦合到目标物体,所述第一芯片通过提供激励信号给所述传感器板以驱动所述传感器板执行感测操作,以获得所述目标物体的预定信息,其中,所述激励信号随所述第一信号的变化而变化。The multi-chip package structure according to claim 1, wherein said first chip comprises a sensor board for capacitively coupling to a target object, said first chip providing an excitation signal to said The sensor board drives the sensor board to perform a sensing operation to obtain predetermined information of the target object, wherein the excitation signal changes as the first signal changes.
  26. 根据权利要求25所述的多芯片封装结构,其特征在于,所述激励信号随所述第一信号的升高而升高、随所述第一信号的降低而降低。The multi-chip package structure according to claim 25, wherein said excitation signal rises as said first signal rises and decreases as said first signal decreases.
  27. 一种多芯片封装结构,包括:A multi-chip package structure comprising:
    第一芯片,包括接地端,所述接地端用于加载变化的信号;和a first chip comprising a ground end for loading a varying signal; and
    第二芯片,包括接地端,所述接地端用于加载恒定的信号。The second chip includes a ground terminal for loading a constant signal.
  28. 根据权利要求27所述的多芯片封装结构,其特征在于,所述第二芯片包括信号传输端,所述信号传输端与所述第一芯片的接地端连接,用于输出所述变化的信号给所述第一芯片的接地端。The multi-chip package structure according to claim 27, wherein the second chip comprises a signal transmission end, and the signal transmission end is connected to a ground end of the first chip for outputting the changed signal Giving the ground of the first chip.
  29. 一种电子设备,所述电子设备包括如权利要求1-28中任意一项所述的多芯片封装结构。An electronic device comprising the multi-chip package structure of any one of claims 1-28.
  30. 一种电子设备,包括一多芯片封装结构和设备地端,所述多芯片封装结构包括:An electronic device includes a multi-chip package structure and a device ground, the multi-chip package structure including:
    第一芯片,包括接地端,所述接地端用于加载变化的信号;和 a first chip comprising a ground end for loading a varying signal; and
    第二芯片,包括接地端,所述接地端与所述设备地端连接。The second chip includes a ground end connected to the ground end of the device.
  31. 根据权利要求30所述的电子设备,其特征在于,所述第二芯片包括信号传输端,所述信号传输端与所述第一芯片的接地端连接,用于输出所述变化的信号给所述第一芯片的接地端。The electronic device according to claim 30, wherein the second chip comprises a signal transmission end, and the signal transmission end is connected to a ground end of the first chip for outputting the changed signal to the The ground terminal of the first chip.
  32. 根据权利要求30所述的电子设备,其特征在于,所述电子设备包括供电电源,所述供电电源包括正极与负极,所述负极为所述设备地端。 The electronic device according to claim 30, wherein the electronic device comprises a power supply, the power supply comprises a positive pole and a negative pole, and the negative pole is a ground end of the equipment.
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