JP2008258775A - Method for designing integrated circuits comprising logical function circuit and self-diagnosis circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for designing integrated circuits comprising a logical function circuit and a self-diagnosis circuit, wherein an error detection rate can be easily calculated, a node to be monitored can be easily optimized and a node cover rate is high. <P>SOLUTION: The method comprises a first step S1 for composing test integrated circuits KT on the basis of a monitor node test list LM, a second step S2 for executing fault simulation and judging whether or not a toggle of each node can be detected by the self-diagnosis circuit KC, a third step S3 for calculating an error detection rate from the toggle detection possibility judgment result, and a fourth step S4 for judging whether or not the error detection rate is a standard error detection rate and more; wherein, when the error detection rate is less than the standard error detection rate, the monitor node test list LM is changed and processing is returned to the first step S1, and when the error detection rate is the standard error detection rate and more, the test integrated circuits KT are adopted to end the design of the integrated circuits. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a design of an integrated circuit comprising a logic function circuit configured by connecting logic elements so as to exhibit a predetermined function, and a self-diagnostic circuit for monitoring the state of a predetermined node in the logic function circuit. Regarding the method.

  A logic integrated circuit with a diagnostic function and a design method thereof are disclosed in Japanese Patent Laid-Open No. 2000-8892 (Patent Document 1).

In recent years, a functional safety standard such as IEC61508 has been established, and in a logic function circuit configured by connecting logic elements so as to exhibit a predetermined function, a malfunction of the logic function circuit is detected by a self-diagnosis circuit, and normal There is a need for a design that can restore operation. Specifically, when the output terminal (error detection terminal) of the self-diagnosis circuit is inserted into the interrupt terminal of a control circuit such as a CPU, and a malfunction occurs during actual use of the logic function circuit, the self-diagnosis circuit detects the malfunction. An error signal is output, and the CPU recognizes the input of the error signal and takes measures to operate the device safely.
JP 2000-8892 A

  In designing the logic function circuit, a logic simulator is usually used.

  FIG. 4 is a diagram for explaining a method for designing an integrated circuit including the logic function circuit and the self-diagnosis circuit using a logic simulator.

  The integrated circuit KT shown in FIG. 4 includes a logic function circuit KL and a self-diagnosis circuit KC. The logic function circuit KL is a circuit configured by connecting various logic elements so as to exhibit a predetermined function. The logic function circuit KL is designed using a logic simulator so that a predetermined logic function circuit output can be obtained when a function test pattern based on the actual operation state is input as shown in FIG.

  The self-diagnosis circuit KC of the integrated circuit KT shown in FIG. 4 is a state of a predetermined node indicated by a black circle among a plurality of nodes (connection points) of logic elements indicated by white circles and black circles in the figure in the logic function circuit KL. Is a circuit that detects the presence or absence of a failure in the logic function circuit KL. To optimally design the self-diagnosis circuit KC, the node of the logic function circuit KL monitored by the self-diagnosis circuit KC is optimally set, and the node coverage rate at which the self-diagnosis circuit KC detects an error is maximized. It is necessary to judge whether it has been.

  Therefore, using the logic simulator shown in FIG. 4, the error detection rate (%) of the self-diagnosis circuit KC is calculated by the following procedure, and it is determined whether the node monitored by the self-diagnosis circuit KC is appropriate. That is, as shown in FIG. 4, (1) by using the FORCE command of the logic simulator, a predetermined node of the logic function circuit KL is stacked at 0 or 1 as shown by a thick x mark in the figure, Force a failure on the node. (2) The logic function circuit output when the predetermined node is stacked and the self-diagnosis circuit output are collated to determine whether an error is detected in the self-diagnosis circuit KC. (3) The above steps (1) and (2) are performed by changing the stacked nodes, and the error detection rate of the self-diagnosis circuit KC is calculated by integrating these results. (4) Steps (1) to (3) are performed by changing the node monitored by the self-diagnostic circuit KC, and the error detection rate of the self-diagnostic circuit KC when the monitored node is changed is compared. It is determined whether the node monitored by the diagnostic circuit KC is appropriate.

  As described above, when the logic simulator used for designing the logic function circuit KL is used, the quality of the node of the logic function circuit KL monitored by the self-diagnosis circuit KC is determined, and the self-diagnosis circuit KC is optimally designed. It is possible. However, in the design method using the logic simulator, it is necessary to perform simulation by stacking all the nodes of the logic function circuit KL one by one with the FORCE command and checking the logic function circuit output and the self-diagnosis circuit output. Therefore, if an error detection rate maximized by a large-scale logic function circuit is obtained, the verification becomes enormous.

  Therefore, the present invention is an integrated circuit design method comprising a logic function circuit and a self-diagnosis circuit that detects the presence or absence of a failure by monitoring a predetermined node of the logic function circuit. The error detection rate of the self-diagnostic circuit can be calculated easily, the optimization of the nodes monitored by the self-diagnostic circuit is easy, and the node coverage rate at which the self-diagnostic circuit detects errors is high. An object of the present invention is to provide an integrated circuit design method comprising a circuit and a self-diagnosis circuit.

  The invention according to claim 1 is, among a logic function circuit configured by connecting logic elements so as to exhibit a predetermined function, and a plurality of nodes (connection points) of the logic elements in the logic function circuit, An integrated circuit design method comprising: a self-diagnosis circuit that detects the presence or absence of a failure of the logic function circuit by monitoring a state of a predetermined node, wherein a monitor node test list monitored by the self-diagnosis circuit Creating a first step of connecting the logic function circuit and the self-diagnosis circuit based on the monitor node test list to configure a test integrated circuit, and performing a failure simulation of the test integrated circuit, A second step for determining whether or not the self-diagnostic circuit can detect the toggle of each of the plurality of logic function circuits in the test integrated circuit. A third step of calculating a ratio of nodes that can be toggle-detected with respect to the plurality of nodes from the result of determination of toggle detection of each node as an error detection rate of the test integrated circuit; And a fourth step of determining whether or not the error detection rate is equal to or higher than a predetermined standard error detection rate. In the fourth step, the error detection rate of the test integrated circuit is greater than the standard error detection rate. If smaller, change the monitor node test list, return to the first step, perform the steps after the first step, and the error detection rate of the test integrated circuit is greater than or equal to the standard error detection rate Adopts a test integrated circuit configured based on the monitor node test list in the first step, and finishes the design of the integrated circuit. It is characterized in that.

  The integrated circuit design method including the logic function circuit and the self-diagnosis circuit uses a failure simulator in determining and optimizing the nodes of the logic function circuit monitored by the self-diagnosis circuit. The failure simulator does not cause an error by stacking the nodes of the logic function circuit by the FORCE command like the logic simulator, and which node toggles with respect to the function test pattern input to the logic function circuit, It can be logically determined whether or not the toggle state can be detected from the outside (that is, by a self-diagnostic circuit). As described above, if the failure simulator is used, it is possible to determine whether or not the toggle state can be detected for all the nodes of the logic function circuit in one simulation.

  Using the fault simulator toggle detection enable / disable determination function, the integrated circuit design method calculates the error detection rate of the self-diagnostic circuit in the test integrated circuit based on one monitor node test list in one simulation. To do. Therefore, in the integrated circuit design method, it is not necessary to stack all the nodes one by one and repeat the simulation as in the case of using a logic simulator in order to obtain an error detection rate related to one monitor node test list. In addition, since the self-diagnostic circuit finds a node whose toggle is not detected in one simulation of the test integrated circuit based on the one monitor node test list, the node to be monitored by the self-diagnostic circuit to be changed is selected. Becomes easy. For this reason, in the integrated circuit based on the monitor node test list to be tested next, the probability of improving the error detection rate of the self-diagnosis circuit is further increased.

  As described above, the integrated circuit design method including the logic function circuit and the self-diagnosis circuit includes a logic function circuit and a self-diagnosis that detects the presence or absence of a failure by monitoring a predetermined node of the logic function circuit. A method for designing an integrated circuit comprising a circuit, which can easily calculate an error detection rate of a self-diagnostic circuit even for a large-scale logic function circuit, and optimizes a node monitored by the self-diagnostic circuit. An integrated circuit design method including a logic function circuit and a self-diagnosis circuit, which is easy and has a high node coverage ratio where the self-diagnosis circuit detects an error, can be provided.

  In the integrated circuit design method comprising the logic function circuit and the self-diagnosis circuit, the actual operation of the logic function circuit is performed during the failure simulation of the test integrated circuit in the second step. It is preferable to input a function test pattern based on the state. As a result, the node coverage rate at which the self-diagnostic circuit in the state close to the actual operation of the logic function circuit detects an error can be determined. Therefore, the integrated circuit composed of the logic function circuit and the self-diagnosis circuit designed by the design method can ensure high functional safety performance even in actual operation.

  The integrated circuit design method including the logic function circuit and the self-diagnosis circuit can be applied to a case where the integrated circuit is configured as a single LSI.

  In this case, the integrated circuit design method including the logic function circuit and the self-diagnosis circuit can be applied to a case where the number of output pins of the self-diagnosis circuit is one as described in claim 4. .

  The present invention relates to a logic function circuit configured by connecting logic elements so as to exhibit a predetermined function, and a state of a predetermined node among a plurality of nodes (connection points) of the logic elements in the logic function circuit. The present invention relates to a method for designing an integrated circuit comprising a self-diagnosis circuit that detects the presence or absence of a failure in a logic function circuit by monitoring. The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram for explaining a method of designing an integrated circuit comprising the above-described logic function circuit and self-diagnosis circuit of the present invention. FIG. 2 is a flowchart showing the design procedure of the integrated circuit design method comprising the above-described logic function circuit and self-diagnosis circuit of the present invention.

  The integrated circuit KT shown in FIG. 1 is the same as the integrated circuit KT shown in FIG. 4 and includes a logic function circuit KL and a self-diagnosis circuit KC. The logic function circuit KL is a circuit configured by connecting various logic elements so as to exhibit a predetermined function. As described in FIG. 4, the logic function circuit KL is designed using a logic simulator so that a predetermined logic function circuit output can be obtained when a function test pattern based on an actual operation state is input.

  Further, the self-diagnosis circuit KC of the integrated circuit KT shown in FIG. 1 is a predetermined node indicated by a black circle among a plurality of nodes (connection points) of logic elements indicated by white circles and black circles in the figure in the logic function circuit KL. By monitoring this state, the circuit detects the presence or absence of a failure in the logic function circuit KL.

  The internal configuration of the self-diagnosis circuit KC is also designed using a logic simulator. In addition, in order to optimally design the self-diagnosis circuit KC, not only the internal configuration but also the node of the logic function circuit KL monitored by the self-diagnosis circuit KC is optimally set. It is necessary to determine whether or not the detected node coverage is maximized. The self-diagnosis circuit KC in the integrated circuit KT in FIG. 1 desirably has a high node coverage with as few monitor points as possible.

  For this reason, in the design method of the integrated circuit KT including the logic function circuit KL and the self-diagnosis circuit KC shown in FIGS. 1 and 2, the error detection rate (%) of the self-diagnosis circuit KC is calculated using a failure simulator. Then, it is determined whether the node monitored by the self-diagnosis circuit KC is appropriate, and the optimum integrated circuit KT is designed. Hereinafter, the design procedure will be described with reference to FIGS.

  First, in the first step S1 shown in FIG. 2, the first monitor node test list LM (1) monitored by the self-diagnosis circuit KC of FIG. 1 is created. Based on the monitor node test list LM (1), the logic function circuit KL and the self-diagnosis circuit KC are connected to form the test integrated circuit KT (1) used for the first test.

  Next, in the second step S2 shown in FIG. 2, a failure simulation of the test integrated circuit KT (1) is performed, and self-diagnosis is performed on the toggle of each of the plurality of logic function circuits KL in the test integrated circuit KT (1). Whether or not detection by the circuit KC is possible is determined.

  Next, in the third step S3 shown in FIG. 2, as the error detection rate of the test integrated circuit KT (1), from the toggle detection availability determination result (toggle detection availability determination list LT (1) in FIG. 1) of each node, The ratio of nodes capable of toggle detection is calculated for a plurality of nodes.

  Next, in the fourth step S4 shown in FIG. 2, it is determined whether or not the error detection rate of the test integrated circuit KT (1) is equal to or higher than a predetermined standard error detection rate.

  If the error detection rate of the test integration circuit KT (1) is smaller than the standard error detection rate in the fourth step S4, the monitor node test list LM (1) is displayed in the next monitor in the fifth step S5 shown in FIG. The node test list LM (2) is changed to return to the first step S1, and steps S2 to S4 after the first step S1 are performed on the second test integration circuit KT (2).

  In the fourth step S4, when the error detection rate of the test integration circuit KT (1) is equal to or higher than the standard error detection rate, the test integration circuit configured based on the monitor node test list LM (1) in the first step S1 The design of the integrated circuit KT is completed by adopting KT (1).

  The designing method of the integrated circuit KT including the logic function circuit KL and the self-diagnosis circuit KC shown in FIGS. 1 and 2 determines and optimizes the node of the logic function circuit KL monitored by the self-diagnosis circuit KC. In this case, a failure simulator is used. Like the logic simulator, the fault simulator does not cause an error by stacking the nodes of the logic function circuit KL with the FORCE command, and which node is toggled with respect to the function test pattern input to the logic function circuit KL. Then, it can be logically determined whether or not the toggle state can be detected from the outside (that is, by a self-diagnosis circuit).

  FIG. 3 is a diagram for specifically explaining the toggle detection capability determination function by the failure simulator described above with a simple integrated circuit. FIG. 3A is a configuration diagram of an integrated circuit KTa composed of a simple logic function circuit KLa and a self-diagnosis circuit KCa, and FIG. 3B is a diagram summarizing the toggle detection feasibility determination result by the failure simulator. .

  FIG. 3A shows the nodes Dtrue, A1, B1, C1, A2, B2, C2, Dout, and ERR of the logic function circuit KLa and the self-diagnosis circuit KCa in the integrated circuit KTa. Each table in FIG. 3 (b) is created for normal cases and when each node Dtrue, A1, B1, C1, A2, B2, C2, Dout, ERR is normal, and stacked in 0 and 1, respectively. Is done. For example, the second table from the top in FIG. 3B shows the case where the node A1 is stacked at 0. In this case, when the input A is 1 and the input B is 0, an error also occurs in the nodes C1 and Dout. appear. The error at this time can be detected by outputting to the node ERR of the self-diagnosis circuit KCa, but cannot be detected when both the input A and the input B are 1. The toggle detection availability determination list LT shown in FIG. 1 can be created from the results of all the tables shown in FIG. 3B, and the error detection rate of the self-diagnostic circuit KCa can be calculated therefrom.

  As described above, if the failure simulator is used, it is possible to determine whether or not the toggle state can be detected for all the nodes of the logic function circuit KL in one simulation. By utilizing the toggle detection capability determination function of this failure simulator, the design method of the integrated circuit KT shown in FIGS. 1 and 2 is a test integration based on one monitor node test list LM (1) in one simulation. The error detection rate of the self-diagnosis circuit in the circuit KT (1) is calculated. Therefore, in the design method of the integrated circuit KT shown in FIGS. 1 and 2, in order to obtain an error detection rate related to one monitor node test list LM (1), all nodes are pointed one by one as in the case of using a logic simulator. There is no need to stack and repeat the simulation. In addition, since the self-diagnostic circuit KC finds a node whose toggle cannot be detected in one simulation of the test integrated circuit KT (1) based on one monitor node test list LM (1), The node to be monitored by the diagnostic circuit KC can be easily selected. For this reason, in the integrated circuit KT (1) based on the monitor node test list LM (2) to be tested next, the probability of improving the error detection rate of the self-diagnosis circuit KC is further increased.

  As described above, the design method of the integrated circuit KT shown in FIGS. 1 and 2 includes the logic function circuit KL and a self-diagnosis circuit that detects the presence or absence of a failure by monitoring a predetermined node of the logic function circuit KL. A method of designing an integrated circuit KT including KC, which can easily calculate the error detection rate of the self-diagnostic circuit KC even for a large-scale logic function circuit KL, and is a node monitored by the self-diagnostic circuit KC The design method of the integrated circuit KT composed of the logic function circuit KL and the self-diagnosis circuit KC, which is easy to optimize, and has a high node coverage rate at which the self-diagnosis circuit KC detects an error, can be obtained.

  In the design method of the integrated circuit KT including the logic function circuit KL and the self-diagnosis circuit KC shown in FIGS. 1 and 2, in the second step S2 of FIG. 2, during the failure simulation of the test integrated circuit KT (1). As shown in FIG. 1, it is preferable to input a function test pattern based on the actual operation state of the logic function circuit KL. Thereby, it is possible to determine the node coverage rate at which the self-diagnosis circuit KC in the state close to the actual operation of the logic function circuit KL detects an error. Therefore, the integrated circuit KT including the logic function circuit KL and the self-diagnosis circuit KC designed by the design method can ensure high functional safety performance even in actual operation.

  Further, the design method of the integrated circuit KT including the logic function circuit KL and the self-diagnosis circuit KC shown in FIGS. 1 and 2 is the case where the integrated circuit KT is configured as one LSI as shown in FIG. It is also applicable to.

  In this case, the design method of the integrated circuit KT including the logic function circuit KL and the self-diagnosis circuit KC shown in FIGS. 1 and 2 is as follows. As shown in FIG. It is also applicable to

It is a figure explaining the design method of the integrated circuit which consists of the logic function circuit and self-diagnosis circuit of this invention. It is a flowchart which shows the design procedure of the design method of the integrated circuit which consists of the logic function circuit and self-diagnosis circuit of this invention. FIG. 3A is a diagram for specifically explaining the toggle detection capability determination function by the failure simulator using a simple integrated circuit. FIG. 3A is a configuration diagram of an integrated circuit KTa including a simple logic function circuit KLa and a self-diagnosis circuit KCa. (B) is the figure which put together the toggle detection availability determination result by a failure simulator. It is a figure explaining the design method of the integrated circuit which consists of a logic function circuit and a self-diagnosis circuit using a logic simulator.

Explanation of symbols

KL, KLa Logic function circuit KC, KCa Self-diagnosis circuit KT, KTa Integrated circuit LM Monitor node test list LT Toggle detection availability determination list

Claims (4)

A logic function circuit configured by connecting logic elements so as to exhibit a predetermined function;
An integrated circuit comprising: a self-diagnosis circuit that detects the presence or absence of a failure of the logic function circuit by monitoring a state of a predetermined node among a plurality of nodes (connection points) of the logic elements in the logic function circuit Design method,
Creating a monitor node test list to be monitored by the self-diagnosis circuit, connecting the logic function circuit and the self-diagnosis circuit based on the monitor node test list, and configuring a test integrated circuit;
Perform a failure simulation of the test integrated circuit,
A second step of determining whether or not the self-diagnostic circuit can detect the toggle of each of the plurality of nodes of the logic function circuit in the test integrated circuit;
A third step of calculating, as an error detection rate of the test integrated circuit, a ratio of nodes capable of toggle detection with respect to the plurality of nodes from a toggle detection availability determination result of each node;
A fourth step of determining whether an error detection rate of the test integrated circuit is equal to or higher than a predetermined standard error detection rate,
In the fourth step,
When the error detection rate of the test integrated circuit is smaller than the standard error detection rate, the monitor node test list is changed, the process returns to the first step, and the steps after the first step are performed.
When the error detection rate of the test integrated circuit is equal to or higher than the standard error detection rate, the test integrated circuit configured based on the monitor node test list in the first step is adopted, and the design of the integrated circuit is completed. An integrated circuit design method comprising a logic function circuit and a self-diagnosis circuit. In the second step, at the time of failure simulation of the test integrated circuit,
2. The integrated circuit design method comprising a logic function circuit and a self-diagnosis circuit according to claim 1, wherein a function test pattern based on an actual operation state of the logic function circuit is input.   3. The integrated circuit design method comprising a logic function circuit and a self-diagnosis circuit according to claim 1, wherein the integrated circuit is configured as one LSI.   4. The method for designing an integrated circuit comprising a logic function circuit and a self-diagnosis circuit according to claim 3, wherein the number of output pins of the self-diagnosis circuit is one.

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