JPH0887538A - Design method for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To provide a design method which can shorten the designing time of a semiconductor integrated circuit. CONSTITUTION: A scanning test cent arrangement area is secured in a scanning test cell arrangement position securing process S31 and at the same time the scan control signals are distributed. Then an ordinary logic part is secured in addition to the scanning test cell arrangement area (S32), and the real wiring length is extracted (S33). On the other hand, the permuting and inserting positions are decided for the scanning test cells (S21). Then the scanning test cells are permuted and inserted in a logic circuit (S22). These processes can be carried out in parallel and independently of each other. The timing of the virtual wiring length including the scanning test cells is verified (S23) based on the real wiring length extracted in the process S33. Then the scanning test cells are arranged and wired (S34). A scanning sequence is decided (S35) and a logical scan path is generated (S24). Then the scan path is actually wired (S36).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout designing method for semiconductor integrated circuits using a scan path test cell system, such as layout and wiring.

[0002]

2. Description of the Related Art In recent years, in order to facilitate testing of semiconductor integrated circuits, test circuit cells such as latches and registers have been previously inserted in various places of a general circuit, and the manufactured semiconductor integrated circuits have to be manufactured. A scan-path test using this test circuit cell has been performed. Such a test circuit cell, that is, a scan test cell needs to be incorporated together with a general circuit at the time of layout of the semiconductor integrated circuit.

FIG. 8 is a flow chart showing a conventional method for designing a semiconductor integrated circuit. In S1, the logic of the circuit to be integrated in the semiconductor integrated circuit is designed. Then S
In 2, the logic design of the scan test cell is performed. In S3, based on the logic design of the S1 and the scan test cell designed in S2, a layout design for physically realizing them is performed. Finally, in S4, simulation such as timing verification is performed using the actual wiring length after the layout design in S3.

Further, in the logic design of the scan test cell in S2, it is determined in S21 which part of the general logic circuit is to be replaced or inserted with the scan test cell, and in S22, the scan test cell is actually scanned into the logic circuit. The timing is verified by simulation using the virtual wiring length after replacing and inserting the test cell and replacing and inserting the scan test cell in S23.

In such a method, since the logic design in S1 to the actual wiring length simulation in S4 must be sequentially executed, there is a drawback that the design time becomes long. Also, the simulation of the actual wiring length can be performed only after laying out all the circuits including the scan test cells, and when it is necessary to go back to the logic design stage and make corrections, it is not necessary. Even if there is, the logic design and layout design of the scan test cell must be redone, which further increases the design time.

As a conventional method for designing a semiconductor integrated circuit, there is, for example, a method described in Japanese Patent Application Laid-Open No. 4-96252. In this document, the layout is performed when the scan register is not replaced, the scan register is replaced using the layout information, the scan register connection, that is, the scan chain is determined, and the determined scan chain is Test vectors are created according to the information. With such technology,
The scan register and the scan chain can be automatically inserted, and the layout design can be facilitated.
However, the steps shown in FIG. 8 are not changed, and it is inevitable that the design time is lengthened by sequentially executing the steps.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a design method capable of shortening the design time of a semiconductor integrated circuit.

[0008]

According to the present invention, in a method of designing a semiconductor integrated circuit having a test circuit cell for performing a test by a scan path method, a region for arranging the test circuit cell is secured, and the test circuit cell is secured. Other general circuit cells are arranged, the test circuit cells are arranged in the previously reserved test circuit cell arrangement area, and the layout is determined.

When securing the placement area of the test circuit cell, a control signal line for connecting the test circuit cell placed in the placement area may be wired.

[0010]

According to the present invention, it is possible to proceed with the layout design without requiring information about the logic design of the test circuit cell until the layout of the general circuit cell is completed.
Therefore, the logic design and layout design of the test circuit cell can be performed in parallel. Also, since the layout of the general circuit cell is performed independently of the logic design of the test circuit cell, even if a mistake in the layout of the general circuit cell is found, it has an influence on the logic design of the test circuit cell. It can be modified without. Further, since the actual wiring length of the general circuit cell is determined when the layout of the general circuit cell is completed, it is possible to perform a test using this information when simulating the circuit wiring length of the test circuit cell. The test circuit cell side can be corrected early.

[0011]

1 is a flow chart showing an embodiment of a method for designing a semiconductor integrated circuit according to the present invention. In S1, a logic design process for determining the logic circuit of the general circuit cell is performed. In S2, a scan design process for facilitating the test is performed. In S3, a layout design process for physically laying out the general circuit cell logically designed in S1 and the scan test cell scan-designed in S2 is performed. In S4, the actual wiring length simulation after the layout design in S3 is performed, and the actual wiring length simulation process for verifying the timing is performed.

As the scan design process performed in S2, the following processes are performed. In S21,
Scan test cell position determination processing is performed to determine which portion of the logic circuit the test cell is to be replaced with and inserted. In S22, a scan test cell replacement / insertion process of replacing and inserting a scan test cell in the logic circuit is performed. In S23, the virtual wiring length of the scan portion after the scan test cell is replaced and inserted, and S3
A virtual wiring length simulation process for verifying the timing is performed using the actual wiring length of the general logic portion extracted in 3. In S24, a scan path generation process for creating a scan test cell scan path according to the layout design in S3 is performed.

As the layout design process performed in S3, the following processes are performed. In S31, a scan test cell placement position securing process for securing a region where the scan test cells are placed is performed. In step S32, a general logic section layout design process is performed for placing and wiring the general logic section excluding the scan test cells. In S33, an actual wiring length extracting process for extracting the actual wiring length as a result of S32 is performed. In S34, a scan test cell placement process of placing the scan test cell determined in S21 at the position secured in S31 is performed. In S35, the scan test cell position extraction process of 35 for determining the order of the scan test cell chain necessary for creating the test vector is performed. In S36, a scan path wiring process for realizing the scan path determined in S24 is performed.

Next, the flow of the design method of the present invention will be described using a specific example. FIG. 2 is a schematic diagram showing a specific example of the layout according to the design method of the present invention. In the figure, 41 is a semiconductor integrated circuit, 42 is an I / O unit, T1 to Tn are scan test cells, TE, SE and TC are scan control signals, SI and SO are scan signals, and DI1 to DIn.
Is an internal data observation signal, and DO1 to DOn are internal data control signals. In the following description, the case of obtaining the layout shown in FIG. 2 will be described.

In the semiconductor integrated circuit 41, a plurality of scan test cells T1 to Tn are arranged. Each of the scan test cells T1 to Tn has a scan control signal T
E, SE, TC are input. Scan signal T
E and SE are signals for setting the operation modes of the scan test cells T1 to Tn, and the scan signal T
C is a signal for supplying a timing for operating each of the scan test cells T1 to Tn. The scan signals TE, SE, TC are I / O of the semiconductor integrated circuit 41.
It is given from the outside through the O section 42.

The scan signal SI of the scan test cell T1 is externally input with the scan signal SI via the I / O section 42. Scan test cell T2
The terminals of the scan signal SI of Tn are connected to the terminals of the scan signal SO of the other scan test cells T1 to Tn-1, and the scan test cells T1 to Tn are serially connected. Then, the scan signal SO is output to the outside from the terminal of the scan signal SO of the scan test cell Tn via the I / O unit 42. Here, all the scan test cells are serially connected, but a configuration in which some scan cells are serially connected may be used. When performing the test, the operating state of the general logic portion can be grasped by externally applying the scan signal SI and observing the scan signal SO, and the semiconductor integrated circuit 41 can be tested.

Each of the scan test cells T1 to Tn includes:
The internal data observation signals DI1 to DIn are input and the internal data control signals DO1 to DOn are output, respectively. The internal data observation signals DI1 to DIn are signals output from a general logic circuit (general logic unit), and are signals to be observed during a test. Also,
The internal data control signals DO1 to DOn are signals input to the general logic unit, and the internal data observation signals DI1 to DIn should be input during normal operation.
During the test, the internal data control signals DO1 to DO
Various tests can be performed by creating and giving n. Internal data control signals DO1 to DO
n can be given by the scan signal SI, and the internal data observation signals DI1 to DIn at that time can be obtained by observing the scan signal SO.

FIG. 3 is a schematic diagram showing an example of a scan chain circuit at the time of replacement with a scan test cell, and FIG. 4 is a schematic diagram showing an example of a scan chain circuit at the time of inserting a scan test cell. Reference numerals 51 to 53 are general logic units. The scan test cell may be arranged by replacing a circuit cell such as a latch or a register in the general logic part created by the logic design, or may be arranged outside the general logic part and inserted in the general logic part. . In FIG. 3, the general logic section 51 and the general logic section 5 are shown.
2 shows an example in which the circuit cells provided between No. 2 and the circuit cells provided between the general logic unit 52 and the general logic unit 53 are replaced with scan test cells T1 to T4. Replaced scan test cell T1
To T4 are serially connected by the scan signals SI and SO, respectively, and the scan control signal T
E, SE, and TC are input in parallel.

In FIG. 4, with respect to the general logic section 51,
The scan test cells T1 to Tn are prepared, and the scan test cells T1 to Tn are inserted into the n signal lines in the general logic section 51, respectively. That is, the signal on the signal line is the internal data observation signal D in the scan test cell.
The internal data control signals DO1 to DOn from the scan test cells are taken out as I1 to DIn and returned to the general logic unit 51 as signals on the original signal lines. The scan test cells T1 to Tn are serially connected by the scan signals SI and SO, respectively, and
Scan control signals TE, SE, and TC are input.

In the flow chart shown in FIG. 1, first, in S1, the logic design of the circuit of the general logic section is performed. Then, the logic design information of the general logic part is used in the scan design process of S2 and the layout design process of S3. The scan design process of S2 and the layout design process of S3 are performed in parallel while being mutually related.

First, in the scan design process of S2, S2
In the scan test cell position determining process of No. 1, the scan test cell is selected from among the logic circuits of the general logic unit.
It is determined which part should be replaced with the scan test cell or which part the scan test cell should be inserted into. For example, as shown in FIGS. 3 and 4, replacement and insertion positions of scan test cells in logic design are determined.
Then, in the scan test cell replacement / insertion process of S22, logical scan test cell replacement and insertion are performed with respect to the logic circuit of the general logic section, and a logic circuit including the scan test cell is created. .

Independently of the scan test cell position determining process of S21 and the scan test cell replacement inserting process of S22 in the scan design process, the scan test cell arrangement of S31 in the layout design process of S3 is performed. The position securing process, the general logic part layout designing process of S32, and the actual wiring length extracting process of S33 can be performed. These processes can be performed before or after the processes of S21 and S22, or in parallel.

First, in the scan test cell placement position securing process of S31, the layout surface of the semiconductor integrated circuit is
An arrangement area for arranging a number or more of scan test cells according to the circuit scale is secured in advance. Then, wiring for supplying scan control signals TE, SE, TC to each scan test cell is performed. At this time, at this time, the scan control signals TE and S
The scan test cells are arranged so that the terminals connected to E and TC have the same Y coordinate, and the scan control signals are wired. FIG. 5 is a layout diagram showing an example of a time point when the arrangement area of the scan test cells is secured. In the figure, Td
1 to Tdn are scan test cell placement regions. As shown in FIG. 5, the scan test cell placement region Td1
To Tdn are secured and scan control signals TE, SE, TC
Is wired. At this stage, only the arrangement area is secured, and the scan test cell is not arranged. Further, no wiring is provided except for the scan control signals TE, SE and TC.

Although the terminals of the test cells are set to have the same Y coordinate in FIG. 5, they may be set to have the same X coordinate depending on the configuration. In addition, when the scan test cells are arranged over a plurality of rows, they are connected like a single stroke in FIG. 5, but the present invention is not limited to this, and wiring in stripes is performed or divided into several blocks. It is possible to perform wiring in various shapes, such as wiring.

With respect to the layout of the semiconductor integrated circuit after the scan test cell layout area is secured in S31, the layout design of the general logic section is performed and the layout and wiring of the general logic section are performed in S32.
At this point, the wiring in the general logic section is fixed,
In the actual wiring length extraction processing of S33, the actual wiring length in the general logic part is extracted.

The information on the actual wiring length obtained in S33 is used in the scan design process in S2. In the virtual wiring length simulation processing of S23, the virtual wiring length of the scan portion after the scan test cells are replaced and inserted into the logic circuit in the scan test cell replacement insertion processing of S22, and the general logic extracted in S33. Using the actual wiring length of the section, simulation is performed to determine whether the operation timing of the general logic section is performed as specified, and the timing is verified. At this stage, the portion of the scan test cell remains as a logic circuit and layout is not performed.

Next, in the layout design process of S3, the scan test cells are actually laid out in the scan test cell placement process of S34. The scan test cells are placed in the scan test cell placement area secured by the scan test cell placement position securing process in S31. The layout of the scan test cell is
Each internal data observation signal and internal data control signal causes it to be placed near its general logic section.

6 and 7 are circuit diagrams showing an example after the scan test cell placement process. At this stage, S2
Since the scan test cells generated in S1 and S22 are only arranged, the wiring for the scan control signals TE, SE, and TC wired in S31 and the layout of the general logic part performed in S32 are performed. It is in a state of being. The scan signals SI and SO are not yet connected.
Therefore, as shown in FIGS. 6 and 7, the scan signal S
This means that the circuit in which I and SO are not connected is laid out.

Next, in the scan test cell position extraction processing of S35, first, the coordinates of each scan test cell are extracted. Further, the order in which the scan test cells are serially connected by the scan signal, that is, the shift clock connection order is determined. Then, the coordinates of the test cells for scanning are sequentially arranged according to the determined shift clock connection order.

Returning to the scan designing means of S2, the scan path generating means of S24 uses the scan signals SI, SO based on the shift clock connection order determined in S35 and the coordinate of the ordered scan test cell. Wiring is performed logically. This logical scan signal SI, S
Based on the wiring information of O, the scan path wiring means of S36 in the layout design processing of S3 carries out the wiring of the scan signals SI and SO to realize the circuit shown in FIGS. 3 and 4. The layout shown in is completed.

[0031]

As is apparent from the above description, according to the present invention, the area where the scan test cells are arranged is secured in advance of the other elements, and the scan test cells are arranged after the other elements are arranged. , Scan design and layout design can be performed in parallel. As a result, the debug of the general logic part and the debugging of the scan part can be performed independently, so that the development period can be shortened. Also,
Since the layout result of the general logic part can be reflected in the virtual wiring length simulation after inserting the scan test cell, the development period can be shortened. Even if a timing failure occurs at this time, the layout can be corrected at the same time as the scan test cell placement process and the scan path wiring process, so that the process is not wasted and efficient design is performed. be able to.
Further, since the scan control signal wiring can be connected to other signal wirings in advance, it is possible to easily perform a one-stroke connection method or a mesh-shaped connection, and it is possible to reduce skew. .

[Brief description of drawings]

FIG. 1 is a flowchart showing an embodiment of a method for designing a semiconductor integrated circuit of the present invention.

FIG. 2 is a schematic diagram showing a specific example of a layout according to the design method of the present invention.

FIG. 3 is a schematic diagram showing an example of a scan chain circuit when replacing with a scan test cell.

FIG. 4 is a schematic diagram showing an example of a scan chain circuit when a scan test cell is inserted.

FIG. 5 is a layout diagram showing an example of a time point when a placement area of scan test cells is secured.

FIG. 6 is a circuit diagram showing an example after a scan test cell replacement placement process.

FIG. 7 is a circuit diagram showing an example after a scan test cell insertion / arrangement process.

FIG. 8 is a flowchart showing a conventional method for designing a semiconductor integrated circuit.

[Explanation of symbols]

41 ... Semiconductor integrated circuit, 42 ... I / O section, 51-53 ...
General logic part, T1 to Tn ... scan test cell,
TE, SE, TC ... Scan control signals, SI, SO ...
Scan signals, DI1 to DIn ... Internal data observation signals,
DO1 to DOn ... Internal data control signals.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/3205 H01L 21/82 T 21/88 T

Claims (2)

[Claims] 1. A method of designing a semiconductor integrated circuit having a test circuit cell for performing a test by the scan path method, wherein an arrangement region of the test circuit cell is secured, and a general circuit cell other than the test circuit cell is arranged. Done,
A method of designing a semiconductor integrated circuit, comprising arranging the test circuit cells in a previously secured area for arranging the test circuit cells and determining a layout. 2. The semiconductor device according to claim 1, wherein a control signal line connecting the test circuit cells arranged in the arrangement region is wired when securing the arrangement region of the test circuit cell. Integrated circuit design method.