JP3389317B2 - Integrated circuit test circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for an integrated circuit, and more particularly to a test circuit for an integrated circuit which can effectively use an output terminal provided on the integrated circuit in a test mode.

[0002]

2. Description of the Related Art Generally, when manufacturing an integrated circuit, after the integrated circuit is built on a wafer, it is tested whether or not various functions of the integrated circuit operate normally in a wafer state. ing. Now, consider the case of testing the internal operation of an integrated circuit (microcomputer) or the like having a mask ROM (read only memory) built therein. Conventionally, no test program instruction is stored in the mask ROM.

Therefore, as a method of testing an integrated circuit having a built-in mask ROM, there is a method of newly providing a test terminal in addition to a normal input / output terminal in the integrated circuit. That is, when the test program is applied to the test terminal in a state where the integrated circuit is set to the test mode and the operation clock is supplied to the integrated circuit, the internal circuit of the integrated circuit operates according to the test program and a predetermined operation is performed. Arithmetic operation is executed. Then, the test operation is realized by outputting the arithmetic processing data from a normal output terminal and determining whether the arithmetic processing data is correct by an external tester.

Another method for testing an integrated circuit with a built-in mask ROM is to use a part of normal input / output terminals of the integrated circuit as a test terminal. In other words, by setting the integrated circuit to the test mode, some of the normal input / output terminals are switched to the test terminals to which the test program can be applied, and when the operating clock is supplied to the integrated circuit, the test program can be applied to the test terminal. Good. As a result, the arithmetic processing according to the test program is executed inside the integrated circuit. Then, the arithmetic operation data is output from the remaining output terminal, and the test operation is realized by determining the correctness of the arithmetic operation data by an external tester.

[0005]

However, in the former test method, since a new test terminal must be provided in addition to the normal input / output terminal, the total number of terminals of the integrated circuit increases, and as a result, the integrated circuit is increased. There is a problem that the pad area on the circuit increases and the chip size increases.

In the latter test method, if a part of the normal input / output terminals is used as a test terminal, it becomes impossible to test the input / output function of this input / output terminal. Therefore, conventionally, two blocks of normal input / output terminals used as test terminals are provided (for example, four test terminals are used).
When you need one, you can also use 4 normal input / output terminals x 2 blocks = 8 as test terminals.) If you want to test the input / output function of one input / output terminal block, the other input / output terminal block On the contrary, when it is desired to test the input / output function of the other input / output terminal block, the terminal function is switched so that one input / output terminal block can be used as the test terminal.
However, a selector for switching the terminal function must be provided for each dual-purpose terminal, resulting in a problem that the chip size becomes large.

Further, a writable and readable EEPROM capable of electrically erasing program data is built in an integrated circuit, a test program is written in the EEPROM when the integrated circuit is tested, and an EEPROM is stored when the integrated circuit is normally operated. Although there is a method of rewriting the contents into a normal program, there is a problem that it takes a lot of time to erase and write the program data, which makes it unsuitable for mass production of integrated circuits.

Therefore, an object of the present invention is to provide a test circuit for an integrated circuit in which an output terminal provided in the integrated circuit can be effectively used in a test mode.

[0009]

The present invention has been made to solve the above-mentioned problems, and is characterized in that a plurality of output terminals for outputting data are applied with test data. In a test circuit of an integrated circuit used as an input terminal, a plurality of test instructions for executing each test are stored in a first storage area, and at least the first storage area is accessed in a second storage area. The memory means storing a plurality of jump instructions, the first gate means for outputting the data from the output terminal, the address data for accessing the second storage area of the memory means from the output terminal, the test Second gate means for inputting as data into the integrated circuit, and stop operation of the first gate means while the integrated circuit is reset. Both of them operate the second gate means to output the test data, and after the integrated circuit is released from reset, the first gate means operate to output the data and the second gate means. Gate control signal generating means for generating a gate control signal for stopping the operation of the test circuit, and test data for holding and outputting the test data output from the second gate means while the integrated circuit is reset. While the holding output means and the integrated circuit are reset, the address data representing the start address of the second storage area of the memory means is preset, and after the integrated circuit is released from reset, the memory means is reset. Increment is performed from address data representing the first address of the second storage area,
The output content of the test data holding output means and the address counter means for accessing the memory means are compared with the count content of the address counter means, and a coincidence detection signal is generated when the output content and the count content match. Only when the comparison means and the coincidence detection signal are generated,
Instruction output means for outputting a jump instruction read from a predetermined address of the second storage area of the memory means, and a function of inputting the test data to the output terminal while the integrated circuit is reset. After the reset of the integrated circuit is released, the output terminal is set to the data output function in the test mode and the normal mode.

[0010]

According to the present invention, the test instruction is stored in the first storage area of the memory means incorporated in the integrated circuit, and the jump instruction branching to the first storage area is stored in the second storage area. Then, while the integrated circuit is reset, the output terminal is made to function so that address data (test data) for accessing the second storage area of the memory means can be input, and after the integrated circuit is released from reset, the output terminal is output. To output the data in the test mode and the normal mode. As a result, the output terminal can be used effectively.

[0011]

The details of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a test circuit of an integrated circuit of the present invention, which is assumed to be built in a microcomputer. In FIG. 1, (1) is a ROM in which program instructions for controlling the operation of the microcomputer are stored.
The storage area of the ROM (1) is roughly divided into an area for storing a system program such as initialization of the microcomputer, an area for storing a normal operation program of the microcomputer, and various types of the microcomputer. It is composed of an area (first storage) in which a function test program is stored and an area (second storage) in which a jump program to the first storage area is stored. Normally, the operation control program of the microcomputer is not stored in all the addresses of the ROM, and there are usually vacant addresses. So, using the vacant address,
The test program and the jump program are written and the storage area of the ROM is effectively used. The details are shown in FIG.

FIG. 2 is a diagram showing a concrete example of the program arrangement of the ROM (1). In FIG. 2, ROM (1)
Has a total number of addresses of 3FFFH (H indicates hexadecimal. The display of H is omitted hereinafter). Then, in the ROM (1), a system program is stored at addresses 0000 to 000F, and 0010 to XXXX.
The normal operation program is stored in the address (the address immediately before the address a), the test program is stored in the addresses a to 3FEF, and the jump program is stored in the addresses 3FF0 to 3FFF. Particularly, in the present embodiment, the details of the first storage area of the ROM (1) in which the test program is stored are as follows from the address a to the input / output terminal (I / O).
Is stored, a program for testing the serial input / output terminal (SIO) is stored at address b, a program for testing RAM at address c is stored, a program for testing the ALU at address d is stored, Digital / analog converter (DAC) from address e
Is stored, a program for testing the analog / digital converter (ADC) from address f is stored, and the other test programs up to address 3FFE are stored in the same manner. Further, the details of the second storage area of the ROM (1) in which the jump program is stored, the program for jumping to the head address in which the normal operation program is stored in the address 3FFO is stored,
Programs for jumping to addresses a to o are stored at addresses 3FF1 to 3FFF, respectively.

Now, returning to FIG. 1 again, (2-1) to (2
-4) is an output terminal for outputting the data O _{1 to} O ₄ which are arithmetically processed in the microcomputer after the microcomputer is released from reset. Further, the output terminals (2-1) to (2-4) are the second terminals of the ROM (1) while the microcomputer is reset.
It also functions as an input terminal for applying address data (test data) for accessing the storage area. Where R
Since the address of OM (1) ends at address 3FFF, R
The address data of OM (1) is composed of 14 bits. However, in the second storage area (addresses 3FF0 to 3FFF) of the ROM (1), only the lower 4 bits of the address data change. Therefore,
According to the number of changed bits (4) of the address data in the second storage area of the ROM (1), four output terminals (2-1) to
(2-4) is also used as test data input.

(3-1) to (3-4) are buffers (first
Gate means) and outputs data O _{1 to} O ₄ to output terminals (2-
1) to (2-4). The resistors (4-1) to (4-4) are connected to the output terminals (2-1) to (2
-4) and the outputs of the buffers (3-1) to (3-4). The resistors (4-1) to (4-4) are
When the microcomputer is in the reset-released state and data can be output from the output terminals (2-1) to (2-4), the test data is output to the output terminals (2-1) to (2-4). It serves to prevent the transistors constituting the internal circuit of the microcomputer from being destroyed when applied by mistake. The resistance (4-1)
(4-4) is about 100Ω. (5-1) ~
(5-4) is an NMOS transistor, the drain is connected to the output terminals (2-1) to (2-4), and the source is grounded. The NMOS transistors (5-1) to
(5-4) operates as a pull-down resistor having a resistance value of several KΩ when turned on. (6-1) to (6-4)
Is an AND gate (second gate means), and one input terminal is connected to the control terminals of the buffers (3-1) to (3-4) and the gates of the NMOS transistors (5-1) to (5-4). The other input terminal is connected to the drains of the NMOS transistors (5-1) to (5-4).

(7) is a D flip-flop,
A reset signal RST is applied to the (data) terminal, and C
The clock CK is applied to the (clock) terminal, and the reset signal RST is inverted and applied to the R (reset) terminal. Then, the Q (output) of the D flip-flop (7)
The latch clock LCK is generated from the terminal. Similarly,
(8) is also a D flip-flop (gate control signal generating means), the latch clock LCK which is the Q terminal output of the D flip-flop (7) at the previous stage is applied to the D terminal, and the clock CK is applied to the C terminal. Then, the reset signal RST is inverted and applied to the R terminal. An internal reset signal IRST for resetting or resetting the internal circuit of the microcomputer is output from the Q terminal of the D flip-flop (8), and the gate control signal CTL is output from the * Q (inverted output) terminal. Is output.
Here, the gate control signal CTL is the buffer (3-1).
~ (3-4) control terminal, NMOS transistor (5-
1) to (5-4) gates, and an AND gate (6-
1) to (6-4) are applied to one of the input terminals to control the operation of each of these elements. That is, the gate control signal CT
When L is low level, buffers (3-1) to (3-4)
Operates, and NMOS transistors (5-1) to (5-
4) turns off, and AND gates (6-1) to (6-4) close the gates. Therefore, the output terminals (2-1) to (2-
In 4), the data O _{1 to} O ₄ can be output. On the contrary, when the gate control signal CTL is at the high level, the buffers (3-1) to (3-4) stop operating, the NMOS transistors (5-1) to (5-4) turn on, and the AND gate (6-1) to (6-4) open the gate. Therefore, the output terminals (2-1) to (2-4) are ready for inputting test data (except when all 4 bits are "0"). Specifically, when the test data is not input in a state where the output terminals (2-1) to (2-4) can input the test data, the NMOS transistors (5-1) to (5-1) to
Since (5-4) functions as a pull-down resistor, A
"0" is output from all of the ND gates (6-1) to (6-4). On the other hand, if the test data is input, A
The test data is directly output from the ND gates (6-1) to (6-4).

Reference numeral (9) is a data holding output circuit (data holding output means), and AND gates (6-1) to (6-).
The output of 4) is held and output. Specifically, the data holding output circuit (9) is provided with four D flip-flops corresponding to the AND gates (6-1) to (6-4), respectively, and the data input D0 to D3. Are respectively connected to the outputs of AND gates (6-1) to (6-4). Therefore, after the reset signal RST applied to the R terminal of the data holding output circuit (9) rises to the high level and the data holding output circuit (9) is released from reset, C of the data holding output circuit (9) is released. When the latch clock LCK is applied to the terminal, the data holding output circuit (9) holds and outputs the 4-bit test data output from the AND gates (6-1) to (6-4). .

(10) is a program counter (address counter means) which generates address data A0 to A13 for accessing the address of the ROM (1). The program counter (10) is configured such that when it is reset by applying a low-level reset signal RST to the R terminal, the address data indicating the address 3FF0 is preset. (11) is an AND gate, one input terminal of which is an internal reset signal IRST
Is applied, and the clock CK is applied to the other input terminal. That is, the AND gate (11) opens the gate at the same time when the microcomputer is released from reset, and starts outputting the clock CK. Therefore, in the program counter (10), the clock CK is applied to the C terminal at the same time when the microcomputer is released from reset, and the value is incremented by +1 in synchronization with the clock CK.

(12) is a comparison circuit (comparison means),
4-bit output data from the output terminals Q0 to Q3 of the data holding output circuit (9) and the program counter (10)
Lower 4 bits A0-A of the address data output from
3 is compared with each other, and a coincidence detection pulse is generated when the two coincide with each other. (13) is an AND gate, which is applied with the higher 10 bits A4 to A13 of the 14-bit address data output from the program counter (10) and outputs the logical product. The output of the AND gate (13) is connected to the ENB (enable) terminal of the comparison circuit (12). That is, the program counter (10) is the second storage area (3FF) of the ROM (1).
The output of the AND gate (13) becomes "1" only when the contents of the address data for accessing (0-3FFF addresses) are set, and the output of the AND gate (13) enables the comparison circuit (12). The comparison operation can be executed. Reference numeral (14) is an AND gate, in which the coincidence detection pulse is applied to one input terminal and the clock CK is applied to the other input terminal. That is, the AND gate (14) outputs a coincidence detection pulse in synchronization with the clock CK.

(15) is an instruction output circuit (instruction output means)
That is, the output control of the program data of the ROM (1) is performed. The command output circuit (15) has INH
An (inhibition) terminal and an OE (output enable) terminal are provided. (16) is an AND gate to which the address data A0 to A13 are inverted and applied. That is, the AND gate (16) is connected to the program counter (1
Only when the value of 0) reaches the address 0000, "1" is output, and the instruction output circuit (15) is set to the data output enabled state. Then, the instruction output circuit (15) reads from the ROM (1) when the coincidence detection pulse is not applied to the C terminal in the inhibit state in which the “1” output of the AND gate (13) is applied to the INH terminal. The operation of prohibiting the input of the selected 16-bit program data ID0 to ID15 is performed, and the data of all "0" is output from the output terminals Q0 to Q15. On the contrary, when the coincidence detection pulse is applied to the C terminal in the prohibition state in which the “1” output of the AND gate (13) is applied to the INH terminal, the command output circuit (15) outputs from the ROM (1). Read program data I
Holds D0 to ID15 but outputs terminals Q0 to Q1
The data of all "0" is output from 5. Further, the instruction output circuit (15) releases the prohibition state because the output of the AND gate (13) becomes "0", and the AND gate (1
When the output of 6) becomes "1" and the output becomes possible, the program data ID held in synchronization with the coincidence detection pulse
0 to ID15 are output from the output terminals Q0 to Q15. After that, when the output of the AND gate (16) becomes "0",
The instruction output circuit (15) directly outputs the program data ID0 to ID15 read from the ROM (1). Then, the internal circuit of the microcomputer operates according to the program data ID0 to ID15 output from the instruction output circuit (15).

Here, FIG. 3 shows a specific circuit of the instruction output circuit (15) which constitutes a part of this embodiment. Figure 3
In (17) is a latch circuit, L (latch)
Each bit of the program data ID0 to ID15 read from the ROM (1) is applied to the terminal, and the coincidence detection pulse is applied to the C terminal. (18) (19) is AN
D gate, (20) is a NOR gate, and these AN
A data switching circuit is composed of the D gates (18) and (19) and the NOR gate (20). AND gate (18)
The output of the AND gate (16) is applied to one input terminal of the
The output of the AND gate (16) is directly applied to one input terminal of 9). That is, AND gate (18)
(19) complementarily opens the gate. Further, the respective bits of the program data ID0 to ID15 read from the ROM (1) are applied to the other input terminal of the AND gate (18) as they are, and the latch circuit is applied to the other input terminal of the AND gate (19). The Q terminal output of (17) is applied. Further, (22) is a NOR gate, the output of the AND gate (13) is applied to one input terminal, the output of the NOR gate (20) is applied to the other input terminal, and each bit of data is output from the output terminal. Is output. The latch circuit (17), the AND gates (18) and (19), and the NOR gates (20) and (22) have program data ID0 to I, respectively.
It is assumed that the same number as the number of bits of D15 is provided.

The operation of FIG. 3 will be described below. First, AN
When the output of the D gate (13) becomes "1" and is applied to the INH terminal, the NOR gate (22) changes to the NOR gate (2).
It becomes unresponsive to the output change of 0). That is, "0" is output from the NOR gate (22) regardless of the output of the program data ID0 to ID15, the coincidence detection pulse, and the AND gate (16). Further, even when the "1" output of the AND gate (13) is applied to the INH terminal, if the coincidence detection pulse is applied to the C terminal of the latch circuit (17), the latch circuit (17) outputs to the latch circuit (17). Program data I
D0 to ID15 are held. However, NOR gate (2
The output of 2) remains "0" for all 16 bits. After that, the output of the AND gate (13) becomes "0" and INH
When applied to the terminals, the NOR gate (22) will generate an output according to the output change of the NOR gate (20). For example, when the output of the AND gate (16) becomes "1" and is applied to the OE terminal, the content held in the latch circuit (17) is output from the NOR gate (22). Also, the output of the AND gate (16) becomes "0", and OE
When applied to the terminals, the program data ID0 to ID15 read from the ROM (1) are directly output from the NOR gate (22).

The operation of FIG. 1 will be described below with reference to the time chart of FIG. First, when the power supply Vdd of the microcomputer itself is turned on, the oscillation signal which is the source of the clock CK starts to oscillate toward a predetermined oscillation frequency. The clock CK starts to be output via a clock generator (not shown) when the oscillation signal becomes stable. Now,
At time t0, the reset signal RST is at the low level and the program counter (10) is in the reset state, that is, the value of the program counter (10) is preset to the address 3FF0 by hardware. Therefore,
ROM (1) is accessed at address 3FF0,
From (1), the program data for jumping to the address 0010 is read. At this time, since the output of the AND gate (13) that calculates the logical product of the upper 10 bits A4 to A13 of the address data is at high level, the INH terminal input of the instruction output circuit (15) becomes high level and the instruction The output circuit (15) is in a state in which data output is prohibited, and all 16-bit outputs are "0". In this embodiment, if all the 16-bit data output from the instruction output circuit (15) are "0", the microcomputer is set so as not to operate (NO.
P).

Before the reset signal RST rises to a high level, the lower 4 bits "0010" of the address data 3FF2 are applied to the output terminals (2-1) to (2-4) as test data. Then, since the NMOS transistors (5-1) to (5-4) are turned on and the AND gates (6-1) to (6-4) open the gates, the AND gate (6-1). ~ (6-4)
Outputs the lower 4 bits "0010".

After that, when the reset signal RST rises to the high level, the data holding output circuit (9), the D flip-flops (7) and (8), and the program counter (10).
Is released from reset. Then, at the time t1, when the clock CK rises, the D flip-flop (7) outputs the high-level latch clock LCK, and the lower 4 bits “0” are synchronized with the rising of the latch clock LCK.
010 ”is held in the data holding output circuit (9) and is output.

At time t2, when the clock CK rises again, the gate control signal output from the * Q terminal of the D flip-flop (8) becomes low level, that is, NM.
The OS transistors (5-1) to (5-4) are turned off, the AND gates (6-1) to (6-4) close the gates, and the buffers (3-1) to (3-4) operate. Therefore, the output terminals (2-1) to (2-4) can output the data O _{1 to} O ₄ from the test data input state (NORM).
AL OUTPUT). On the other hand, since the internal reset signal IRST goes high, the internal circuit of the microcomputer is released from reset. Also, AND
The gate (11) is a high level internal reset signal IRS
Since the gate is opened by T, the program counter (10)
The clock CK starts to be applied to the C terminal of, and the value of the program counter (10) is incremented by 1 to 3FF.
At the address 1, the program data for jumping to the address a is read from the ROM (1). However, the instruction output circuit (15) is still in a state in which data of all 16 bits is "0".

Next, at time t3, when the clock CK rises again, the value of the program counter (10) becomes +1.
Incremented to address 3FF2, ROM
The program data for jumping from (1) to address b is read. At this time, the lower 4 bits “0010” of the address data indicating the address 3FF2 are applied to the comparison circuit (12) through the output terminals Q _{3 to} Q _{0 of the} data holding output circuit (9), and The lower 4 bits of the value of the program counter (10), that is, 3FF
The lower 4 bits "0010" of address 2 are applied. Therefore, the comparison circuit (12) outputs a coincidence detection pulse. This coincidence detection pulse is output from the AND gate (14) for the time period overlapping with the generation period of the clock CK,
It is applied to the C terminal of the command output circuit (15). Therefore,
The instruction output circuit (15) holds program data for jumping to the address b of the ROM (1). But,
Data of which all 16 bits are "0" are still read from the instruction output circuit (15), and the microcomputer does not operate.

Then, the program counter (10) continues to increment, and the program counter (1
When the clock CK rises at time t4 from the state in which the value of 0) is the address data representing the 3FFF address, the value of the program counter (10) is incremented by +1 to become the address data representing the 0000 address.
Then, the output of the AND gate (13) becomes low level, the comparison operation of the comparison circuit (12) is prohibited, and the instruction output circuit (15) is released from the state of outputting all 16-bit data "0". It At the same time, the output of the AND gate (16) becomes high level only during the period when the value of the program counter (10) is the address data indicating the address 0000, and the instruction output circuit (15) holds it in the instruction output circuit (15). The program data for jumping to the previously-addressed b is output.

At time t5, when the clock CK rises, the value of the program counter (10) becomes address data representing the address b, and the ROM (1) changes the serial input / output terminal SIO stored at the address b and thereafter. Program data for testing is read out, and this program data is directly output from the instruction output circuit (15) and decoded inside the microcomputer. This operation is b ~ (c
By repeating up to the address -1), the test of the serial input / output terminal SIO can be executed.

According to the present invention which operates as described above, the output terminals (2-1) to (2-4) are also used as test data input terminals while the microcomputer is reset, and the microcomputer is also used. After it is released from reset, it can be used as a data output terminal in the test mode and the normal mode. Therefore, the number of output terminals provided in the microcomputer can be minimized, and the chip area can be reduced. Furthermore, it will be possible to support mass production.

[0030]

According to the present invention, the output terminal is also used as the test data input terminal while the integrated circuit is being reset, and the data in the test mode and the normal mode after the integrated circuit is released from the reset state. Can be used as the output terminal of. Therefore, the number of output terminals provided in the integrated circuit can be minimized, and the chip area can be reduced. Further, there are advantages such as being able to cope with mass production.

[Brief description of drawings]

FIG. 1 is a diagram showing a test circuit of an integrated circuit of the present invention.

FIG. 2 is a diagram showing a program layout diagram of a ROM used in the present invention.

FIG. 3 is a diagram showing a specific circuit of an instruction output circuit used in the present invention.

FIG. 4 is a time chart showing the operation of the present invention.

[Explanation of symbols]

(1) ROM (2-1) to (2-4) output terminals (3-1) to (3-4) buffer (6-1) to (6-4) AND gate (8) D flip-flop (9) Data holding output circuit (10) Program counter (12) Comparison circuit (15) Command output circuit

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 11/22 G06F 9/06 G01R 31/28 JISST file (JOIS)

Claims (3)

(57) [Claims] 1. A test circuit of an integrated circuit using a plurality of output terminals for outputting data as input terminals for applying test data, wherein a plurality of test instructions for executing each test are stored in a first storage area. Memory means in which a plurality of jump instructions for accessing at least the first storage area are stored in the second storage area, first gate means for outputting the data from the output terminal, and the output terminal Second gate means for inputting address data for accessing the second memory area of the memory means into the integrated circuit as the test data from the first gate means while the integrated circuit is reset. And the second gate means are operated to output the test data, and the integrated circuit is reset. And a gate control signal generating means for generating a gate control signal for operating the first gate means to output the data and stopping the operation of the second gate means, and resetting the integrated circuit. A test data holding and outputting means for holding and outputting the test data outputted from the second gate means while the integrated circuit is being reset; and a second storage of the memory means while the integrated circuit is being reset. The address data representing the start address of the area is preset, and after the reset of the integrated circuit is released, the address data representing the start address of the second storage area of the memory means is incremented to access the memory means. Counter means, output contents of the test data holding output means and counting of the address counter means Comparing means for comparing the contents and generating a coincidence detection signal when the output contents and the counted contents coincide; and a predetermined address of the second storage area of the memory means only when the coincidence detection signal occurs Command output means for outputting the read jump command, wherein the output terminal serves as an input function of the test data while the integrated circuit is reset, and after the integrated circuit is released from reset, A test circuit for an integrated circuit, wherein an output terminal is set to a data output function in a test mode and a normal mode. 2. The integrated circuit according to claim 1, further comprising a pull-down element that pulls down the plurality of output terminals to the same potential by the gate control signal while the integrated circuit is reset. Test circuit. 3. A jump instruction stored at the head address of the second storage area of the memory means is output when the test data is not applied to the output terminal while the integrated circuit is reset. 3. The output from the means, and according to the jump instruction at this time, the value of the address counter means is set to the address of the memory means in which the program instruction for executing the normal operation is stored. Integrated circuit test circuit.